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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Maurice Ma > -----Original Message----- > From: Patrick Rudolph > Sent: Monday, February 7, 2022 2:01 > To: devel@edk2.groups.io > Cc: Ni, Ray ; Ma, Maurice ; You, > Benjamin ; Dong, Guo > Subject: [edk2-platform][PATCH] UefiPayloadPkg: Fix PciHostBridgeLib >=20 > On modern platforms with TBT devices the coreboot resource allocator > opens large PCI bridge MMIO windows above 4GiB to place hotplugable PCI > BARs there as they won't fit below 4GiB. In addition modern GPGPU devices > have very big PCI bars that doesn't fit below 4GiB. >=20 > The PciHostBridgeLib made lots of assumptions about the coreboot resource > allocator that were not verified at runtime and are no longer true. >=20 > Remove all of the 'coreboot specific' code and implement the same logic a= s > OvmfPkg's ScanForRootBridges. >=20 > Fixes assertion > "ASSERT [PciHostBridgeDxe] Bridge->Mem.Limit < 0x0000000100000000ULL". >=20 > Tested with coreboot as bootloader on platforms that have PCI resources > above 4GiB and on platforms that don't have resources above 4GiB. >=20 > Signed-off-by: Patrick Rudolph > --- > UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 137 +++= - > ---------------- > 1 file changed, 18 insertions(+), 119 deletions(-) >=20 > diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport= .c > b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > index bf2d10f4bf..8a890b6b53 100644 > --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > @@ -18,92 +18,6 @@ > #include #include "PciHostBridge.h" -/**- Adjust the > collected PCI resource.-- @param[in] Io IO aperture.-- @= param[in] > Mem MMIO aperture.-- @param[in] MemAbove4G MMIO > aperture above 4G.-- @param[in] PMem Prefetchable MMIO > aperture.-- @param[in] PMemAbove4G Prefetchable MMIO aperture > above 4G.-**/-VOID-AdjustRootBridgeResource (- IN > PCI_ROOT_BRIDGE_APERTURE *Io,- IN PCI_ROOT_BRIDGE_APERTURE > *Mem,- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,- IN > PCI_ROOT_BRIDGE_APERTURE *PMem,- IN PCI_ROOT_BRIDGE_APERTURE > *PMemAbove4G- )-{- UINT64 Mask;-- //- // For now try to downgrade > everything into MEM32 since- // - coreboot does not assign resource abov= e > 4GB- // - coreboot might allocate interleaved MEM32 and PMEM32 > resource- // in some cases- //- if (PMem->Base < Mem->Base) {- Me= m- > >Base =3D PMem->Base;- }-- if (PMem->Limit > Mem->Limit) {- Mem->Lim= it > =3D PMem->Limit;- }-- PMem->Base =3D MAX_UINT64;- PMem->Limit =3D 0;-= - if > (MemAbove4G->Base < 0x100000000ULL) {- if (MemAbove4G->Base < > Mem->Base) {- Mem->Base =3D MemAbove4G->Base;- }-- if > (MemAbove4G->Limit > Mem->Limit) {- Mem->Limit =3D MemAbove4G- > >Limit;- }-- MemAbove4G->Base =3D MAX_UINT64;- MemAbove4G->Limi= t > =3D 0;- }-- if (PMemAbove4G->Base < 0x100000000ULL) {- if > (PMemAbove4G->Base < Mem->Base) {- Mem->Base =3D PMemAbove4G- > >Base;- }-- if (PMemAbove4G->Limit > Mem->Limit) {- Mem->Limit= =3D > PMemAbove4G->Limit;- }-- PMemAbove4G->Base =3D MAX_UINT64;- > PMemAbove4G->Limit =3D 0;- }-- //- // Align IO resource at 4K bounda= ry- //- > Mask =3D 0xFFFULL;- Io->Limit =3D ((Io->Limit + Mask) & ~Mask) - 1;= - if (Io- > >Base !=3D MAX_UINT64) {- Io->Base &=3D ~Mask;- }-- //- // Align ME= M > resource at 1MB boundary- //- Mask =3D 0xFFFFFULL;- Mem->Limit = =3D > ((Mem->Limit + Mask) & ~Mask) - 1;- if (Mem->Base !=3D MAX_UINT64) {- > Mem->Base &=3D ~Mask;- }-}- /** Probe a bar is existed or not. @@ -114= ,28 > +28,24 @@ AdjustRootBridgeResource ( > STATIC VOID PcatPciRootBridgeBarExisted (- IN UINT64 Address,+ IN > UINTN Address, OUT UINT32 *OriginalValue, OUT UINT32 *Value ) {= - > UINTN PciAddress;-- PciAddress =3D (UINTN)Address;- // // Preserve = the > original value //- *OriginalValue =3D PciRead32 (PciAddress);+ *Origi= nalValue > =3D PciRead32 (Address); // // Disable timer interrupt while the BAR= is > probed // DisableInterrupts (); - PciWrite32 (PciAddress, 0xFFFFFFFF= );- > *Value =3D PciRead32 (PciAddress);- PciWrite32 (PciAddress, *OriginalVal= ue);+ > PciWrite32 (Address, 0xFFFFFFFF);+ *Value =3D PciRead32 (Address);+ > PciWrite32 (Address, *OriginalValue); // // Enable interrupt@@ -179,= 9 > +89,7 @@ PcatPciRootBridgeParseBars ( > IN UINTN BarOffsetEnd, IN PCI_ROOT_BRIDGE_APERTU= RE *Io, > IN PCI_ROOT_BRIDGE_APERTURE *Mem,- IN > PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,- IN > PCI_ROOT_BRIDGE_APERTURE *PMem,- IN PCI_ROOT_BRIDGE_APERTURE > *PMemAbove4G+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G ) > {@@ -246,11 +154,7 @@ PcatPciRootBridgeParseBars ( > // Length =3D ((~Length) + 1) & 0xffffffff; - = if ((Value & BIT3) =3D=3D > BIT3) {- MemAperture =3D PMem;- } else {- = MemAperture =3D > Mem;- }+ MemAperture =3D Mem; } else { = // // > 64bit@@ -269,8 +173,8 @@ PcatPciRootBridgeParseBars ( > Length =3D LShiftU64 (1ULL, LowBit); } - = if ((Value & BIT3) =3D=3D > BIT3) {- MemAperture =3D PMemAbove4G;+ if (Base < BAS= E_4GB) {+ > MemAperture =3D Mem; } else { MemAperture =3D > MemAbove4G; }@@ -291,6 +195,8 @@ PcatPciRootBridgeParseBars ( > } } +STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture =3D > { MAX_UINT64, 0 };+ /** Scan for all root bridges in platform. @@ -317,= 8 > +223,6 @@ ScanForRootBridges ( > PCI_ROOT_BRIDGE_APERTURE Io; PCI_ROOT_BRIDGE_APERTURE Mem; > PCI_ROOT_BRIDGE_APERTURE MemAbove4G;- > PCI_ROOT_BRIDGE_APERTURE PMem;- PCI_ROOT_BRIDGE_APERTURE > PMemAbove4G; PCI_ROOT_BRIDGE_APERTURE *MemAperture; > PCI_ROOT_BRIDGE *RootBridges; UINTN BarOf= fsetEnd;@@ - > 338,9 +242,7 @@ ScanForRootBridges ( > ZeroMem (&Io, sizeof (Io)); ZeroMem (&Mem, sizeof (Mem)); > ZeroMem (&MemAbove4G, sizeof (MemAbove4G));- ZeroMem (&PMem, > sizeof (PMem));- ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));- > Io.Base =3D Mem.Base =3D MemAbove4G.Base =3D PMem.Base =3D > PMemAbove4G.Base =3D MAX_UINT64;+ Io.Base =3D Mem.Base =3D > MemAbove4G.Base =3D MAX_UINT64; // // Scan all the PCI devices on= the > primary bus of the PCI root bridge //@@ -446,16 +348,17 @@ > ScanForRootBridges ( > // // Get the Prefetchable Memory range that the PP= B is > decoding+ // and merge it into Memory range // = Value =3D > Pci.Bridge.PrefetchableMemoryBase & 0x0f; Base =3D > ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16; Lim= it =3D > (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0) = << 16) | > 0xfffff;- MemAperture =3D &PMem;+ MemAperture =3D &Mem;= if > (Value =3D=3D BIT0) { Base |=3D LShiftU64 > (Pci.Bridge.PrefetchableBaseUpper32, 32); Limit |=3D LSh= iftU64 > (Pci.Bridge.PrefetchableLimitUpper32, 32);- MemAperture =3D > &PMemAbove4G;+ MemAperture =3D &MemAbove4G; } = if > ((Base > 0) && (Base < Limit)) {@@ -513,9 +416,7 @@ ScanForRootBridges ( > BarOffsetEnd, &Io, &Mem,- &MemAbo= ve4G,- > &PMem,- &PMemAbove4G+ &MemAbove4G ); = //@@ - > 593,8 +494,6 @@ ScanForRootBridges ( > ); ASSERT (RootBridges !=3D NULL); - > AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, > &PMemAbove4G);- InitRootBridge ( Attributes, Attrib= utes,@@ - > 604,8 +503,8 @@ ScanForRootBridges ( > &Io, &Mem, &MemAbove4G,- &PMem,- > &PMemAbove4G,+ &mNonExistAperture,+ &mNonExistAperture, > &RootBridges[*NumberOfRootBridges] ); > RootBridges[*NumberOfRootBridges].ResourceAssigned =3D TRUE;-- > 2.34.1