* Re: [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll [not found] <17A7512BA8BD522D.25044@groups.io> @ 2024-01-05 2:20 ` Ni, Ray 2024-01-05 2:37 ` Zhi Jin 0 siblings, 1 reply; 3+ messages in thread From: Ni, Ray @ 2024-01-05 2:20 UTC (permalink / raw) To: devel@edk2.groups.io, Jin, Zhi Cc: Laszlo Ersek, Kumar, Rahul R, Gerd Hoffmann, Wu, Jiaxin Zhi, With your patch, 1. SMM entry(code) and SmmSaveState region (data) are changed to correct paging attributes. 2. FlushTlb() is removed after the changing. 3. FlushTlb() is updated to flush in parallel. My concern is about #2. Can you explain a bit why FlushTlb() can be removed after changing paging attributes in #1? Thanks, Ray > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Jin, Zhi > Sent: Friday, January 5, 2024 10:04 AM > To: devel@edk2.groups.io > Cc: Jin, Zhi <zhi.jin@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo Ersek > <lersek@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd > Hoffmann <kraxel@redhat.com>; Wu, Jiaxin <jiaxin.wu@intel.com> > Subject: [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize > PatchSmmSaveStateMap and FlushTlbForAll > > PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState > region (data) for each core, which can be improved to flush TLB once > after all the memory entries have been patched. > FlushTlbForAll flushes TLB for each core in serial, which can be > improved to flush TLB in parrallel. > > Cc: Ray Ni <ray.ni@intel.com> > Cc: Laszlo Ersek <lersek@redhat.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Cc: Gerd Hoffmann <kraxel@redhat.com> > Cc: Jiaxin Wu <jiaxin.wu@intel.com> > Signed-off-by: Zhi Jin <zhi.jin@intel.com> > --- > .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 95 > ++++++++++++------- > 1 file changed, 63 insertions(+), 32 deletions(-) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index 15f998e501..d4066436f5 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -547,17 +547,14 @@ FlushTlbForAll ( > VOID > ) > { > - UINTN Index; > - > FlushTlbOnCurrentProcessor (NULL); > - > - for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { > - if (Index != gSmst->CurrentlyExecutingCpu) { > - // Force to start up AP in blocking mode, > - SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL); > - // Do not check return status, because AP might not be present in some > corner cases. > - } > - } > + InternalSmmStartupAllAPs ( > + (EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor, > + 0, > + NULL, > + NULL, > + NULL > + ); > } > > /** > @@ -799,71 +796,105 @@ PatchSmmSaveStateMap ( > UINTN TileCodeSize; > UINTN TileDataSize; > UINTN TileSize; > + UINTN PageTableBase; > > - TileCodeSize = GetSmiHandlerSize (); > - TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); > - TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + > sizeof (SMRAM_SAVE_STATE_MAP); > - TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); > - TileSize = TileDataSize + TileCodeSize - 1; > - TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); > + TileCodeSize = GetSmiHandlerSize (); > + TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); > + TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + > sizeof (SMRAM_SAVE_STATE_MAP); > + TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); > + TileSize = TileDataSize + TileCodeSize - 1; > + TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); > + PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > > DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n")); > for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) { > // > // Code > // > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + TRUE, > + NULL > ); > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + FALSE, > + NULL > ); > > // > // Data > // > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + > TileCodeSize, > TileSize - TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + FALSE, > + NULL > ); > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + > TileCodeSize, > TileSize - TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + TRUE, > + NULL > ); > } > > // > // Code > // > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + TRUE, > + NULL > ); > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + FALSE, > + NULL > ); > > // > // Data > // > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET + TileCodeSize, > SIZE_32KB - TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + FALSE, > + NULL > ); > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET + TileCodeSize, > SIZE_32KB - TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + TRUE, > + NULL > ); > } > > -- > 2.39.2 > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113206): https://edk2.groups.io/g/devel/message/113206 Mute This Topic: https://groups.io/mt/103535844/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll 2024-01-05 2:20 ` [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll Ni, Ray @ 2024-01-05 2:37 ` Zhi Jin 0 siblings, 0 replies; 3+ messages in thread From: Zhi Jin @ 2024-01-05 2:37 UTC (permalink / raw) To: Ni, Ray, devel@edk2.groups.io Cc: Laszlo Ersek, Kumar, Rahul R, Gerd Hoffmann, Wu, Jiaxin Thanks for the comments, Ray. It is a mistake to remove the FlushTlb() in this patch. I will send out the patch v2. BRs Zhi Jin -----Original Message----- From: Ni, Ray <ray.ni@intel.com> Sent: Friday, January 05, 2024 10:21 AM To: devel@edk2.groups.io; Jin, Zhi <zhi.jin@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Wu, Jiaxin <jiaxin.wu@intel.com> Subject: RE: [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll Zhi, With your patch, 1. SMM entry(code) and SmmSaveState region (data) are changed to correct paging attributes. 2. FlushTlb() is removed after the changing. 3. FlushTlb() is updated to flush in parallel. My concern is about #2. Can you explain a bit why FlushTlb() can be removed after changing paging attributes in #1? Thanks, Ray > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Jin, Zhi > Sent: Friday, January 5, 2024 10:04 AM > To: devel@edk2.groups.io > Cc: Jin, Zhi <zhi.jin@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo Ersek > <lersek@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd > Hoffmann <kraxel@redhat.com>; Wu, Jiaxin <jiaxin.wu@intel.com> > Subject: [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize > PatchSmmSaveStateMap and FlushTlbForAll > > PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState > region (data) for each core, which can be improved to flush TLB once > after all the memory entries have been patched. > FlushTlbForAll flushes TLB for each core in serial, which can be > improved to flush TLB in parrallel. > > Cc: Ray Ni <ray.ni@intel.com> > Cc: Laszlo Ersek <lersek@redhat.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Cc: Gerd Hoffmann <kraxel@redhat.com> > Cc: Jiaxin Wu <jiaxin.wu@intel.com> > Signed-off-by: Zhi Jin <zhi.jin@intel.com> > --- > .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 95 > ++++++++++++------- > 1 file changed, 63 insertions(+), 32 deletions(-) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index 15f998e501..d4066436f5 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -547,17 +547,14 @@ FlushTlbForAll ( > VOID > ) > { > - UINTN Index; > - > FlushTlbOnCurrentProcessor (NULL); > - > - for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { > - if (Index != gSmst->CurrentlyExecutingCpu) { > - // Force to start up AP in blocking mode, > - SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL); > - // Do not check return status, because AP might not be present in some > corner cases. > - } > - } > + InternalSmmStartupAllAPs ( > + (EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor, > + 0, > + NULL, > + NULL, > + NULL > + ); > } > > /** > @@ -799,71 +796,105 @@ PatchSmmSaveStateMap ( > UINTN TileCodeSize; > UINTN TileDataSize; > UINTN TileSize; > + UINTN PageTableBase; > > - TileCodeSize = GetSmiHandlerSize (); > - TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); > - TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + > sizeof (SMRAM_SAVE_STATE_MAP); > - TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); > - TileSize = TileDataSize + TileCodeSize - 1; > - TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); > + TileCodeSize = GetSmiHandlerSize (); > + TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); > + TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + > sizeof (SMRAM_SAVE_STATE_MAP); > + TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); > + TileSize = TileDataSize + TileCodeSize - 1; > + TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); > + PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > > DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n")); > for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) { > // > // Code > // > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + TRUE, > + NULL > ); > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + FALSE, > + NULL > ); > > // > // Data > // > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + > TileCodeSize, > TileSize - TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + FALSE, > + NULL > ); > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + > TileCodeSize, > TileSize - TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + TRUE, > + NULL > ); > } > > // > // Code > // > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + TRUE, > + NULL > ); > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + FALSE, > + NULL > ); > > // > // Data > // > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET + TileCodeSize, > SIZE_32KB - TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + FALSE, > + NULL > ); > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET + TileCodeSize, > SIZE_32KB - TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + TRUE, > + NULL > ); > } > > -- > 2.39.2 > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113207): https://edk2.groups.io/g/devel/message/113207 Mute This Topic: https://groups.io/mt/103535844/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 3+ messages in thread
* [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll @ 2024-01-05 2:04 Zhi Jin 0 siblings, 0 replies; 3+ messages in thread From: Zhi Jin @ 2024-01-05 2:04 UTC (permalink / raw) To: devel; +Cc: Zhi Jin, Ray Ni, Laszlo Ersek, Rahul Kumar, Gerd Hoffmann, Jiaxin Wu PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState region (data) for each core, which can be improved to flush TLB once after all the memory entries have been patched. FlushTlbForAll flushes TLB for each core in serial, which can be improved to flush TLB in parrallel. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Zhi Jin <zhi.jin@intel.com> --- .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 95 ++++++++++++------- 1 file changed, 63 insertions(+), 32 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 15f998e501..d4066436f5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -547,17 +547,14 @@ FlushTlbForAll ( VOID ) { - UINTN Index; - FlushTlbOnCurrentProcessor (NULL); - - for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { - if (Index != gSmst->CurrentlyExecutingCpu) { - // Force to start up AP in blocking mode, - SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL); - // Do not check return status, because AP might not be present in some corner cases. - } - } + InternalSmmStartupAllAPs ( + (EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor, + 0, + NULL, + NULL, + NULL + ); } /** @@ -799,71 +796,105 @@ PatchSmmSaveStateMap ( UINTN TileCodeSize; UINTN TileDataSize; UINTN TileSize; + UINTN PageTableBase; - TileCodeSize = GetSmiHandlerSize (); - TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); - TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); - TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); - TileSize = TileDataSize + TileCodeSize - 1; - TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); + TileCodeSize = GetSmiHandlerSize (); + TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); + TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); + TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); + TileSize = TileDataSize + TileCodeSize - 1; + TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); + PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n")); for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) { // // Code // - SmmSetMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, TileCodeSize, - EFI_MEMORY_RO + EFI_MEMORY_RO, + TRUE, + NULL ); - SmmClearMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, TileCodeSize, - EFI_MEMORY_XP + EFI_MEMORY_XP, + FALSE, + NULL ); // // Data // - SmmClearMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + TileCodeSize, TileSize - TileCodeSize, - EFI_MEMORY_RO + EFI_MEMORY_RO, + FALSE, + NULL ); - SmmSetMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + TileCodeSize, TileSize - TileCodeSize, - EFI_MEMORY_XP + EFI_MEMORY_XP, + TRUE, + NULL ); } // // Code // - SmmSetMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET, TileCodeSize, - EFI_MEMORY_RO + EFI_MEMORY_RO, + TRUE, + NULL ); - SmmClearMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET, TileCodeSize, - EFI_MEMORY_XP + EFI_MEMORY_XP, + FALSE, + NULL ); // // Data // - SmmClearMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET + TileCodeSize, SIZE_32KB - TileCodeSize, - EFI_MEMORY_RO + EFI_MEMORY_RO, + FALSE, + NULL ); - SmmSetMemoryAttributes ( + ConvertMemoryPageAttributes ( + PageTableBase, + mPagingMode, mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET + TileCodeSize, SIZE_32KB - TileCodeSize, - EFI_MEMORY_XP + EFI_MEMORY_XP, + TRUE, + NULL ); } -- 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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