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From: "Bassa, Damian"
To: "Wu, Hao A" , "devel@edk2.groups.io"
, "Ni, Ray"
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP
Thread-Topic: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check
for RCiEP before looking for RP
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Date: Tue, 31 Aug 2021 17:44:48 +0000
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It refers to access to the root port device that doesn't exist in case we a=
re dealing with RCiEP device.
There can be specific case where RCiEP device has ARI extended capability I=
D (even though it's unsupported in this case).
In such a case PciSearchDevice goes to CreatePciIoDevice through GatherDevi=
ceInfo. And in this case parent is PCI_IO_DEVICE instance created from Crea=
teRootBridge function, which isn't valid PCIe device and doesn't have speci=
fic bus, only a range of buses. In that case enumerator tries to use this i=
nstance to read operation using default 0 bus number, which isn't correct.
Damian
From: Wu, Hao A
Sent: Tuesday, August 31, 2021 6:28 AM
To: devel@edk2.groups.io; Wu, Hao A ; Bassa, Damian ; Ni, Ray
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che=
ck for RCiEP before looking for RP
From: devel@edk2.groups.io > On Behalf Of Wu, Hao A
Sent: Tuesday, August 31, 2021 12:25 PM
To: devel@edk2.groups.io; Bassa, Damian >
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che=
ck for RCiEP before looking for RP
Really sorry,
Could you help to provide more information on the below statement?
"undefined parent register accesses"
Thanks in advance.
Best Regards,
Hao Wu
From: devel@edk2.groups.io > On Behalf Of Bassa, Damian
Sent: Tuesday, August 24, 2021 11:15 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check f=
or RCiEP before looking for RP
Before trying to access parent root port to check ARI capabilities,
enumerator should see if Endpoint device is not Root Complex integrated
to avoid undefined parent register accesses in these cases.
Signed-off-by: Damian Bassa damian.bassa@intel.com
---
.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod=
ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index db1b35f8ef..6451fb8af9 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -2153,6 +2153,7 @@ CreatePciIoDevice (
PCI_IO_DEVICE *PciIoDevice;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
+ PCI_REG_PCIE_CAPABILITY Capability;
PciIoDevice =3D AllocateZeroPool (sizeof (PCI_IO_DEVICE));
if (PciIoDevice =3D=3D NULL) {
@@ -2229,7 +2230,16 @@ CreatePciIoDevice (
return NULL;
}
- if (PcdGetBool (PcdAriSupport)) {
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PciIoDevice->PciExpressCapabilityOffset + OFFSET_OF (PCI_C=
APABILITY_PCIEXP, Capability),
+ 1,
+ &Capability.Uint16
+ );
+
+ if (PcdGetBool (PcdAriSupport) &&
+ Capability.Bits.DevicePortType !=3D PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX=
_INTEGRATED_ENDPOINT) {
//
// Check if the device is an ARI device.
//
--
2.27.0.windows.1
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It refers to access to the root port device that doe=
sn’t exist in case we are dealing with RCiEP device.
There can be specific case where RCiEP device has AR=
I extended capability ID (even though it’s unsupported in this case).
In such a case PciSearchDevice goes to CreatePciIoDe=
vice through GatherDeviceInfo. And in this case parent is PCI_IO_DEVICE ins=
tance created from CreateRootBridge function, which isn’t valid PCIe =
device and doesn’t have specific bus, only
a range of buses. In that case enumerator tries to use this instance to re=
ad operation using default 0 bus number, which isn’t correct.
Damian
From: Wu, Hao A <hao.a.wu@intel.com>
Sent: Tuesday, August 31, 2021 6:28 AM
To: devel@edk2.groups.io; Wu, Hao A <hao.a.wu@intel.com>; Bass=
a, Damian <damian.bassa@intel.com>; Ni, Ray <ray.ni@intel.com><=
br>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator=
to check for RCiEP before looking for RP
Really sorry,
Could you help to provide more information on the be=
low statement?
“undefined parent register accesses”
Thanks in advance.
Before trying to access parent root port to check AR=
I capabilities,
enumerator should see if Endpoint device is not Root=
Complex integrated
to avoid undefined parent register accesses in these=
cases.
Signed-off-by: Damian Bassa
damian.bassa@intel.com
---
.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c &n=
bsp; | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)=
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnume=
ratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c=
index db1b35f8ef..6451fb8af9 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSu=
pport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSu=
pport.c
@@ -2153,6 +2153,7 @@ CreatePciIoDevice (=
PCI_IO_DEVICE &n=
bsp; *PciIoDevice;
EFI_PCI_IO_PROTOCOL *PciIo;<=
/o:p>
EFI_STATUS &nbs=
p; Status;
+ PCI_REG_PCIE_CAPABILITY Capability;
PciIoDevice =3D AllocateZeroPool (=
sizeof (PCI_IO_DEVICE));
if (PciIoDevice =3D=3D NULL) {
@@ -2229,7 +2230,16 @@ CreatePciIoDevice (
return NULL;
}
- if (PcdGetBool (PcdAriSupport)) {=
+ PciIo->Pci.Read (
+ &nb=
sp; PciIo,
+ &nb=
sp; EfiPciIoWidthUint16,
+ &nb=
sp; PciIoDevice->PciExpressCapabilit=
yOffset + OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability),
+ &nb=
sp; 1,
+ &nb=
sp; &Capability.Uint16=
p>
+ &nb=
sp; );
+
+ if (PcdGetBool (PcdAriSupport) &&
+ Capability.Bits.DevicePortType !=
=3D PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {
//
// Check if the device is a=
n ARI device.
//
--
2.27.0.windows.1
Intel Technol=
ogy Poland sp. z o.o.
ul. S=B3owackiego 173 | 80-298 Gd=
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