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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable =0A= =0A= =0A= From: Marc Zyngier =0A= Sent: Tuesday, October 12, 2021 10:27 AM=0A= To: Ashish Singhal =0A= Cc: Shanker Donthineni ; Ard Biesheuvel ; edk2-devel-groups-io ; Leif Lindholm ; Ard Biesheuvel =0A= Subject: Re: [PATCH v2] ArmPkg/TimerDxe: Delay End Of Interrupt Signal =0A= =A0=0A= External email: Use caution opening links or attachments=0A= =0A= =0A= On Tue, 12 Oct 2021 17:11:36 +0100,=0A= Ashish Singhal wrote:=0A= >=0A= > Marc,=0A= >=0A= > What do you suggest should be the proper fix for getting timer=0A= > interrupts even when ISTATUS bit is not set? Should we ignore them=0A= > the way it is in current implementation? I am OK to file a bug for=0A= > this if you think that is a better way to discuss this.=0A= =0A= I don't think there is anything to fix.=0A= =0A= Yes, the order in EDKII is odd. No, changing the order doesn't give=0A= any extra guarantee. Spurious interrupts can always happen. Broken (or=0A= slow) HW and bad emulation are more susceptible to it.=0A= =0A= Now, how often do you see that? On which HW?=0A= =0A= =A0=A0=A0=A0=A0=A0=A0 M.=0A= =0A= --=0A= Without deviation from the norm, progress is not possible.=0A= =0A= Marc,=0A= =0A= We see at least one spurious interrupt after every valid timer interrupt. W= hile both valid and spurious interrupt has the correct source, spurious int= errupt does not have ISTATUS bit set. We are seeing this on Silicon and not= on the emulation platform. Delaying EOI signal to GIC does take the spurio= us interrupt out as with the new flow we clear the interrupt before signali= ng EOI so that next time only a valid interrupt can be triggered and not th= e old interrupt which was still not cleared while signaling EOI to GIC.=0A= =0A= Thanks=0A= Ashish=0A= =0A= Thanks=0A= Ashish=