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Tue, 13 Jul 2021 02:44:33 +0000 From: "Abner Chang" To: Sunil V L , "devel@edk2.groups.io" CC: "sunil.vl@gmail.com" , Liming Gao , Bob Feng , Yuwei Chen , Pete Batard , "Schaefer, Daniel" Subject: Re: [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation Thread-Topic: [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation Thread-Index: AQHXdVU+6qfgOoWwv0mGZQ2U1KaCF6tAN1Fw Date: Tue, 13 Jul 2021 02:44:33 +0000 Message-ID: References: <20210710063114.4278-1-sunilvl@ventanamicro.com> In-Reply-To: <20210710063114.4278-1-sunilvl@ventanamicro.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: ventanamicro.com; dkim=none (message not signed) header.d=none;ventanamicro.com; dmarc=none action=none header.from=hpe.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f7c37392-7229-4223-fcc7-08d945a825be x-ms-traffictypediagnostic: CS1PR8401MB0710: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4714; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Abner Chang > -----Original Message----- > From: Sunil V L [mailto:sunilvl@ventanamicro.com] > Sent: Saturday, July 10, 2021 2:31 PM > To: devel@edk2.groups.io > Cc: sunil.vl@gmail.com; Sunil V L ; Liming Gao > ; Bob Feng ; Yuwei > Chen ; Pete Batard ; Chang, Abner > (HPS SW/FW Technologist) ; Schaefer, Daniel > > Subject: [PATCH] BaseTools GenFw: Add support for > R_RISCV_PCREL_LO12_S relocation >=20 > Ref: > INVALID URI REMOVED > d=3D3459__;!!NpxR!zrGTHXfzHm6WE6VZ2rABQ0yFTgu7frG5J213efKk- > TmOGcp_9TSXv8E3b_XlNzo$ >=20 > This patch adds support for R_RISCV_PCREL_LO12_S relocation type. > The logic is same as existing R_RISCV_PCREL_LO12_I relocation > except the difference between load vs store instruction formats. >=20 > Signed-off-by: Sunil V L >=20 > Cc: Liming Gao > Cc: Bob Feng > Cc: Yuwei Chen > Cc: Pete Batard > Cc: Abner Chang > Cc: Daniel Schaefer > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 55 > +++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) >=20 > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > b/BaseTools/Source/C/GenFw/Elf64Convert.c > index 3d7e20aaff..0bb3ead228 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -557,6 +557,60 @@ WriteSectionRiscV64 ( > Value =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > break; >=20 > + case R_RISCV_PCREL_LO12_S: > + if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && > mRiscVPass1SymSecIndex !=3D 0) { > + int i; > + Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > + > + Value =3D ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5); > + Value =3D (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5))); > + > + if(Value & (RISCV_IMM_REACH/2)) { > + Value |=3D ~(RISCV_IMM_REACH-1); > + } > + Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + > mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > + > + if(-2048 > (INT32)Value) { > + i =3D (((INT32)Value * -1) / 4096); > + Value2 -=3D i; > + Value +=3D 4096 * i; > + if(-2048 > (INT32)Value) { > + Value2 -=3D 1; > + Value +=3D 4096; > + } > + } > + else if( 2047 < (INT32)Value) { > + i =3D (Value / 4096); > + Value2 +=3D i; > + Value -=3D 4096 * i; > + if(2047 < (INT32)Value) { > + Value2 +=3D 1; > + Value -=3D 4096; > + } > + } > + > + // Update the IMM of SD instruction > + // > + // |31 25|24 20|19 15|14 12 |11 7|6 0| > + // |-------------------------------------------|-------| > + // |imm[11:5] | rs2 | rs1 | funct3 |imm[4:0] | opcode| > + // --------------------------------------------------- > + > + // First Zero out current IMM > + *(UINT32 *)Targ &=3D ~0xfe000f80; > + > + // Update with new IMM > + *(UINT32 *)Targ |=3D (RV_X(Value, 5, 7) << 25); > + *(UINT32 *)Targ |=3D (RV_X(Value, 0, 5) << 7); > + > + // Update previous instruction > + *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | > (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > + } > + mRiscVPass1Sym =3D NULL; > + mRiscVPass1Targ =3D NULL; > + mRiscVPass1SymSecIndex =3D 0; > + break; > + > case R_RISCV_PCREL_LO12_I: > if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && > mRiscVPass1SymSecIndex !=3D 0) { > int i; > @@ -1587,6 +1641,7 @@ WriteRelocations64 ( > case R_RISCV_PCREL_HI20: > case R_RISCV_GOT_HI20: > case R_RISCV_PCREL_LO12_I: > + case R_RISCV_PCREL_LO12_S: > break; >=20 > default: > -- > 2.32.0