From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.23195.1598546020457496666 for ; Thu, 27 Aug 2020 09:33:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=VxZn2WoD; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0508fb1276=abner.chang@hpe.com) Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07RGXeEQ004840; Thu, 27 Aug 2020 16:33:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pps0720; bh=/KbjPEXuY2Wr3YEI8voPuPyYZxf9S5GcCsxoOWs1pQ8=; b=VxZn2WoDomX94s8l8GH7qupzeNlkFxX72rs+teIyq2FXyz99ZCGdqHVOcN+833xeotKV wFQndCmCLlFoKOHXCQjtAT4cF64qNNu4um5/AyhzqzPk88fYqeWe8Rb2aK2Nkjtf4UYB 20PB4+TA8TF7R0ESw/TDw3FFV1PqCLfONTTb8R18ItJj28CNc5jooaAvMbR4tNgFWKPi 5F/XyFb33A89Mq5bIBYoKCWG6YCsq38r8iK4c9CZilQGn1gxZu6uZuKomBVrF/6AdmMz h5Lv3CYkVlfsnto/CRFmURAc/YtiZFFkFxEgBzwrwYdS0jPiHHhwjiAqCDHUsqg92EdP LA== Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0a-002e3701.pphosted.com with ESMTP id 336fat0j94-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 16:33:39 +0000 Received: from G9W8456.americas.hpqcorp.net (exchangepmrr1.us.hpecorp.net [16.216.161.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by g2t2354.austin.hpe.com (Postfix) with ESMTPS id 71E2791; Thu, 27 Aug 2020 16:33:30 +0000 (UTC) Received: from G1W8108.americas.hpqcorp.net (2002:10c1:483c::10c1:483c) by G9W8456.americas.hpqcorp.net (2002:10d8:a15f::10d8:a15f) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 Aug 2020 16:33:15 +0000 Received: from NAM02-CY1-obe.outbound.protection.outlook.com (15.241.52.11) by G1W8108.americas.hpqcorp.net (16.193.72.60) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Thu, 27 Aug 2020 16:33:16 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X8qaSI0sKA9AmOW/42QEQ0dEUtrgNai0JlCDjXfh7g53hhPDV/+OeC2aPY+zeETT141YbsMhMH+lo3m/A9OqBgL8fdjrDUt98UxMEwG9lPnhhAupspuyVpr5kUJxbvnJICJAYRY8iiZt9o7xR0kj0aiy0BpfHMyMdNNES05kl7I7qENSCTsTspPBfF/pfqrbNaHlvKmmuJDyxjq17nUUv/NdH35E5MPSLzXJYqWk+5uNoxI8fVjLxwEHTz4QU7cBnHjRHJd4zSenz4a4OxUyyHQgDgmgMt6bLz8Ndx9lC2gVEn+F0bYRYpGvGXk0u8YdQlc4kIODYwSVrHA/v1vlYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=e+fkKgFePROZpsrPNIiRtEIYKDbV21m12IW/Qbgxswc=; b=B4mfVUxf9yxAswlstKMxWsgwY95pxHyVJ6AHpHu/M59rHbdRCwID6Db2YtNVkG9n6EZJ3qIosc0KdXbd7zxwxXtnjzXPzgs+0q1znjxhtJEBR8EeucigOQvzhfkRIqPe5t4NEbRQwe4Yc3fR0wh/AG8AyK9QR5IME1jQ1eVRwBqZca0lLr2CKslV/0ATxXhn0qP5WAZD8JfUZVml7ioMf0a3yfjv0oSnrtseBRU61Zg969KyYlL4NzvycRU8qaf8E4B/8bzCqFm2LpxW0IFmk8jW9T1buC1gQXemje9DLbm6R4GAcDkDr9RB3VR9+4c/8Ex+wrpEQKOdLp5pM3PBCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=hpe.com; dmarc=pass action=none header.from=hpe.com; dkim=pass header.d=hpe.com; arc=none Received: from CS1PR8401MB1144.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:7508::16) by CS1PR8401MB0855.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:7511::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3305.25; Thu, 27 Aug 2020 16:33:14 +0000 Received: from CS1PR8401MB1144.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4ed:e814:836b:f074]) by CS1PR8401MB1144.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4ed:e814:836b:f074%10]) with mapi id 15.20.3305.032; Thu, 27 Aug 2020 16:33:14 +0000 From: "Abner Chang" To: Leif Lindholm , "devel@edk2.groups.io" CC: "Schaefer, Daniel" Subject: Re: [edk2-devel] [edk2-plaforms PATCH 2/3] RISC-V/PlatformPkg: Revise Readme.md Thread-Topic: [edk2-devel] [edk2-plaforms PATCH 2/3] RISC-V/PlatformPkg: Revise Readme.md Thread-Index: AQHWfHARDHSFMvP15Euh4QRjcct10KlL8bSAgAAz28A= Date: Thu, 27 Aug 2020 16:33:13 +0000 Message-ID: References: <20200827120305.26095-1-abner.chang@hpe.com> <20200827120305.26095-3-abner.chang@hpe.com> <20200827132345.GU1191@vanye> In-Reply-To: <20200827132345.GU1191@vanye> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nuviainc.com; dkim=none (message not signed) header.d=none;nuviainc.com; dmarc=none action=none header.from=hpe.com; x-originating-ip: [1.34.113.40] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 199baed4-345d-4db4-ced4-08d84aa6e519 x-ms-traffictypediagnostic: CS1PR8401MB0855: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2449; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: EyHVhB+WiMvpF8s41DIRG9KeT2MHk6VwdjVcCSaseUNlRF4idkHmGKvq0DKiOsGixbr8blxJMfgwnJ9McESqS4jkQaz7RQYcBeu2/57X3TmZ0EoyCNPujVvxG257uLlNH5oJVhLos/Y2kACgr26rHTRKVRjJODLNhSUrIxJ7lq/TZZ3v7Cv1UX8iGecOeZYD/2K0Hng+q+kgI96eAfOgVk4E1iAB4vs8YAeCB7EpvLS25PO26yCiS/psfiI4KSk//+7cCGalukts+9hhelqbyoQfWf1oPDVsLAyE4vqeS8+Y9PV3eeQH3WT0Hm6I3XQ3fcXfAYY5Vv7EHeaxPGLwqWeDHZRNz7jOux1119JjvHHd7B/wb1rUhuFzn4sXPqsJlzPq57bXuJ9OtYSoDWJM6w== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CS1PR8401MB1144.NAMPRD84.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(366004)(136003)(376002)(396003)(346002)(39860400002)(186003)(7696005)(33656002)(5660300002)(110136005)(30864003)(64756008)(478600001)(4326008)(66446008)(55016002)(2906002)(8936002)(9686003)(8676002)(316002)(966005)(76116006)(66946007)(66556008)(66476007)(52536014)(71200400001)(19627235002)(86362001)(26005)(6506007)(53546011)(83380400001);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: LAY09dZc4srVDFFrhrlzk12CMfB36sCX38R1gPHCruylqwXMCQ2Yi2eQ2YBV3hDrTZxj3EwRktyOB+fe7M7skCrgMZS/b2KPlDjaTErXnh3Ca8+6LyQ2Q0WsqFtLmrdSWcSnHNXOQQJQqFAXleLPQlCQhn+SsMVLH65FXuv9AzcpQ93DePv02FJBQn6rqSE9DRJIhBfkJrNircR02L0VcjtCMgZklguVRxk3cKH+oPPEwCN3a0uaVGGqCqTCZr051izDRyzsFQ9AAk3KIMAXkDddUdfbBOiEKI6I/y83EPPK+yRi9PcdcP8ljReMqChP+wVcooT/0LXRX/OHQdnPdJ9304kBfCBcAxSDriHjccTUKN5eeMdZaQscSFIGB4LD7Z4i+IzbzbqxhjjJpVBRlqGZpzP43XxhJaSwN08jmjATyhcMCck9hQOJLKWO2UeEU/UqgPPxEsMuUVA9Qr9LAl2uca1Nq4h9ISY6cDxfPJSsTAJM/tczTokUJ7aK77aQcNY8WDWuKFwhEfoAHCVWBTZ88Vns2C4awNHD0JstKzQspF3P2aineJG3vJnUNOdzpvGtEQhCJwKVKUYIWJRnpZns9ka6c73pGRzXdk8bRXjwJA3BdSB1ex7FRLkTroFAq+9nFQkneFioYjfoXy9FwA== X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CS1PR8401MB1144.NAMPRD84.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 199baed4-345d-4db4-ced4-08d84aa6e519 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Aug 2020 16:33:13.9936 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: b/zQ/QaE+0sv13I6zCyul5hunMoH5GCQLNCL7sB8K5YG4Qn26jpr5KnRQGQfZMMCX8MFNWTE7HnWEoofv9jyaA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CS1PR8401MB0855 X-OriginatorOrg: hpe.com X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-08-27_08:2020-08-27,2020-08-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270123 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I just resent the whole set of patches without missing patch 3/3. Some comm= ents you mentioned were addressed but the lines are still too long. Will fi= x it with your comment on v2 patch. > -----Original Message----- > From: Leif Lindholm [mailto:leif@nuviainc.com] > Sent: Thursday, August 27, 2020 9:24 PM > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) > > Cc: Schaefer, Daniel > Subject: Re: [edk2-devel] [edk2-plaforms PATCH 2/3] RISC-V/PlatformPkg: > Revise Readme.md >=20 > On Thu, Aug 27, 2020 at 20:03:04 +0800, Abner Chang wrote: > > Update RISC-V PlatformPkg Readme.md to align with the latest > implementation. > > > > Signed-off-by: Abner Chang > > Co-authored-by: Daniel Schaefer > > > > Cc: Daniel Schaefer > > --- > > Platform/RISC-V/PlatformPkg/Readme.md | 72 > > ++++++++++++++------------- > > 1 file changed, 37 insertions(+), 35 deletions(-) > > > > diff --git a/Platform/RISC-V/PlatformPkg/Readme.md > > b/Platform/RISC-V/PlatformPkg/Readme.md > > index 2632ebeb28..bd3b823fb4 100644 > > --- a/Platform/RISC-V/PlatformPkg/Readme.md > > +++ b/Platform/RISC-V/PlatformPkg/Readme.md > > @@ -1,49 +1,48 @@ > > -# Introduction > > +# Introduction of EDK2 RISC-V Port >=20 > This is edk2-platforms: any introduction of edk2 portions should be in e= dk2. >=20 > > > > -## EDK2 RISC-V Platform Packages > > -RISC-V platform package provides the generic and common modules for > > RISC-V -platforms. RISC-V platform package could include > > RiscPlatformPkg.dec to -use the common drivers, libraries, > > definitions, PCDs and etc. for the -platform development. > > +## EDK2 RISC-V Project > > +The edk2 build architecture which is supported and verified on edk2 c= ode > base for RISC-V platforms is `RISCV64`. > > +The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu= - > toolchain) for building edk2 RISC-V binary. > > +The corresponding edk2 Toolchain tag for building RISC-V platform is > "GCC5" declared in `tools_def.txt`. >=20 > Please wrap long lines, like in the text being replaced. > The point of markdown/rst etc is that it can be rendered into auto-reflo= wed > HTML text *or* read directly in a terminal. Wrapping it properly for the= latter > won't impact the former. >=20 > > > > -There are two packages to support RISC-V: > > +There are two packages to support RISC-V edk2 platforms: > > - `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec` > > - `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec` >=20 > (I would say edk2-platforms can be left out when referring to the curren= t > repository.) >=20 > > > > -`RiscVPlatformPkg` provides SEC phase and NULL libs. > > -`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers. > > +`RiscVPlatformPkg` currently provides the generic SEC driver for all = RISC-V > platforms, and some platform level libraries. > > +`RiscVProcessorPkg` currently provides RISC-V processor related > > +libraries, PEI modules, DXE drivers and industrial standard header fi= les. > > > > -### Download the sources ### > > +## EDK2 RISC-V Platform Package >=20 > edk2-platforms? >=20 > > +RISC-V platform package provides the common modules for RISC-V > > +platforms. RISC-V platform vendors could include RiscPlatformPkg.dec > > +to use the common drivers, libraries, definitions, PCDs and etc. for = the > RISC-V platform development. > > + > > +### Download the Source Code ### > > ``` > > git clone https://github.com/tianocore/edk2.git > > +git clone https://github.com/tianocore/edk2-platforms.git > > > > -git clone https://github.com/changab/edk2-platforms.git > > -# Check out branch: riscv-smode-lib > > ``` > > > > -To build it, you have to follow the regular steps for EDK2 and > > additionally set -an environmen variable to point to your RISC-V > > toolchain installation, -including the binary prefixes: > > - > > +You have to follow the build steps for EDK2 > > +(https://github.com/tianocore/tianocore.github.io/wiki/Getting-Starte > > +d-with-EDK-II) and additionally set an environment variable to point > > +to your RISC-V toolchain binaries for building RISC-V platforms, > > ``` > > +# e.g. If the toolchain binaries are under > > +/riscv-gnu-toolchain-binaries/bin > > export > > GCC5_RISCV64_PREFIX=3D/riscv-gnu-toolchain-binaries/bin/riscv64- > unknown- > > elf- > > ``` >=20 > Look, I realise you guys aren't building natively yet, but I > *strongly* recomment that you start seeing that as something normal > sooner rather than later. There's nothing wrong with describing cross > compilation as well, and in these early days even point to specific "kno= wn > good" toolchains, but treating it as the only valid way of building feed= s > complacency. >=20 > And even while I *did* push for native-is-normal for arm64 from the earl= iest > days, we still get occasional comments about people using some archaolog= ic > specific linaro build and think the sky will fall on their heads because= it's an > ancient build for i686 and no longer runs on current Linux distros. >=20 > / > Leif >=20 > > > > -Then you can build the image for the SiFive HifiveUnleashed platform: > > +Then you can build the edk2 firmware image for RISC-V platforms. > > > > ``` > > +# e.g. For building SiFive Hifive Unleashed platform: > > build -a RISCV64 -t GCC5 -p > > > Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc > > ``` > > > > -### EDK2 project > > -All changes in edk2 are upstream, however, most of the RISC-V code is > > in -edk2-platforms. Therefore you have to check out the branch > > `riscv-smode-lib` on -`github.com/changab/edk2-platforms`. > > - > > -The build architecture which is supported and verified so far is `RIS= CV64`. > > -The latest master of the RISC-V toolchain > > https://github.com/riscv/riscv-gnu-toolchain > > -should work but the latest verified commit is > `b468107e701433e1caca3dbc8aef8d40`. > > -Toolchain tag is "GCC5" declared in `tools_def.txt` > > +## RISC-V OpenSBI Library > > +RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the > > +implementation of [RISC-V SBI (Supervisor Binary Interface) > specification](https://github.com/riscv/riscv-sbi-doc). For EDK2 UEFI > firmware solution, RISC-V OpenSBI is integrated as a library > [(submoudule)](Silicon/RISC- > V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi) in EDK2 RISC-V Processor > Package. The RISC-V OpenSBI library is built in SEC driver without any > modifications and provides the interfaces for supervisor mode execution > environment to execute privileged operations. > > > > ## RISC-V Platform PCD settings > > ### EDK2 Firmware Volume Settings > > @@ -54,9 +53,9 @@ EDK2 Firmware volume related PCDs which declared in > platform FDF file. > > |PcdRiscVSecFvBase| The base address of SEC Firmware Volume| > > |PcdRiscVSecFvSize| The size of SEC Firmware Volume| > > |PcdRiscVPeiFvBase| The base address of PEI Firmware Volume| > > -|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| > > +|PcdRiscVPeiFvSize| The size of PEI Firmware Volume| > > |PcdRiscVDxeFvBase| The base address of DXE Firmware Volume| > > -|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| > > +|PcdRiscVDxeFvSize| The size of DXE Firmware Volume| > > > > ### EDK2 EFI Variable Region Settings The PCD settings regard to EFI > > Variable @@ -84,21 +83,24 @@ Below PCDs could be set in platform FDF > > file. > > |--------------|---------| > > |PcdHartCount| Number of RISC-V HARTs, the value is > > processor-implementation specific| |PcdBootHartId| The ID of RISC-V > > HART to execute main fimrware code and boot system to OS| > > +|PcdBootableHartNumber|The bootable HART number, which is > incorporate > > +|PcdBootableHartNumber|with RISC-V OpenSBI platform hart_index2id > > +|PcdBootableHartNumber|value| > > > > ### RISC-V OpenSBI Settings > > > > | **PCD name** |**Usage**| > > |--------------|---------| > > -|PcdScratchRamBase| The base address of OpenSBI scratch buffer for > > -|PcdScratchRamBase| all RISC-V HARTs| > > -|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all > > -|PcdScratchRamSize| RISC-V HARTs| > > -|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART > > -|PcdOpenSbiStackSize| for booting system use OpenSBI| > > +|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer > > +|PcdScratchRamBase| for all RISC-V HARTs| > > +|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer > > +|PcdScratchRamSize| for all RISC-V HARTs| > > +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART > > +|PcdOpenSbiStackSize| for booting system use RISC-V OpenSBI| > > |PcdTemporaryRamBase| The base address of temporary memory for PEI > > phase| |PcdTemporaryRamSize| The temporary memory size for PEI > phase| > > +|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 > > +|PcdPeiCorePrivilegeMode|PEI phase| > > > > ## Supported Operating Systems > > -Only support to boot to EFI Shell so far. > > - > > -Porting GRUB2 and Linux EFISTUB is in progress. > > +Currently support boot to EFI Shell and Linux kernel. > > +Refer to below link for more information, > > +https://github.com/riscv/riscv-uefi-edk2-docs > > > > ## Known Issues and Limitations > > -Only RISC-V RV64 is verified. > > +Only RISC-V RV64 is verified on edk2. > > + > > -- > > 2.25.0 > > > > > >=20 > >