Hi Dandan,
Below is the information for you to update the table in your slide.

                        IA32      X64         EBC      ARM     ARM64     AARCH64     RISCV64
CSR R/W        NA       NA           NA        NA          NA               NA               YES

Thanks
Abner

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of devel@edk2.groups.io Calendar
Sent: Friday, March 5, 2021 9:30 AM
To: devel@edk2.groups.io
Subject: [edk2-devel] TianoCore Design Meeting - APAC/NAMO - Fri, 03/05/2021 #cal-notice


TianoCore Design Meeting - APAC/NAMO

When:
Friday, 5 March 2021
9:30am to 10:30am
(GMT+08:00) Asia/Shanghai

Where:
https://intel.webex.com/intel/j.php?MTID=me894224717bbf0af843f2ff7502c98cb

Organizer:
ray.ni@intel.com<mailto:ray.ni@intel.com?subject=Re:%20Event:%20TianoCore%20Design%20Meeting%20-%20APAC%2FNAMO>

Description:

TOPIC

  *   FilterLib: Filter/Trace Port IO/MMIO/MSR access (Dandan Bi/Intel)

Slides: https://edk2.groups.io/g/devel/files/Designs/2021/0305/FilterLib.pdf<https://edk2.groups.io/g/devel/files/Designs/2021/0305/FilterLib.pdf>

For more info, see here: https://www.tianocore.org/design-meeting/<https://www.tianocore.org/design-meeting/>

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