* [PATCH 4/4] SecurityPkg: convert Tpm2DeviceLibDTpm to use TpmIoLib
@ 2018-11-13 22:12 Cohen, Eugene
0 siblings, 0 replies; only message in thread
From: Cohen, Eugene @ 2018-11-13 22:12 UTC (permalink / raw)
To: edk2-devel@lists.01.org, Yao, Jiewen, Zhang, Chao B
Cc: Bin, Sung-Uk (빈성욱)
SecurityPkg: convert Tpm2DeviceLibDTpm to use TpmIoLib
Contributed-under: TianoCore Contribution Agreement 1.1
Cc: Chao Zhang <chao.b.zhang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Eugene Cohen <eugene@hp.com>
---
SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2DeviceLibDTpm.inf | 2 +-
SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf | 2 +-
SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c | 60 ++++++++++----------
SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c | 28 ++++-----
4 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2DeviceLibDTpm.inf b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2DeviceLibDTpm.inf
index c6d23c9..2da8949 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2DeviceLibDTpm.inf
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2DeviceLibDTpm.inf
@@ -47,7 +47,7 @@
[LibraryClasses]
BaseLib
BaseMemoryLib
- IoLib
+ TpmIoLib
TimerLib
DebugLib
PcdLib
diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
index 14e5e2e..4de76a3 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
@@ -43,7 +43,7 @@
[LibraryClasses]
BaseLib
BaseMemoryLib
- IoLib
+ TpmIoLib
TimerLib
DebugLib
PcdLib
diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
index ad2f188..6525416 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
@@ -16,7 +16,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
+#include <Library/TpmIoLib.h>
#include <Library/TimerLib.h>
#include <Library/DebugLib.h>
#include <Library/Tpm2DeviceLib.h>
@@ -51,7 +51,7 @@ Tpm2IsPtpPresence (
{
UINT8 RegRead;
- RegRead = MmioRead8 ((UINTN)Reg);
+ RegRead = TpmRead8 ((UINTN)Reg);
if (RegRead == 0xFF) {
//
// No TPM chip
@@ -84,7 +84,7 @@ PtpCrbWaitRegisterBits (
UINT32 WaitTime;
for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
- RegRead = MmioRead32 ((UINTN)Register);
+ RegRead = TpmRead32 ((UINTN)Register);
if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
return EFI_SUCCESS;
}
@@ -114,7 +114,7 @@ PtpCrbRequestUseTpm (
return EFI_NOT_FOUND;
}
- MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
+ TpmWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
Status = PtpCrbWaitRegisterBits (
&CrbReg->LocalityStatus,
PTP_CRB_LOCALITY_STATUS_GRANTED,
@@ -180,7 +180,7 @@ PtpCrbTpmCommand (
// STEP 0:
// if CapCRbIdelByPass == 0, enforce Idle state before sending command
//
- if (PcdGet8(PcdCRBIdleByPass) == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){
+ if (PcdGet8(PcdCRBIdleByPass) == 0 && (TpmRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){
Status = PtpCrbWaitRegisterBits (
&CrbReg->CrbControlStatus,
PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
@@ -202,7 +202,7 @@ PtpCrbTpmCommand (
// of 1 by software to Request.cmdReady, as indicated by the Status field
// being cleared to 0.
//
- MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
+ TpmWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
Status = PtpCrbWaitRegisterBits (
&CrbReg->CrbControlRequest,
0,
@@ -231,21 +231,21 @@ PtpCrbTpmCommand (
// of 1 to Start.
//
for (Index = 0; Index < SizeIn; Index++) {
- MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
+ TpmWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
}
- MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
- MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
- MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
+ TpmWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
+ TpmWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
+ TpmWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
- MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
- MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
+ TpmWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
+ TpmWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
//
// STEP 3:
// Command Execution occurs after receipt of a 1 to Start and the TPM
// clearing Start to 0.
//
- MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
+ TpmWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
Status = PtpCrbWaitRegisterBits (
&CrbReg->CrbControlStart,
0,
@@ -257,14 +257,14 @@ PtpCrbTpmCommand (
// Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
// Expect TPM_RC_CANCELLED or successfully completed response.
//
- MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
+ TpmWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
Status = PtpCrbWaitRegisterBits (
&CrbReg->CrbControlStart,
0,
PTP_CRB_CONTROL_START,
PTP_TIMEOUT_B
);
- MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
+ TpmWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
if (EFI_ERROR(Status)) {
//
@@ -286,7 +286,7 @@ PtpCrbTpmCommand (
// Get response data header
//
for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
- BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
+ BufferOut[Index] = TpmRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
}
DEBUG_CODE (
DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
@@ -320,7 +320,7 @@ PtpCrbTpmCommand (
// Continue reading the remaining data
//
for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {
- BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
+ BufferOut[Index] = TpmRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
}
DEBUG_CODE (
@@ -337,7 +337,7 @@ GoReady_Exit:
// If not supported. flow down to GoIdle
//
if (PcdGet8(PcdCRBIdleByPass) == 1) {
- MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
+ TpmWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
return Status;
}
@@ -350,7 +350,7 @@ GoIdle_Exit:
//
// Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.
//
- MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
+ TpmWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
//
// Only enforce Idle state transition if execution fails when CRBIndleBypass==1
@@ -429,8 +429,8 @@ Tpm2GetPtpInterface (
//
// Check interface id
//
- InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
- InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
+ InterfaceId.Uint32 = TpmRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
+ InterfaceCapability.Uint32 = TpmRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
@@ -463,7 +463,7 @@ Tpm2GetIdleByPass (
//
// Check interface id
//
- InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
+ InterfaceId.Uint32 = TpmRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);
}
@@ -490,9 +490,9 @@ DumpPtpInfo (
return ;
}
- InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
- InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
- StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
+ InterfaceId.Uint32 = TpmRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
+ InterfaceCapability.Uint32 = TpmRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
+ StatusEx = TpmRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
//
// Dump InterfaceId Register for PTP
@@ -529,15 +529,15 @@ DumpPtpInfo (
DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));
switch (PtpInterface) {
case Tpm2PtpInterfaceCrb:
- Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
- Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
+ Vid = TpmRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
+ Did = TpmRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
Rid = (UINT8)InterfaceId.Bits.Rid;
break;
case Tpm2PtpInterfaceFifo:
case Tpm2PtpInterfaceTis:
- Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
- Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
- Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
+ Vid = TpmRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
+ Did = TpmRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
+ Rid = TpmRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
break;
default:
break;
diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
index 6f390bf..75a3488 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
@@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
+#include <Library/TpmIoLib.h>
#include <Library/TimerLib.h>
#include <Library/DebugLib.h>
#include <Library/Tpm2DeviceLib.h>
@@ -47,7 +47,7 @@ TisPcPresenceCheck (
{
UINT8 RegRead;
- RegRead = MmioRead8 ((UINTN)&TisReg->Access);
+ RegRead = TpmRead8 ((UINTN)&TisReg->Access);
return (BOOLEAN)(RegRead != (UINT8)-1);
}
@@ -74,7 +74,7 @@ TisPcWaitRegisterBits (
UINT32 WaitTime;
for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
- RegRead = MmioRead8 ((UINTN)Register);
+ RegRead = TpmRead8 ((UINTN)Register);
if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
return EFI_SUCCESS;
MicroSecondDelay (30);
@@ -111,10 +111,10 @@ TisPcReadBurstCount (
do {
//
// TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
- // so it needs to use MmioRead8 to read two times
+ // so it needs to use TpmRead8 to read two times
//
- DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
- DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
+ DataByte0 = TpmRead8 ((UINTN)&TisReg->BurstCount);
+ DataByte1 = TpmRead8 ((UINTN)&TisReg->BurstCount + 1);
*BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
if (*BurstCount != 0) {
return EFI_SUCCESS;
@@ -147,7 +147,7 @@ TisPcPrepareCommand (
return EFI_INVALID_PARAMETER;
}
- MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
+ TpmWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
Status = TisPcWaitRegisterBits (
&TisReg->Status,
TIS_PC_STS_READY,
@@ -183,7 +183,7 @@ TisPcRequestUseTpm (
return EFI_NOT_FOUND;
}
- MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
+ TpmWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
Status = TisPcWaitRegisterBits (
&TisReg->Access,
(UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
@@ -262,7 +262,7 @@ Tpm2TisTpmCommand (
goto Exit;
}
for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
- MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
+ TpmWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
Index++;
}
}
@@ -283,7 +283,7 @@ Tpm2TisTpmCommand (
//
// Executed the TPM command and waiting for the response data ready
//
- MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
+ TpmWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
//
// NOTE: That may take many seconds to minutes for certain commands, such as key generation.
@@ -301,7 +301,7 @@ Tpm2TisTpmCommand (
//
DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out. Trying to cancel the command!!\n"));
- MmioWrite32((UINTN)&TisReg->Status, TIS_PC_STS_CANCEL);
+ TpmWrite32((UINTN)&TisReg->Status, TIS_PC_STS_CANCEL);
Status = TisPcWaitRegisterBits (
&TisReg->Status,
(UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
@@ -333,7 +333,7 @@ Tpm2TisTpmCommand (
goto Exit;
}
for (; BurstCount > 0; BurstCount--) {
- *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
+ *(BufferOut + Index) = TpmRead8 ((UINTN)&TisReg->DataFifo);
Index++;
if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;
}
@@ -368,7 +368,7 @@ Tpm2TisTpmCommand (
//
while ( Index < TpmOutSize ) {
for (; BurstCount > 0; BurstCount--) {
- *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
+ *(BufferOut + Index) = TpmRead8 ((UINTN)&TisReg->DataFifo);
Index++;
if (Index == TpmOutSize) {
Status = EFI_SUCCESS;
@@ -389,7 +389,7 @@ Exit:
}
DEBUG ((EFI_D_VERBOSE, "\n"));
);
- MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
+ TpmWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
return Status;
}
--
2.7.4
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