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Thu, 28 Feb 2019 17:40:31 -0500 Received: from CS1PR8401MB1189.NAMPRD84.PROD.OUTLOOK.COM (10.169.97.20) by CS1PR8401MB0582.NAMPRD84.PROD.OUTLOOK.COM (10.169.14.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1643.15; Thu, 28 Feb 2019 22:40:29 +0000 Received: from CS1PR8401MB1189.NAMPRD84.PROD.OUTLOOK.COM ([fe80::ec9d:c9c3:8a92:4378]) by CS1PR8401MB1189.NAMPRD84.PROD.OUTLOOK.COM ([fe80::ec9d:c9c3:8a92:4378%4]) with mapi id 15.20.1643.019; Thu, 28 Feb 2019 22:40:29 +0000 From: "Cohen, Eugene" To: Ashish Singhal , "Wu, Hao A" , "edk2-devel@lists.01.org" , Ard Biesheuvel Thread-Topic: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems Thread-Index: AdTOimUh6bq74L7bQyCZsF0hnADHfgAhuWlQABE+2EAAEKP68AABVU+wAANAbhAAAOJ+kAAA/hKAAAC2wPA= Date: Thu, 28 Feb 2019 22:40:29 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [15.65.252.14] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ae4acbc5-cbe4-460c-fd93-08d69dcdbd7c x-microsoft-antispam: BCL:0; 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charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Ashish, I think that code will still fail for our use case. We are version 3 with = 64-bit support so Private->Capability[Slot].SysBus64V3 =3D=3D 0 will evalua= te to FALSE. Since we are V3 Private->ControllerVersion[Slot] >=3D SD_MMC_= HC_CTRL_VER_400 will also evaluate to FALSE. Therefore Support64BitDma wil= l still be TRUE resulting in DUAL_ADDRESS_CYCLE being set which disables bo= unce buffering. Since no code is in place to do V3 64b DMA we will still hit the same probl= em, specifically namely that buffers that are not DMAable will be allocated= and we will still fail the check here. Until such time that V3 64b DMA support is in place I believe only the V4 b= it should be evaluated. Eugene From: Ashish Singhal Sent: Thursday, February 28, 2019 3:21 PM To: Cohen, Eugene ; Wu, Hao A ; edk2-dev= el@lists.01.org; Ard Biesheuvel Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Eugene, Thanks for the explanation. The problem is valid and is more clear to me no= w. How about we do this: Instead of: if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 && Private->Capability[Slot].SysBus64V4 =3D=3D 0) { Support64BitDma =3D FALSE; } What do you think about: if ((Private->ControllerVersion[Slot] =3D=3D SD_MMC_HC_CTRL_VER_300 && Private->Capability[Slot].SysBus64V3 =3D=3D 0) || (Private->ControllerVersion[Slot] >=3D SD_MMC_HC_CTRL_VER_400 && Private->Capability[Slot].SysBus64V4 =3D=3D 0)) { Support64BitDma =3D FALSE; } With this, we would be checking 64b capability based on the version we are = using and not for something we may not be using despite of being advertised= in the controller. Thanks Ashish From: Cohen, Eugene > Sent: Thursday, February 28, 2019 2:59 PM To: Ashish Singhal = >; Wu, Hao A >; edk2-devel@li= sts.01.org; Ard Biesheuvel > Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Ashish, =D8 Right now, we disable 64b DMA Support in PCI if the controller cannot = support 64b DMA in V3 as well as V4. If either of these support 64b DMA, w= e do not disable it. In the code, we set Support64BitDma to TRUE by default= and change it to FALSE only if any of the controller does not support it i= n V3 as well as V4. If all controllers support it in V3 or V4 we keep 64b D= MA support enabled. That is precisely the problem. An SDHC v3 controller might support 64b DMA= in V3 but not in V4 mode. The current code will leave 64b DMA support ena= bled resulting in the issuing of the PCI DUAL_ADDRESS_CYCLE attribute ( see= https://github.com/tianocore/edk2/blob/ece4c1de3e7b2340d351c2054c79ea689a9= 54ed6/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c#L738 ) which then causes buffer= s to be allocated that cannot be DMAed. For reference look at this snippet of the NonDiscoverablePciDeviceIo driver= : https://github.com/tianocore/edk2/blob/ece4c1de3e7b2340d351c2054c79ea689a= 954ed6/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceIo.c#L622 and you can see that bounce buffering will onl= y occur if DUAL_ADDRESS_CYCLE is clear. So since we do not have V3 64b DMA (96-bit descriptor) support in place we = must not allow the DUAL_ADDRESS_CYCLE attribute to be set or we will fail w= ith this check: https://github.com/tianocore/edk2/blob/ece4c1de3e7b2340d351= c2054c79ea689a954ed6/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c#L1426= I've added Ard who updated the driver with DUAL_ADDRESS_CYCLE support. Eugene From: Ashish Singhal > Sent: Thursday, February 28, 2019 2:28 PM To: Cohen, Eugene >; Wu, Hao A >; edk2-devel@lists.01.org Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Eugene, We do not have support for V4 64b DMA right now but it can be added later i= f needed. I am trying to understand the reason behind changing the check fr= om AND to OR. Right now, we disable 64b DMA Support in PCI if the controlle= r cannot support 64b DMA in V3 as well as V4. If either of these support 64= b DMA, we do not disable it. In the code, we set Support64BitDma to TRUE by= default and change it to FALSE only if any of the controller does not supp= ort it in V3 as well as V4. If all controllers support it in V3 or V4 we ke= ep 64b DMA support enabled. // // Enable 64-bit DMA support in the PCI layer if this controller // supports it. // if (Support64BitDma) { Status =3D PciIo->Attributes ( PciIo, EfiPciIoAttributeOperationEnable, EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, NULL ); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_WARN, "SdMmcPciHcDriverBindingStart: failed to enable 6= 4-bit DMA (%r)\n", Status)); } } Thanks Ashish From: Cohen, Eugene > Sent: Thursday, February 28, 2019 12:56 PM To: Ashish Singhal = >; Wu, Hao A >; edk2-devel@li= sts.01.org Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Ashish, =D8 With my change, if any of the controller did not support 64b DMA in V3= as well as V4 capability, we are not enabling it in PCI layer. The logic is: if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 && Private->Capability[Slot].SysBus64V4 =3D=3D 0) { Support64BitDma =3D FALSE; } which means that for a SDHC v3 controller you have SysBus64V3=3D1 and SysBu= s64V4=3D0 the FALSE assignment is never done - this is not correct. Perhap= s you intended an OR instead of an AND? Either way changing this to an || = or using my patch is the same logical result because a V3 controller will u= se 32-bit DMA and V4 controller will use 64-bit DMA (a V4 controller should= have the V3 bit set). I really saw no reason to be checking the V3 bit si= nce the driver was unprepared to do V3 64-bit DMA operations anyways. Eugene From: Ashish Singhal > Sent: Thursday, February 28, 2019 12:15 PM To: Cohen, Eugene >; Wu, Hao A >; edk2-devel@lists.01.org Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Hello Eugene, My patch enabled support for SDHC 4.0 and above in general including suppor= t for 64b ADMA descriptor. The check for V3 capability for 64b DMA was alre= ady there and similar check was implemented for V4 capability for 64b DMA. = Earlier, if any of the V3 controller did not support 64b DMA, we were not e= nabling it in PCI layer. With my change, if any of the controller did not s= upport 64b DMA in V3 as well as V4 capability, we are not enabling it in PC= I layer. This check in my opinion is better because we only disable 64b DMA PCI supp= ort when both V3 and V4 have it disabled. Thanks Ashish -----Original Message----- From: Cohen, Eugene > Sent: Thursday, February 28, 2019 4:24 AM To: Wu, Hao A >; edk2-devel@l= ists.01.org Cc: Ashish Singhal = > Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Hao, > I remember the commit b5547b9ce97e80c3127682a2a5d4b9bd14af353e from > Ashish only handles the controllers with version greater or equal to 4.00= . Right - that commit added support for SDHC 4.0 and above. The original driv= er supported SDHC 3.0 albeit only with SDMA and 32-bit ADMA support. With that commit two descriptor types are supported the 32-bit ADMA descrip= tor (SD_MMC_HC_ADMA_32_DESC_LINE which is 64-bits in size) and the V4 64-bi= t ADMA descriptor (SD_MMC_HC_ADMA_64_DESC_LINE which is 128-bits in size). However the commit mistakenly added a check for the V3 capability for 64-bi= t DMA and used it to set the PCI DUAL_ADDRESS_CYCLE attributre which then d= oes not the 32-bit compatible bounce buffer mechanism. Later, when we attem= pt an ADMA data transfer we hit an ASSERT because the PCI DMA subsystem is = not using bounce buffers to provide 32-bit DMA compatible memory. So the pa= tch I submitted simply removes the unnecessary check of the V3 64-bit DMA c= apability check so the PCI DUAL_ADDRESS_CYCLE attribute is not set allowing= 32-bit DMA to succeed on these platforms. > And the ADMA2 (96-bit Descriptor) mode for V3 controllers is selected > by setting the 'DMA Select' filed in the Host Control 1 Register to > 11b. But the currently behavior of the driver is setting the field to > 10b, which I think will not switch to the ADMA2 (96-bit Descriptor) mode = for V3. Correct, right now for a V3 controller only 32-bit DMA is supported. An enh= ancement for V3 64-bit ADMA would improve performance on controllers that s= upport that mode by eliminating the bounce buffer and associated memory cop= ies. I think we should file a BZ for SD HCI V3 64-bit ADMA support - if you= agree I would be happy to do that. I should point out that we have done extensive testing of this change on ou= r host controller. Thanks, Eugene --- From: Wu, Hao A > Sent: Wednesday, February 27, 2019 8:25 PM To: Cohen, Eugene >; edk2-devel@lists.0= 1.org Cc: Ashish Singhal = > Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit = systems Loop Ashish in. Some comments below. > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Cohen, Eugene > Sent: Wednesday, February 27, 2019 6:59 PM > To: mailto:edk2-devel@lists.01.org; Wu, Hao A > Subject: [edk2] [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC > v3 64-bit systems > > The SdMmcPciHcDriverBindingStart function was checking two different > capability bits in determining whether 64-bit DMA modes were > supported, one mode is defined in the SDHC version > 3 specification (using 96-bit descriptors) and another is defined in > the SDHC version 4 specification (using 128-bit descriptors). Since > the currently implementation of 64-bit > ADMA2 only supports the SDHC version 4 implementation it is incorrect > to check the V3 64-bit capability bit since this will activate V4 > ADMA2 on V3 controllers. I remember the commit b5547b9ce97e80c3127682a2a5d4b9bd14af353e from Ashish = only handles the controllers with version greater or equal to 4.00. And the ADMA2 (96-bit Descriptor) mode for V3 controllers is selected by se= tting the 'DMA Select' filed in the Host Control 1 Register to 11b. But the= currently behavior of the driver is setting the field to 10b, which I thin= k will not switch to the ADMA2 (96-bit Descriptor) mode for V3. Maybe there is something I miss here. Could you help to provide some more d= etail on the issue you met? Thanks. Best Regards, Hao Wu > > Cc: Hao Wu > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eugene Cohen > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > index b474f8d..5bc91c5 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > @@ -666,8 +666,7 @@ SdMmcPciHcDriverBindingStart ( // If any of the > slots does not support 64b system bus // do not enable 64b DMA in the > PCI layer. > // > - if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 && > - Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > + if (Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > Support64BitDma =3D FALSE; > } > > -- > 2.7.4 > _______________________________________________ > edk2-devel mailing list > mailto:edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel ---------------------------------------------------------------------------= -------- This email message is for the sole use of the intended recipient(s) and may= contain confidential information. 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