From: "Cohen, Eugene" <eugene@hp.com>
To: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
Hao Wu <hao.a.wu@intel.com>
Subject: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems
Date: Wed, 27 Feb 2019 10:58:57 +0000 [thread overview]
Message-ID: <CS1PR8401MB1189F7C1BC87C67DCC3D2824B4740@CS1PR8401MB1189.NAMPRD84.PROD.OUTLOOK.COM> (raw)
The SdMmcPciHcDriverBindingStart function was checking two
different capability bits in determining whether 64-bit DMA
modes were supported, one mode is defined in the SDHC version
3 specification (using 96-bit descriptors) and another is
defined in the SDHC version 4 specification (using 128-bit
descriptors). Since the currently implementation of 64-bit
ADMA2 only supports the SDHC version 4 implementation it is
incorrect to check the V3 64-bit capability bit since this
will activate V4 ADMA2 on V3 controllers.
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eugene Cohen <eugene@hp.com>
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index b474f8d..5bc91c5 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -666,8 +666,7 @@ SdMmcPciHcDriverBindingStart (
// If any of the slots does not support 64b system bus
// do not enable 64b DMA in the PCI layer.
//
- if (Private->Capability[Slot].SysBus64V3 == 0 &&
- Private->Capability[Slot].SysBus64V4 == 0) {
+ if (Private->Capability[Slot].SysBus64V4 == 0) {
Support64BitDma = FALSE;
}
--
2.7.4
next reply other threads:[~2019-02-27 10:59 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-27 10:58 Cohen, Eugene [this message]
2019-02-28 3:24 ` [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems Wu, Hao A
2019-02-28 11:23 ` Cohen, Eugene
2019-02-28 19:15 ` Ashish Singhal
2019-02-28 19:56 ` Cohen, Eugene
2019-02-28 21:27 ` Ashish Singhal
2019-02-28 21:58 ` Cohen, Eugene
2019-02-28 22:20 ` Ashish Singhal
2019-02-28 22:40 ` Cohen, Eugene
2019-02-28 23:58 ` Ashish Singhal
2019-03-01 0:10 ` Cohen, Eugene
2019-03-01 0:19 ` Ashish Singhal
2019-03-01 10:32 ` Ard Biesheuvel
2019-03-01 10:34 ` Ard Biesheuvel
2019-03-01 10:54 ` Cohen, Eugene
2019-03-01 11:38 ` Ard Biesheuvel
2019-03-01 12:31 ` Ashish Singhal
2019-03-01 18:31 ` Ashish Singhal
2019-03-01 15:25 ` Ashish Singhal
2019-03-04 2:39 ` Wu, Hao A
2019-03-04 4:00 ` Ashish Singhal
2019-03-04 4:26 ` Wu, Hao A
2019-03-05 11:58 ` Cohen, Eugene
2019-03-01 11:02 ` Cohen, Eugene
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