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Tue, 15 Oct 2019 06:39:05 +0000 From: "Abner Chang" To: "devel@edk2.groups.io" , "leif.lindholm@linaro.org" Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Thread-Topic: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Thread-Index: AQHVcaqVD4Qavye24kuQMytHDPvblKc+jnsAgBzS0lA= Date: Tue, 15 Oct 2019 06:39:04 +0000 Message-ID: References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <20190926222240.GA25504@bivouac.eciton.net> In-Reply-To: <20190926222240.GA25504@bivouac.eciton.net> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [16.242.247.131] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e033740a-c74d-47e8-6e9c-08d7513a5fa4 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: CS1PR8401MB0789: x-ms-exchange-purlcount: 1 x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:49; x-forefront-prvs: 01917B1794 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(366004)(346002)(376002)(39860400002)(136003)(396003)(13464003)(189003)(199004)(7736002)(2501003)(76176011)(2906002)(110136005)(52536014)(316002)(6116002)(3846002)(8676002)(305945005)(81156014)(25786009)(8936002)(81166006)(229853002)(186003)(102836004)(53546011)(6506007)(26005)(7696005)(66066001)(486006)(11346002)(446003)(476003)(99286004)(6246003)(66946007)(30864003)(5660300002)(14454004)(55016002)(6306002)(6436002)(478600001)(9686003)(74316002)(966005)(86362001)(76116006)(14444005)(71200400001)(33656002)(71190400001)(66446008)(19627235002)(256004)(66476007)(66556008)(64756008);DIR:OUT;SFP:1102;SCL:1;SRVR:CS1PR8401MB0789;H:CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Leif, thanks for spending lot of time to review the set of RISC-V edk2 p= atches. I addressed most of comments and gave back few feedbacks to you in = email. I think the major remaining issue is the toolchain problem. I will investi= gate toolchain issue while you review v3 patches. I think most of patches s= hould look fine now. How do you think?=20 Abner > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Leif Lindholm > Sent: Friday, September 27, 2019 6:23 AM > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V > EDK2 Port on >=20 > On Mon, Sep 23, 2019 at 08:31:25AM +0800, Abner Chang wrote: > > This branch "RISC-V-V2" is used to contribute RISC-V architecture on E= DK2. > > Compare to the old branch "RISC-V", this branch "RISC-V-V2" is created > > based on the most recent edk2/master @37eef910. This is easier for > > reviewers to have clear ideas of edk2 code changes for RISC-V EDK2 > implementation. > > Because of the code changes made on old branch "RISC-V" is stale and > > not compliant with the latest RISC-V spec, this new branch has the > > fresh changes for RISC-V EDK2 implementation. > > > > The main changes of these series of patches are, > > - Add RiscVPkg which conform with RISC-V Privilege Spec v1.10. > > - Incorporate and leverage RISC-V OpenSBI to provide EDK2 port OpenSBI > library. > > - Provide RISC-V platform implementation specific drivers to EDK2 RISC= -V > platform > > package. > > - Provide generic RISC-V SMBIOS DXE drive to create SMBIOS type 4, 7 a= nd > 44 records, > > in which the SMBIOS type 44 record is introduced in SMBIOS spec 3.3.= 0. > > > > Abner Chang (29): > > RiscVPkg: RISC-V processor package. > > RiscVPkg/Include: Add header files of RISC-V CPU package > > RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support >=20 > PatchCheck.py warns about long line in commit message. >=20 > > MdePkg: RISC-V RV64 binding in MdePkg > > MdePkg/Include: RISC-V definitions. > > MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch. > > MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor. > > MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance > > implementation. >=20 > PatchCheck.py warns about long line in commit message. >=20 > > MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions. > > MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. > > MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. > > MdePkg/BaseSynchronizationLib: RISC-V cache related code. > > MdeModulePkg/Logo > > NetworkPkg > > RiscVPkg/Library: RISC-V CPU library > > RiscVPkg/Library: Add RISC-V exception library > > RiscVPkg/Library: Add RISC-V timer library > > RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library. > > RiscVPkg/Library: RISC-V platform level DxeIPL libraries. > > MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL > > RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service > > Table Pointer library >=20 > PatchCheck.py warns about long line in commit message. >=20 > > RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary > > Memory library >=20 > PatchCheck.py warns about long line in commit message. >=20 > / > Leif >=20 > > RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver. > > BaseTools: BaseTools changes for RISC-V platform. > > BaseTools/Scripts > > RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V > > platforms. > > edk2-staging/RISC-V-V2: Add submodule > > edk2-staging/RISC-V-V2: Add ReadMe > > edk2-staging: Update Maintainers.txt > > > > .gitmodules | 16 +- > > BaseTools/Conf/build_rule.template | 62 ++- > > BaseTools/Conf/tools_def.template | 64 ++- > > BaseTools/Scripts/GccBaseRiscV.lds | 66 +++ > > BaseTools/Source/C/Common/BasePeCoff.c | 15 +- > > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++ > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 ++++- > > BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 260 ++++++++- > > BaseTools/Source/C/GenFw/elf_common.h | 62 +++ > > .../Source/C/Include/IndustryStandard/PeImage.h | 6 + > > BaseTools/Source/Python/Common/DataType.py | 7 +- > > Maintainers.txt | 5 + > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +- > > MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 +++ > > MdeModulePkg/Logo/Logo.inf | 2 +- > > .../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +- > > MdePkg/Include/IndustryStandard/PeImage.h | 12 + > > MdePkg/Include/Library/BaseLib.h | 26 + > > MdePkg/Include/Protocol/DebugSupport.h | 55 ++ > > MdePkg/Include/Protocol/PxeBaseCode.h | 4 + > > MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++ > > MdePkg/Include/Uefi/UefiBaseType.h | 13 + > > MdePkg/Include/Uefi/UefiSpec.h | 5 + > > .../BaseCacheMaintenanceLib.inf | 4 + > > .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++ > > MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +- > > MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +- > > MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 + > > .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +- > > MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 > +++++++++++++++++++++ > > MdePkg/Library/BaseLib/BaseLib.inf | 18 +- > > MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 + > > MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 + > > MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 + > > MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 + > > MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 + > > MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 ++ > > .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 ++ > > MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 ++ > > .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 + > > MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 + > > MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 ++ > > .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++ > > MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++ > > MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + > > MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 + > > .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 + > > .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++ > > .../BaseSynchronizationLib.inf | 6 + > > .../RiscV64/Synchronization.c | 183 +++++++ > > .../RiscV64/SynchronizationAsm.S | 78 +++ > > MdePkg/MdePkg.dec | 5 +- > > NetworkPkg/Network.dsc.inc | 2 +- > > RiscVEdk2Readme.md | 34 ++ > > RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++ > > RiscVPkg/Include/Library/RiscVCpuLib.h | 68 +++ > > RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++ > > .../Library/RiscVPlatformTempMemoryInitLib.h | 17 + > > RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++ > > RiscVPkg/Include/RiscV.h | 72 +++ > > RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++ > > RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++ > > RiscVPkg/Include/sbi/sbi.h | 96 ++++ > > RiscVPkg/Include/sbi/sbi_bits.h | 17 + > > RiscVPkg/Include/sbi/sbi_types.h | 18 + > > .../PeiServicesTablePointerLibOpenSbi.inf | 38 ++ > > .../PeiServicesTablePointerLibOpenSbi.uni | 23 + > > .../PeiServicesTablePointerOpenSbi.c | 121 +++++ > > RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 ++++ > > RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++ > > .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 ++ > > .../RiscVDxeIplHandoffLib.inf | 32 ++ > > .../RiscVDxeIplHandoffOpenSbiLib.c | 102 ++++ > > .../RiscVDxeIplHandoffOpenSbiLib.inf | 33 ++ > > .../RiscVExceptionLib/CpuExceptionHandler.S | 88 +++ > > .../CpuExceptionHandlerDxeLib.inf | 42 ++ > > .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++ > > .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 + > > .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++ > > .../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++ > > .../Riscv64/TempMemInit.S | 26 + > > .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++ > > RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++ > > RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 + > > RiscVPkg/RiscVPkg.dec | 42 ++ > > RiscVPkg/RiscVPkg.uni | 13 + > > RiscVPkg/RiscVPkgExtra.uni | 13 + > > RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 +++++++++++ > > RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++ > > RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++ > > RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 + > > RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 + > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 ++++++++++++ > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++ > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++ > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 + > > .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 + > > RiscVPkg/opensbi | 1 + > > 100 files changed, 6085 insertions(+), 66 deletions(-) create mode > > 100644 BaseTools/Scripts/GccBaseRiscV.lds > > create mode 100644 > MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > > create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h > > create mode 100644 > > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > > create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S > > create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c > > create mode 100644 > > MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c > > create mode 100644 > > MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S > > create mode 100644 > > MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c > > create mode 100644 > > MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c > > create mode 100644 > > MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c > > create mode 100644 > > MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S > > create mode 100644 RiscVEdk2Readme.md create mode 100644 > > RiscVPkg/Include/IndustryStandard/RiscV.h > > create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h > > create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h > > create mode 100644 > > RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h > > create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h > > create mode 100644 RiscVPkg/Include/RiscV.h create mode 100644 > > RiscVPkg/Include/SmbiosProcessorSpecificData.h > > create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h > > create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644 > > RiscVPkg/Include/sbi/sbi_bits.h create mode 100644 > > RiscVPkg/Include/sbi/sbi_types.h create mode 100644 > > RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoi > > nterLibOpenSbi.inf create mode 100644 > > RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoi > > nterLibOpenSbi.uni create mode 100644 > > RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoi > > nterOpenSbi.c create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S > > create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf > > create mode 100644 > > RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c > > create mode 100644 > > RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf > > create mode 100644 > > > RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS > b > > iLib.c create mode 100644 > > > RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS > b > > iLib.inf create mode 100644 > > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S > > create mode 100644 > > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf > > create mode 100644 > > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c > > create mode 100644 > > RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni > > create mode 100644 > > RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf > > create mode 100644 > > > RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTemp > M > > emoryInitLibNull.inf create mode 100644 > > > RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemI > ni > > t.S create mode 100644 > > RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf > > create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c > > create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h > > create mode 100644 RiscVPkg/RiscVPkg.dec create mode 100644 > > RiscVPkg/RiscVPkg.uni create mode 100644 RiscVPkg/RiscVPkgExtra.uni > > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c > > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h > > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf > > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni > > create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf > > create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni > > create mode 100644 > > RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni > > create mode 160000 RiscVPkg/opensbi > > > > -- > > 2.7.4 > > > > > > > > >=20 >=20