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Thread-Topic: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Thread-Index: AQHVcaqpKASTnjTMzUC8EhwQSPRQRqc6E4ww Date: Tue, 24 Sep 2019 01:57:53 +0000 Message-ID: References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <15C6EB99CBC780B5.2053@groups.io> In-Reply-To: <15C6EB99CBC780B5.2053@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [16.242.247.131] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c20140fe-0bb9-4774-e4b3-08d740929d19 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:CS1PR8401MB0983; x-ms-traffictypediagnostic: CS1PR8401MB0983: x-ms-exchange-purlcount: 1 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:163; x-forefront-prvs: 0170DAF08C x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(376002)(366004)(396003)(136003)(39860400002)(346002)(199004)(189003)(13464003)(2906002)(71200400001)(9686003)(71190400001)(30864003)(229853002)(52536014)(110136005)(99286004)(14454004)(316002)(66066001)(478600001)(5660300002)(966005)(256004)(86362001)(6116002)(26005)(6246003)(4326008)(74316002)(102836004)(54906003)(25786009)(8936002)(81156014)(486006)(476003)(81166006)(33656002)(66556008)(446003)(6436002)(11346002)(8676002)(305945005)(66946007)(3846002)(2501003)(76176011)(6306002)(19627235002)(7696005)(14444005)(76116006)(66476007)(7736002)(53546011)(6506007)(55016002)(186003)(64756008)(66446008);DIR:OUT;SFP:1102;SCL:1;SRVR:CS1PR8401MB0983;H:CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: hpe.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: KgT1tkuJNhJYGyMjRHiIfd9VvWf6NWsKHo+5mq6YHpLstvngCaRgH88datGNwLpYm0e9DKp7tY5wj8MvzKzDLnaBwGRTLarYhh/HjpOP0P9xbW9Ay2orld1SmPfyDQbdKZqKjL6CcazNXvF+0FiOXYgJ6B8GQfQwOr23IGVt9Lb0YzDacgjG1z056LVnaE8OCLlfruyb/FKFoVdjjzX9GwJofM8ACF5QVGCIRtbqsp4jDlZLpCC7xjVBmTfygS+i2zgphA7Y60CWZ07HdsUuV2FqyNABvMc4xMJfz43Sk8BhHIsfKJFU9BZtDrKCte1jEOtoRO3Ma53TQygP4WfcfmN/6ACwipTT8OapHWpPdy5MKwnnQO83wyMf7G/KFuBMyp6dQZpoOHsP/SJDFDsc5DAwfVhKDy31VJ+jcZPyu+Q= X-MS-Exchange-CrossTenant-Network-Message-Id: c20140fe-0bb9-4774-e4b3-08d740929d19 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2019 01:57:54.0027 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 6F83umpQu91U0mP95zT6L4mRqgA3hXMUhq546dMRpi4JfaJCg1nweEV5tYSTU2dSmkGX9w0nEO3+NZ1NLFzgKA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CS1PR8401MB0983 X-OriginatorOrg: hpe.com X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-09-23_10:2019-09-23,2019-09-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=983 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909240018 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable CC maintainers. > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Abner Chang > Sent: Monday, September 23, 2019 8:32 AM > To: devel@edk2.groups.io > Cc: Chang, Abner (HPS SW/FW Technologist) > Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] > MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance > implementation. >=20 > Implement RISC-V cache maintenance functions in > BaseCacheMaintenanceLib. >=20 > Signed-off-by: Abner Chang > --- > .../BaseCacheMaintenanceLib.inf | 4 + > .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 > +++++++++++++++++++++ > 2 files changed, 254 insertions(+) > create mode 100644 > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c >=20 > diff --git > a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > index ec7feec..d9bfa04 100644 > --- > a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > +++ > b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > @@ -6,6 +6,7 @@ > # > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. # > Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All > +rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ > [Sources.AARCH64] > ArmCache.c >=20 > +[Sources.RISCV64] > + RiscVCache.c > + > [Packages] > MdePkg/MdePkg.dec >=20 > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > new file mode 100644 > index 0000000..d8e4665 > --- /dev/null > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > @@ -0,0 +1,250 @@ > +/** @file > + RISC-V specific functionality for cache. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. > + All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#include > +#include > +#include > + > +/** > + RISC-V invalidate instruction cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateInstCacheAsm ( > + VOID > + ); > + > +/** > + RISC-V invalidate data cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateDataCacheAsm ( > + VOID > + ); > + > +/** > + Invalidates the entire instruction cache in cache coherency domain of > +the > + calling CPU. > + > +**/ > +VOID > +EFIAPI > +InvalidateInstructionCache ( > + VOID > + ) > +{ > + RiscVInvalidateInstCacheAsm (); > +} > + > +/** > + Invalidates a range of instruction cache lines in the cache coherency > +domain > + of the calling CPU. > + > + Invalidates the instruction cache lines specified by Address and > + Length. If Address is not aligned on a cache line boundary, then > + entire instruction cache line containing Address is invalidated. If > + Address + Length is not aligned on a cache line boundary, then the > + entire instruction cache line containing Address + Length -1 is > + invalidated. This function may choose to invalidate the entire > + instruction cache if that is more efficient than invalidating the > + specified range. If Length is 0, then no instruction cache lines are > invalidated. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the instruction cache lines to > + invalidate. If the CPU is in a physical addressing mo= de, then > + Address is a physical address. If the CPU is in a vir= tual > + addressing mode, then Address is a virtual address. > + > + @param Length The number of bytes to invalidate from the instructio= n > cache. > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateInstructionCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", > +__FUNCTION__)); > + return Address; > +} > + > +/** > + Writes back and invalidates the entire data cache in cache coherency > +domain > + of the calling CPU. > + > + Writes back and invalidates the entire data cache in cache coherency > + domain of the calling CPU. This function guarantees that all dirty > + cache lines are written back to system memory, and also invalidates > + all the data cache lines in the cache coherency domain of the calling= CPU. > + > +**/ > +VOID > +EFIAPI > +WriteBackInvalidateDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", > +__FUNCTION__)); } > + > +/** > + Writes back and invalidates a range of data cache lines in the cache > + coherency domain of the calling CPU. > + > + Writes back and invalidates the data cache lines specified by Address > + and Length. If Address is not aligned on a cache line boundary, then > + entire data cache line containing Address is written back and > + invalidated. If Address + Length is not aligned on a cache line > + boundary, then the entire data cache line containing Address + Length > + -1 is written back and invalidated. This function may choose to write > + back and invalidate the entire data cache if that is more efficient > + than writing back and invalidating the specified range. If Length is > + 0, then no data cache lines are written back and invalidated. Address= is > returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write bac= k > and > + invalidate. If the CPU is in a physical addressing mo= de, then > + Address is a physical address. If the CPU is in a vir= tual > + addressing mode, then Address is a virtual address. > + @param Length The number of bytes to write back and invalidate from > the > + data cache. > + > + @return Address of cache invalidation. > + > +**/ > +VOID * > +EFIAPI > +WriteBackInvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); > + return Address; > +} > + > +/** > + Writes back the entire data cache in cache coherency domain of the > +calling > + CPU. > + > + Writes back the entire data cache in cache coherency domain of the > + calling CPU. This function guarantees that all dirty cache lines are > + written back to system memory. This function may also invalidate all > + the data cache lines in the cache coherency domain of the calling CPU= . > + > +**/ > +VOID > +EFIAPI > +WriteBackDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); } > + > +/** > + Writes back a range of data cache lines in the cache coherency domain > +of the > + calling CPU. > + > + Writes back the data cache lines specified by Address and Length. If > + Address is not aligned on a cache line boundary, then entire data > + cache line containing Address is written back. If Address + Length is > + not aligned on a cache line boundary, then the entire data cache line > + containing Address + Length -1 is written back. This function may > + choose to write back the entire data cache if that is more efficient = than > writing back the specified range. > + If Length is 0, then no data cache lines are written back. This > + function may also invalidate all the data cache lines in the > + specified range of the cache coherency domain of the calling CPU. Add= ress > is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write bac= k. If > + the CPU is in a physical addressing mode, then Addres= s is a > + physical address. If the CPU is in a virtual addressi= ng > + mode, then Address is a virtual address. > + @param Length The number of bytes to write back from the data cache= . > + > + @return Address of cache written in main memory. > + > +**/ > +VOID * > +EFIAPI > +WriteBackDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); > + return Address; > +} > + > +/** > + Invalidates the entire data cache in cache coherency domain of the > +calling > + CPU. > + > + Invalidates the entire data cache in cache coherency domain of the > + calling CPU. This function must be used with care because dirty cache > + lines are not written back to system memory. It is typically used for > + cache diagnostics. If the CPU does not support invalidation of the > + entire data cache, then a write back and invalidate operation should = be > performed on the entire data cache. > + > +**/ > +VOID > +EFIAPI > +InvalidateDataCache ( > + VOID > + ) > +{ > + RiscVInvalidateDataCacheAsm (); > +} > + > +/** > + Invalidates a range of data cache lines in the cache coherency domain > +of the > + calling CPU. > + > + Invalidates the data cache lines specified by Address and Length. If > + Address is not aligned on a cache line boundary, then entire data > + cache line containing Address is invalidated. If Address + Length is > + not aligned on a cache line boundary, then the entire data cache line > + containing Address + Length -1 is invalidated. This function must > + never invalidate any cache lines outside the specified range. If > + Length is 0, then no data cache lines are invalidated. Address is > + returned. This function must be used with care because dirty cache > + lines are not written back to system memory. It is typically used for > + cache diagnostics. If the CPU does not support invalidation of a data > + cache range, then a write back and invalidate operation should be > performed on the data cache range. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to invalidat= e. If > + the CPU is in a physical addressing mode, then Addres= s is a > + physical address. If the CPU is in a virtual addressi= ng mode, > + then Address is a virtual address. > + @param Length The number of bytes to invalidate from the data cache= . > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); > + return Address; > +} > -- > 2.7.4 >=20 >=20 >=20