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Wed, 16 Oct 2019 01:36:07 +0000 From: "Abner Chang" To: "devel@edk2.groups.io" , "leif.lindholm@linaro.org" , "Chen, Gilbert" Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores Thread-Topic: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores Thread-Index: AQHVbp3JMPAKVXhKUkWP2KVOLghvG6dGXTsAgBZBhSA= Date: Wed, 16 Oct 2019 01:36:07 +0000 Message-ID: References: <20190919035131.4700-1-gilbert.chen@hpe.com> <20190919035131.4700-3-gilbert.chen@hpe.com> <20191001211438.GX25504@bivouac.eciton.net> In-Reply-To: <20191001211438.GX25504@bivouac.eciton.net> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [16.242.247.131] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f891e17a-8457-448d-a4a7-08d751d9379a x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: CS1PR8401MB0486: x-ms-exchange-purlcount: 1 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:304; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Leif Lindholm > Sent: Wednesday, October 2, 2019 5:15 AM > To: devel@edk2.groups.io; Chen, Gilbert > Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] > Silicon/SiFive: Add library module of SiFive RISC-V cores >=20 > On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote: > > Initial version of SiFive RISC-V core libraries. Library of each core > > creates processor core SMBIOS data hob for building SMBIOS records in > > DXE phase. >=20 > So yes, this implementation needs to change. > These should all implement the same LibraryClass. No. It shouldn't be the same library class (If you were saying the same Li= braryClass). RISC-V SoC could be the combination of different RISC-V cores,= or even the cores from different vendors. This depends on how SoC vendor c= ombine those IPs. Either U54 or E51 could be a standalone SoC, while U54MC is the combinatio= n of 4 x U54 core and one E51 core. U5MC under Platform/SiFive could be 1-8 U5 core and optionally support E5 = core. This is the special case for U500 VC707 platform because the core nu= mber could be customized. > Also, U54 appears to be a simple superset of U51. U54 is a single core.=20 >=20 > What I would suggest is creating a > Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a > SiFiveSoCCoreInfoLib in Silicon/SiFive//Library, providing the acua= l SoC- > specific bits. Platform system firmware integrator just pull in the necessary core librar= ies from Silicon/{vendor} and invoke the function to create specific core = bits. I think this implementation is well and flexible which has no need to chan= ge. >=20 > / > Leif >=20 > > Signed-off-by: Gilbert Chen > > --- > > .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 > +++++++++++++++++ > > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++ > > .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 294 > +++++++++++++++++++++ > > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++ > > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 185 ++++++++++++= + > > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 50 ++++ > > 6 files changed, 873 insertions(+) > > create mode 100644 > > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > create mode 100644 > > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf > > create mode 100644 > > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > create mode 100644 > > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf > > create mode 100644 > > Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > create mode 100644 > > > Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL > > ib.inf >=20 >=20