From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=01703bcc39=abner.chang@hpe.com) Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Mon, 23 Sep 2019 18:59:26 -0700 Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8O1uhpm023330 for ; Tue, 24 Sep 2019 01:59:25 GMT Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v6tjjpg8s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 24 Sep 2019 01:59:25 +0000 Received: from G4W10204.americas.hpqcorp.net (g4w10204.houston.hpecorp.net [16.207.82.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by g4t3427.houston.hpe.com (Postfix) with ESMTPS id C1C1C57 for ; Tue, 24 Sep 2019 01:59:24 +0000 (UTC) Received: from G4W10205.americas.hpqcorp.net (2002:10cf:520f::10cf:520f) by G4W10204.americas.hpqcorp.net (2002:10cf:5210::10cf:5210) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 24 Sep 2019 01:59:24 +0000 Received: from NAM04-CO1-obe.outbound.protection.outlook.com (15.241.52.10) by G4W10205.americas.hpqcorp.net (16.207.82.15) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Tue, 24 Sep 2019 01:59:24 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VIjHdXit6vIFcYnBx16FjvCRWkoiYW02Xudc/JsFsrduhzPfFY7fqKRd+o2wAKpzdPWqjZyaucpCJHs5MQ+nsFupdaP0tHuwlWHlB81oio8Py7uejKWqKHaB83T9v4Nv9lO4A2GqEhcunEqK+e28GQ82clGkloSt5DbAWo/jA1/OOttJ3uiNVn7aXJrSnXFhmTeRJ2qgoWSOT/o+0eo8mhR8oscJWyLFMBpQmNcBQYs1JWQydDkGYgh+sOjBzR5MTuv2zkPfRVBQsQbHaq3uggF843Xk+POmnDnTtuGu4IVMxQ6CM5LDH8kDXVtFKIYlxhC5+sQD3GCjRytrfExHVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UzExEGF8JoyuSpEAOEK7bRtTe4C+cIuE7gmteMBQNVY=; b=NR5Pi74F06GiEw7OWq0H6n+UUcH4uwDZE1U6PTjjzY/3/+ebszFdNZjCjaPC/FG4rvt+YlMvdrJYWLwl394o0J2TG1HQ/BZ798sgKe/+EBEdehRjuWkVEaJyzjYZHB9QnWX3w3P8hrl1O9MRu3Eq3jB/Z02iaRoEADV4e8TA4CC0e5pStSBBHEITYlu1LUwp+Nar3uklzSeEs60nwuDrZkflGyQWQVsA3fi0bO2saf4bC8Rj5d7EbNRgQsYYSHEP5rcxFITEdSeO48ljymD/aLVmvChH7FlvV/rnNKYOt1j17APdc3+qddnkQNcUS/AElGfqesZnKSlJZp0RM3sA/g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=hpe.com; dmarc=pass action=none header.from=hpe.com; dkim=pass header.d=hpe.com; arc=none Received: from CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM (10.169.12.151) by CS1PR8401MB1319.NAMPRD84.PROD.OUTLOOK.COM (10.169.12.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2284.26; Tue, 24 Sep 2019 01:59:22 +0000 Received: from CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4fb:84b9:76e6:1cde]) by CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4fb:84b9:76e6:1cde%8]) with mapi id 15.20.2284.023; Tue, 24 Sep 2019 01:59:22 +0000 From: "Abner Chang" To: "devel@edk2.groups.io" , "Chang, Abner (HPS SW/FW Technologist)" CC: Liming Gao , Michael D Kinney Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Thread-Topic: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Thread-Index: AQHVcaqvnv0lB0nLrUe3f4wZtG1jp6c6E9tw Date: Tue, 24 Sep 2019 01:59:22 +0000 Message-ID: References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <15C6EB99608359A3.24160@groups.io> In-Reply-To: <15C6EB99608359A3.24160@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [16.242.247.131] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ab765297-2920-4a64-9838-08d74092d1f2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:CS1PR8401MB1319; x-ms-traffictypediagnostic: CS1PR8401MB1319: x-ms-exchange-purlcount: 1 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:163; x-forefront-prvs: 0170DAF08C x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(396003)(136003)(39860400002)(366004)(376002)(346002)(13464003)(199004)(189003)(9686003)(5660300002)(99286004)(30864003)(76176011)(86362001)(26005)(102836004)(6506007)(7696005)(53546011)(3846002)(6116002)(71190400001)(186003)(81156014)(33656002)(8676002)(66946007)(81166006)(446003)(2906002)(476003)(66476007)(66446008)(64756008)(66556008)(2501003)(52536014)(71200400001)(486006)(11346002)(14444005)(4326008)(6246003)(74316002)(966005)(8936002)(54906003)(76116006)(25786009)(14454004)(7736002)(110136005)(316002)(19627235002)(478600001)(66066001)(6436002)(229853002)(6306002)(256004)(55016002)(305945005);DIR:OUT;SFP:1102;SCL:1;SRVR:CS1PR8401MB1319;H:CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: hpe.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: blPH0vgahkWGrMZC9pae1TL/p0YeJZ98f5Jsmv60EdTQFnQXepoFTLuDaBd0q4nT6XjZLPRnwoM2Qroe3LC3ejNY9nPRRiU0XVrRh0q+Gzv3wt1MXo9Rddm+m63C4nCrzAwaAAxzq11gOnTucVgQvrbJUbY2C4r5DcExeBdVWu//OQhAFPbM0gLoSuSZ8R2G6Z7De6yVEOsMRHBIzkTVVpJi3l52RUe0ASTrrTtxakWcdutAwPSF6r6kDNd8KZHjt2CFUk42jcNlBlzYSmRYMMWuWVOV0kCYuHxN8hzzGWlb9QBxJ2D3KhsqkDKYfCwwoTtf5bMxoYkKvNWPFFmRP912hoBvn+P0PGkTxsXHdPBfOELDB5+FELXaw8snZu4LMcpDAxVmHhVoOUdciaomwkxr6hvI8zhcZu8fhrqKKvw= X-MS-Exchange-CrossTenant-Network-Message-Id: ab765297-2920-4a64-9838-08d74092d1f2 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2019 01:59:22.5835 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ihDpl3vguxCIIB1i+/F0xE3ZOGkJZVsk/62dj0CTbxBcGHgl1ywwAYOi4wQjSbSzB3rQTr6BnggiyUNRQN2sHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CS1PR8401MB1319 X-OriginatorOrg: hpe.com X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-09-23_10:2019-09-23,2019-09-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=971 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909240018 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable CC maintainers. > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Abner Chang > Sent: Monday, September 23, 2019 8:32 AM > To: devel@edk2.groups.io > Cc: Chang, Abner (HPS SW/FW Technologist) > Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] > MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance > implementation. >=20 > Implement RISC-V cache maintenance functions in > BaseCacheMaintenanceLib. >=20 > Signed-off-by: Abner Chang > --- > .../BaseCacheMaintenanceLib.inf | 4 + > .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 > +++++++++++++++++++++ > 2 files changed, 254 insertions(+) > create mode 100644 > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c >=20 > diff --git > a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > index ec7feec..d9bfa04 100644 > --- > a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > +++ > b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in > f > @@ -6,6 +6,7 @@ > # > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. # > Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All > +rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ > [Sources.AARCH64] > ArmCache.c >=20 > +[Sources.RISCV64] > + RiscVCache.c > + > [Packages] > MdePkg/MdePkg.dec >=20 > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > new file mode 100644 > index 0000000..d8e4665 > --- /dev/null > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > @@ -0,0 +1,250 @@ > +/** @file > + RISC-V specific functionality for cache. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. > + All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#include > +#include > +#include > + > +/** > + RISC-V invalidate instruction cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateInstCacheAsm ( > + VOID > + ); > + > +/** > + RISC-V invalidate data cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateDataCacheAsm ( > + VOID > + ); > + > +/** > + Invalidates the entire instruction cache in cache coherency domain of > +the > + calling CPU. > + > +**/ > +VOID > +EFIAPI > +InvalidateInstructionCache ( > + VOID > + ) > +{ > + RiscVInvalidateInstCacheAsm (); > +} > + > +/** > + Invalidates a range of instruction cache lines in the cache coherency > +domain > + of the calling CPU. > + > + Invalidates the instruction cache lines specified by Address and > + Length. If Address is not aligned on a cache line boundary, then > + entire instruction cache line containing Address is invalidated. If > + Address + Length is not aligned on a cache line boundary, then the > + entire instruction cache line containing Address + Length -1 is > + invalidated. This function may choose to invalidate the entire > + instruction cache if that is more efficient than invalidating the > + specified range. If Length is 0, then no instruction cache lines are > invalidated. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the instruction cache lines to > + invalidate. If the CPU is in a physical addressing mo= de, then > + Address is a physical address. If the CPU is in a vir= tual > + addressing mode, then Address is a virtual address. > + > + @param Length The number of bytes to invalidate from the instructio= n > cache. > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateInstructionCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", > +__FUNCTION__)); > + return Address; > +} > + > +/** > + Writes back and invalidates the entire data cache in cache coherency > +domain > + of the calling CPU. > + > + Writes back and invalidates the entire data cache in cache coherency > + domain of the calling CPU. This function guarantees that all dirty > + cache lines are written back to system memory, and also invalidates > + all the data cache lines in the cache coherency domain of the calling= CPU. > + > +**/ > +VOID > +EFIAPI > +WriteBackInvalidateDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", > +__FUNCTION__)); } > + > +/** > + Writes back and invalidates a range of data cache lines in the cache > + coherency domain of the calling CPU. > + > + Writes back and invalidates the data cache lines specified by Address > + and Length. If Address is not aligned on a cache line boundary, then > + entire data cache line containing Address is written back and > + invalidated. If Address + Length is not aligned on a cache line > + boundary, then the entire data cache line containing Address + Length > + -1 is written back and invalidated. This function may choose to write > + back and invalidate the entire data cache if that is more efficient > + than writing back and invalidating the specified range. If Length is > + 0, then no data cache lines are written back and invalidated. Address= is > returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write bac= k > and > + invalidate. If the CPU is in a physical addressing mo= de, then > + Address is a physical address. If the CPU is in a vir= tual > + addressing mode, then Address is a virtual address. > + @param Length The number of bytes to write back and invalidate from > the > + data cache. > + > + @return Address of cache invalidation. > + > +**/ > +VOID * > +EFIAPI > +WriteBackInvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); > + return Address; > +} > + > +/** > + Writes back the entire data cache in cache coherency domain of the > +calling > + CPU. > + > + Writes back the entire data cache in cache coherency domain of the > + calling CPU. This function guarantees that all dirty cache lines are > + written back to system memory. This function may also invalidate all > + the data cache lines in the cache coherency domain of the calling CPU= . > + > +**/ > +VOID > +EFIAPI > +WriteBackDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); } > + > +/** > + Writes back a range of data cache lines in the cache coherency domain > +of the > + calling CPU. > + > + Writes back the data cache lines specified by Address and Length. If > + Address is not aligned on a cache line boundary, then entire data > + cache line containing Address is written back. If Address + Length is > + not aligned on a cache line boundary, then the entire data cache line > + containing Address + Length -1 is written back. This function may > + choose to write back the entire data cache if that is more efficient = than > writing back the specified range. > + If Length is 0, then no data cache lines are written back. This > + function may also invalidate all the data cache lines in the > + specified range of the cache coherency domain of the calling CPU. Add= ress > is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write bac= k. If > + the CPU is in a physical addressing mode, then Addres= s is a > + physical address. If the CPU is in a virtual addressi= ng > + mode, then Address is a virtual address. > + @param Length The number of bytes to write back from the data cache= . > + > + @return Address of cache written in main memory. > + > +**/ > +VOID * > +EFIAPI > +WriteBackDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); > + return Address; > +} > + > +/** > + Invalidates the entire data cache in cache coherency domain of the > +calling > + CPU. > + > + Invalidates the entire data cache in cache coherency domain of the > + calling CPU. This function must be used with care because dirty cache > + lines are not written back to system memory. It is typically used for > + cache diagnostics. If the CPU does not support invalidation of the > + entire data cache, then a write back and invalidate operation should = be > performed on the entire data cache. > + > +**/ > +VOID > +EFIAPI > +InvalidateDataCache ( > + VOID > + ) > +{ > + RiscVInvalidateDataCacheAsm (); > +} > + > +/** > + Invalidates a range of data cache lines in the cache coherency domain > +of the > + calling CPU. > + > + Invalidates the data cache lines specified by Address and Length. If > + Address is not aligned on a cache line boundary, then entire data > + cache line containing Address is invalidated. If Address + Length is > + not aligned on a cache line boundary, then the entire data cache line > + containing Address + Length -1 is invalidated. This function must > + never invalidate any cache lines outside the specified range. If > + Length is 0, then no data cache lines are invalidated. Address is > + returned. This function must be used with care because dirty cache > + lines are not written back to system memory. It is typically used for > + cache diagnostics. If the CPU does not support invalidation of a data > + cache range, then a write back and invalidate operation should be > performed on the data cache range. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to invalidat= e. If > + the CPU is in a physical addressing mode, then Addres= s is a > + physical address. If the CPU is in a virtual addressi= ng mode, > + then Address is a virtual address. > + @param Length The number of bytes to invalidate from the data cache= . > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", > +__FUNCTION__)); > + return Address; > +} > -- > 2.7.4 >=20 >=20 >=20