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Thu, 17 Oct 2019 02:21:01 +0000 From: "Abner Chang" To: "devel@edk2.groups.io" , "leif.lindholm@linaro.org" , "Chen, Gilbert" CC: Palmer Dabbelt Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 10/14] U500Pkg/Library: Library instances of U500 platform library Thread-Topic: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 10/14] U500Pkg/Library: Library instances of U500 platform library Thread-Index: AQHVbp2YasLRrKgvHku/2C2deVoK5adJMwUAgBUQq7A= Date: Thu, 17 Oct 2019 02:21:01 +0000 Message-ID: References: <20190919035131.4700-1-gilbert.chen@hpe.com> <20190919035131.4700-11-gilbert.chen@hpe.com> <20191003163220.GN25504@bivouac.eciton.net> In-Reply-To: <20191003163220.GN25504@bivouac.eciton.net> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [16.242.247.131] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a2c7b34e-2201-4b9d-9958-08d752a8a788 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: CS1PR8401MB0358: x-ms-exchange-purlcount: 2 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:172; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Leif Lindholm > Sent: Friday, October 4, 2019 12:32 AM > To: devel@edk2.groups.io; Chen, Gilbert > Cc: Palmer Dabbelt > Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 10/14] > U500Pkg/Library: Library instances of U500 platform library >=20 > On Thu, Sep 19, 2019 at 11:51:27AM +0800, Gilbert Chen wrote: > > OpneSbiPlatformLib > > - In order to reduce the dependencies with RISC-V OpenSBI project > > (https://github.com/riscv/opensbi) and less burdens to EDK2 build > > process, the implementation of RISC-V EDK2 platform is leverage > > platform source code from OpenSBI code tree. The "platform.c" > > under OpenSbiPlatformLib is cloned from RISC-V OpenSBI code tree (in > > EDK2 RiscVPkg) and built based on EDK2 build environment. > > > > PeiCoreInfoHobLib > > - This is the library to create RISC-V core characteristics for > > building up RISC-V related SMBIOS records to support the unified boot > > loader and OS image. > > > > - RiscVPlatformTimerLib > > This is U500 platform timer library which has the platform-specific > > timer implementation. > > > > - SerialPortLib > > U500 serial port platform library >=20 > Please split this up into the 4 logical commits. > And add the specific header files with those commits. >=20 > > Signed-off-by: Gilbert Chen > > --- > > .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 47 ++++ > > .../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 214 > ++++++++++++++++++ > > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 195 > +++++++++++++++++ > > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 58 +++++ > > .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S | 48 ++++ > > .../RiscVPlatformTimerLib.inf | 39 ++++ > > .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf | 31 +++ > > .../U500Pkg/Library/SerialIoLib/SerialPortLib.c | 241 > +++++++++++++++++++++ > > .../Library/SerialIoLib/U500SerialPortLib.uni | 16 ++ > > 9 files changed, 889 insertions(+) > > create mode 100644 > > > Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatfo > > rmLib.inf create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c > > create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > create mode 100644 > > > Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHob > > Lib.inf create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatf > > ormTimerLib.S create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatf > > ormTimerLib.inf create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf > > create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c > > create mode 100644 > > Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.un > > i > > > > diff --git > > > a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlat > > formLib.inf > > > b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlat > > formLib.inf > > new file mode 100644 > > index 00000000..473386d2 > > --- /dev/null > > +++ > b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbi > > +++ PlatformLib.inf > > @@ -0,0 +1,47 @@ > > +## @file > > +# RISC-V OpenSbi Platform Library > > +# This is the the required library which provides platform >=20 > Please don't use the word required. (If it wasn't, why would you include= it at > all?) >=20 > > +# level opensbi functions follow RISC-V opensbi implementation. > > +# > > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > +rights reserved.
# # SPDX-License-Identifier: > > +BSD-2-Clause-Patent # ## > > + > > +[Defines] > > + INF_VERSION =3D 0x00010005 >=20 > Please bump specification version. >=20 > > + BASE_NAME =3D OpenSbiPlatformLib > > + FILE_GUID =3D 9424ED54-EBDA-4FB5-8FF6-8291B07B= B151 > > + MODULE_TYPE =3D SEC > > + VERSION_STRING =3D 1.0 > > + LIBRARY_CLASS =3D OpenSbiPlatformLib >=20 > Seeing this, I have a bit of a feeling that this Opensbi isn't being con= sistently > treated/named: > - In edk2, we have RiscVPkg/Library/RiscVOpensbiLib which implements > class RiscVOpensbiLib. > - Here, we have U500Pkg/Library/OpenSbiPlatformLib implementing the > class OpenSbiPlatformLib. > - *Logically*, what we have is > Platform/RiscV/Universal/Sec/SecMain.inf which depends on the > OpensbiLib which depends on the OpenSbiPlatformLib. > - However, there is no OpenSbiPlatformLib in edk2, which is very > unfortunate because that does not let us build edk2/RiscVPkg in > isolation (like we can with all the other packages in edk2). Will name it as Opensbi. >=20 > Here is my preferred solution for untangling this: > 1) Standardise on OpenSbi or Opensbi. Opensbi follows the pattern we > already use for Openssl, so would be my preference. > 2) Standardise on RiscVOpensbi or Opensbi - both for filenames and > LibararyClasses. Either is fine, the former is less likely to clash > with other imported projects in the future (but I would estimate > this risk as *very* low to begin with). > 3) Implement a (RiscV)OpensbiPlatformLibNull in edk2/RiscVPkg/Library, I will have OpensbiPlatformLibNull in RiscVPlatformPkg/Library > containing only what is required to build/link > RiscVPkg/Library/(RiscV)OpensbiLib/. > 3.5) Map that to OpensbiPlatformLib in RiscVPkg/RiscVPkg.dsc. > 3.6) Add a depedency on OpensbiPlatformLib to > (RiscV)OpensbiLib.inf > 3.7) Drop the dependency on OpensbiPlatformLib from > Platform/RiscV/Universal/Sec/SecMain.inf Above work for me >=20 > (That might read like a lot of work, but really it's a 5 minute job and = if we > untangle this now, this won't cascade over umpteen > platforms.) >=20 > > + > > +# > > +# The following information is for reference only and not required by= the > build tools. > > +# > > +# VALID_ARCHITECTURES =3D RISCV64 EBC >=20 > Drop EBC. >=20 > > +# > > + > > +[Sources] > > + platform.c >=20 > Please rename as Platform.c. >=20 > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + RiscVPkg/RiscVPkg.dec > > + Platform/RiscV/RiscVPlatformPkg.dec >=20 > Please sort files alphabetically. >=20 > > + > > +[LibraryClasses] > > + BaseLib > > + DebugLib > > + BaseMemoryLib > > + PcdLib > > + DebugAgentLib > > + RiscVCpuLib > > + PrintLib >=20 > Please sort LibraryClasses alphabetically. >=20 > > + > > +[FixedPcd] > > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount > > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize > > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId >=20 > Please sort Pcds alphabetically. >=20 > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c > > b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c > > new file mode 100644 > > index 00000000..4dca75f2 > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platfor > > +++ m.c > > @@ -0,0 +1,214 @@ > > +/* > > + * SPDX-License-Identifier: BSD-2-Clause > > + * > > + * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > +rights reserved.
> > + * Copyright (c) 2019 Western Digital Corporation or its affiliates. > > + * > > + * Authors: > > + * Atish Patra >=20 > Please change commit Author instead. >=20 > Please point out that this is the platform-specific portion of OpensbiLi= b. With > that, I'm OK with it not following EDK2 coding style. *However*, it need= s to > follow OpenSBI coding style, and it currently doesn't - 3-space indentat= ion > follows nothing. >=20 > From what I see, OpenSBI follows Linux coding style. So please update to > that, throughout this file. *if* you untabify it (8 spaces/tab) before > submission, our tools will complain less, so do consider that. >=20 > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include #include > > + > > + > > + > > +#define U500_HART_COUNT FixedPcdGet32(PcdHartCount) > > +#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize) > > +#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId) > > + > > +#define U500_SYS_CLK 100000000 > > + > > +#define U500_CLINT_ADDR 0x2000000 > > + > > +#define U500_PLIC_ADDR 0xc000000 > > +#define U500_PLIC_NUM_SOURCES 0x35 > > +#define U500_PLIC_NUM_PRIORITIES 7 > > + > > +#define U500_UART_ADDR 0x54000000 > > + > > +#define U500_UART_BAUDRATE 115200 > > + > > +/** > > + * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode. > > + * HARTs 1 is selected as boot HART > > + */ > > +#ifndef U500_ENABLED_HART_MASK > > +#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID) > > +#endif > > + > > +#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK) > > + > > +/* PRCI clock related macros */ > > +//TODO: Do we need a separate driver for this ? >=20 > Well, do we? >=20 > > +#define U500_PRCI_BASE_ADDR 0x10000000 > > +#define U500_PRCI_CLKMUXSTATUSREG 0x002C > > +#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1) >=20 > Please adjust right-column alignment through the defines above. >=20 > > + > > +static void U500_modify_dt(void *fdt) { > > + u32 i, size; >=20 >=20 > > + int chosen_offset, err; > > + int cpu_offset; > > + char cpu_node[32] =3D ""; > > + const char *mmu_type; > > + > > + for (i =3D 0; i < U500_HART_COUNT; i++) { > > + sbi_sprintf(cpu_node, "/cpus/cpu@%d", i); > > + cpu_offset =3D fdt_path_offset(fdt, cpu_node); > > + mmu_type =3D fdt_getprop(fdt, cpu_offset, "mmu-type", NULL); > > + if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") || > > + !strcmp(mmu_type,"riscv,sv48"))) > > + continue; > > + else > > + fdt_setprop_string(fdt, cpu_offset, "status", "masked"); > > + memset(cpu_node, 0, sizeof(cpu_node)); > > + } > > + size =3D fdt_totalsize(fdt); > > + err =3D fdt_open_into(fdt, fdt, size + 256); > > + if (err < 0) > > + sbi_printf("Device Tree can't be expanded to accmodate new > > + node"); > > + > > + chosen_offset =3D fdt_path_offset(fdt, "/chosen"); > > + fdt_setprop_string(fdt, chosen_offset, "stdout-path", > > + "/soc/serial@10010000:115200"); > > + > > + plic_fdt_fixup(fdt, "riscv,plic0"); } > > + > > +static int U500_final_init(bool cold_boot) { > > + void *fdt; > > + > > + if (!cold_boot) > > + return 0; > > + > > + fdt =3D sbi_scratch_thishart_arg1_ptr(); > > + U500_modify_dt(fdt); > > + > > + return 0; > > +} > > + > > +static u32 U500_pmp_region_count(u32 hartid) { > > + return 1; > > +} > > + > > +static int U500_pmp_region_info(u32 hartid, u32 index, > > + ulong *prot, ulong *addr, ulong *log2size) { > > + int ret =3D 0; > > + > > + switch (index) { > > + case 0: > > + *prot =3D PMP_R | PMP_W | PMP_X; > > + *addr =3D 0; > > + *log2size =3D __riscv_xlen; > > + break; > > + default: > > + ret =3D -1; > > + break; > > + }; > > + > > + return ret; > > +} > > + > > +static int U500_console_init(void) > > +{ > > + unsigned long peri_in_freq; > > + > > + peri_in_freq =3D U500_SYS_CLK/2; > > + return sifive_uart_init(U500_UART_ADDR, peri_in_freq, > > +U500_UART_BAUDRATE); } > > + > > +static int U500_irqchip_init(bool cold_boot) { > > + int rc; > > + u32 hartid =3D sbi_current_hartid(); > > + > > + if (cold_boot) { > > + rc =3D plic_cold_irqchip_init(U500_PLIC_ADDR, > > + U500_PLIC_NUM_SOURCES, > > + U500_HART_COUNT); > > + if (rc) > > + return rc; > > + } > > + > > + return plic_warm_irqchip_init(hartid, > > + (hartid) ? (2 * hartid - 1) : 0, > > + (hartid) ? (2 * hartid) : -1); } > > + > > +static int U500_ipi_init(bool cold_boot) { > > + int rc; > > + > > + if (cold_boot) { > > + rc =3D clint_cold_ipi_init(U500_CLINT_ADDR, > > + U500_HART_COUNT); > > + if (rc) > > + return rc; > > + > > + } > > + > > + return clint_warm_ipi_init(); > > +} > > + > > +static int U500_timer_init(bool cold_boot) { > > + int rc; > > + > > + if (cold_boot) { > > + rc =3D clint_cold_timer_init(U500_CLINT_ADDR, > > + U500_HART_COUNT); > > + if (rc) > > + return rc; > > + } > > + > > + return clint_warm_timer_init(); > > +} > > + > > +static int U500_system_down(u32 type) { > > + /* For now nothing to do. */ > > + return 0; > > +} > > + > > +const struct sbi_platform_operations platform_ops =3D { > > + .pmp_region_count =3D U500_pmp_region_count, > > + .pmp_region_info =3D U500_pmp_region_info, > > + .final_init =3D U500_final_init, > > + .console_putc =3D sifive_uart_putc, > > + .console_getc =3D sifive_uart_getc, > > + .console_init =3D U500_console_init, > > + .irqchip_init =3D U500_irqchip_init, > > + .ipi_send =3D clint_ipi_send, > > + .ipi_sync =3D clint_ipi_sync, > > + .ipi_clear =3D clint_ipi_clear, > > + .ipi_init =3D U500_ipi_init, > > + .timer_value =3D clint_timer_value, > > + .timer_event_stop =3D clint_timer_event_stop, > > + .timer_event_start =3D clint_timer_event_start, > > + .timer_init =3D U500_timer_init, > > + .system_reboot =3D U500_system_down, > > + .system_shutdown =3D U500_system_down }; > > + > > +const struct sbi_platform platform =3D { > > + .opensbi_version =3D OPENSBI_VERSION, // The Op= enSBI > version this platform table is built bassed on. > > + .platform_version =3D SBI_PLATFORM_VERSION(0x0001, 0x0000), //= SBI > Platform version 1.0 > > + .name =3D "SiFive Freedom U500", > > + .features =3D SBI_PLATFORM_DEFAULT_FEATURES, > > + .hart_count =3D U500_HART_COUNT, > > + .hart_stack_size =3D U500_HART_STACK_SIZE, > > + .disabled_hart_mask =3D U500_HARTID_DISABLED, > > + .platform_ops_addr =3D (unsigned long)&platform_ops > > +}; > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob. > > c > > b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob. > > c > > new file mode 100644 > > index 00000000..bfb97351 > > --- /dev/null > > +++ > b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfo > > +++ Hob.c > > @@ -0,0 +1,195 @@ > > +/**@file > > + Build up platform processor information. > > + > > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > + rights reserved.
> > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +// > > +// The package level header files this module uses // #include > > + > > + > > +// > > +// The Library classes this module consumes // #include > > + #include #include > > + > > + > > +#include #include > > + #include > #include > > + #include >=20 > Please sort includes alphabetically. >=20 > > + > > +/** > > + Build up processor-specific HOB for U5MC Coreplex > > + > > + @param UniqueId Unique ID of this U5MC Coreplex processor > > + > > + @return EFI_SUCCESS The PEIM initialized successfully. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +CreateU5MCCoreplexProcessorSpecificDataHob ( > > + IN UINTN UniqueId > > + ) > > +{ > > + EFI_STATUS Status; > > + UINT32 HartIdNumber; > > + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData; > > + EFI_GUID *ParentCoreGuid; > > + BOOLEAN MCSupport; > > + > > + DEBUG ((DEBUG_INFO, "Building U5 Coreplex processor information > > + HOB\n")); > > + > > + HartIdNumber =3D 0; > > + ParentCoreGuid =3D PcdGetPtr(PcdSiFiveU5MCCoreplexGuid); > > + MCSupport =3D PcdGetBool (PcdE5MCSupported); if (MCSupport =3D=3D = TRUE) > > + { > > + Status =3D CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, > UniqueId, HartIdNumber, FALSE, &GuidHobData); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino > HOB\n")); > > + ASSERT (FALSE); > > + } > > + HartIdNumber ++; > > + DEBUG ((DEBUG_INFO, "Support E5 Monitor core on U500 platform, > > + HOB at address 0x%x\n", GuidHobData)); >=20 > Hmm, OK, this was why you had the different LibraryClasses? > I still don't think it should be a separate libraryclass per CPU. If pos= sible, I > would prefer MonitorCoreInfoLib and ApplicationCoreInfoLib. >=20 > > + } > > + for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + > (UINT32)MCSupport); HartIdNumber ++) { > > + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, > > + UniqueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 > > + (PcdBootHartId))? TRUE: FALSE, &GuidHobData); >=20 > Nesting that ternary saves you nothing other than typing, and not much o= f > that. Please use a temporary variable instead: >=20 > BOOL IsBootHart; > IsBootHart =3D HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId)) ? T= RUE : > FALSE > /* Also, always spaces around ? and : for ternaries. */ > /* No, don't actually include this comment. */ > Status =3D CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, > UniqueId, > HartIdNumber, IsBootHart, &GuidHobData); >=20 > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino > HOB\n")); > > + ASSERT (FALSE); > > + } > > + DEBUG ((DEBUG_INFO, "Support U5 application core on U500 > > + platform, HOB Data at address 0x%x\n", GuidHobData)); } DEBUG > > + ((DEBUG_INFO, "Support %d U5 application cores on U500 platform\n", > > + HartIdNumber - (UINT32)MCSupport)); >=20 > Please wrap those DEBUG lines. Not the strings, just the arguments. >=20 > > + > > + if (HartIdNumber !=3D FixedPcdGet32 (PcdHartCount)) { > > + DEBUG ((DEBUG_ERROR, "Improper core settings...\n")); > > + DEBUG ((DEBUG_ERROR, " PcdHartCount\n")); > > + DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n")); > > + DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n")); > > + ASSERT (FALSE); > > + } > > + return Status; > > +} > > + > > +/** > > + Function to build processor related SMBIOS information. RISC-V > > +SMBIOS DXE driver collect > > + this information and build SMBIOS Type4 and Type7 record. > > + > > + @param ProcessorUid Unique ID of pysical processor which owns t= his > core. > > + @param SmbiosHobPtr Pointer to receive > RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers > > + maintained in this structure is only valid = before memory is > discovered. > > + Access to those pointers after memory is in= stalled will cause > unexpected issues. > > + > > + @return EFI_SUCCESS The PEIM initialized successfully. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +CreateU5MCProcessorSmbiosDataHob ( > > + IN UINTN ProcessorUid, > > + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr > > + ) > > +{ > > + EFI_GUID *GuidPtr; > > + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; > > + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; > > + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; > > + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; > > + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; > > + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; > > + > > + DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); > > + > > + if (SmbiosHobPtr =3D=3D NULL) { > > + return EFI_INVALID_PARAMETER; > > + } > > + > > + // > > + // Build up SMBIOS type 7 L2 cache record. > > + // > > + ZeroMem((VOID *)&L2CacheDataHob, sizeof > > + (RISC_V_PROCESSOR_TYPE7_DATA_HOB)); > > + L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr > > + (PcdSiFiveU5MCCoreplexGuid)); L2CacheDataHob.ProcessorUid =3D > > + ProcessorUid; L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D > > + TO_BE_FILLED_BY_VENDOR; > L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D > RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \ > > + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ > > + RISC_V_CACHE_CONFIGURATION_ENABLED | \ > > + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; > > + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D > > + TO_BE_FILLED_BY_VENDOR; > > + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D > > + TO_BE_FILLED_BY_VENDOR; > > + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; > > + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; > > + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D > TO_BE_FILLED_BY_VENDOR; > > + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D > > + TO_BE_FILLED_BY_VENDOR; > > + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D > CacheTypeUnified; > > + L2CacheDataHob.SmbiosType7Cache.Associativity =3D > > + TO_BE_FILLED_BY_VENDOR; GuidPtr =3D (EFI_GUID *)PcdGetPtr > > + (PcdProcessorSmbiosType7GuidHobGuid); > > + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB > > + *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof > > + (RISC_V_PROCESSOR_TYPE7_DATA_HOB)); >=20 > Please wrap long line. >=20 > > + if (L2CacheDataHobPtr =3D=3D NULL) { > > + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC > > + Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); >=20 > Please wrap long line. (That format string is longer than 80 characters = on its > own, consider shortening it.) >=20 > > + ASSERT (FALSE); > > + } > > + > > + // > > + // Build up SMBIOS type 4 record. > > + // > > + ZeroMem((VOID *)&ProcessorDataHob, sizeof > > + (RISC_V_PROCESSOR_TYPE4_DATA_HOB)); > > + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr > > + (PcdSiFiveU5MCCoreplexGuid)); ProcessorDataHob.ProcessorUid =3D > > + ProcessorUid; ProcessorDataHob.SmbiosType4Processor.Socket =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D > > + CentralProcessor; > > + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D > > + ProcessorFamilyIndicatorFamily2; > > + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D > > + TO_BE_FILLED_BY_VENDOR; SetMem ((VOID > > + *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof > > + (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); >=20 > Please wrap long line. >=20 > > + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D > > + TO_BE_FILLED_BY_VENDOR; > > + > ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapabi > > + lity3_3V =3D 1; ProcessorDataHob.SmbiosType4Processor.ExternalClock= =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.Status =3D > TO_BE_FILLED_BY_CODE; > > + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D > > + TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER; > > + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D > > + TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER; > > + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; > > + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D > > + TO_BE_FILLED_BY_CODE; > > + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D > > + TO_BE_FILLED_BY_VENDOR; > > + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D > > + (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool > > + (PcdE5MCSupported); > > + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D > > + (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool > > + (PcdE5MCSupported); > > + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D > > + (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool > > + (PcdE5MCSupported); >=20 > Please wrap long lines. > There are several more cases in this file, I'll stop pointing them out, = but the > general rule is no longer than 80. PatchCheck.py is a bit lax on this. >=20 > > + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D > > + (UINT16)(1 << 2); // 64-bit capable > > + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D > > + ProcessorFamilyRiscVRV64; > > + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; > > + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; > > + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; GuidPtr = = =3D > > + (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); > > + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB > > + *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof > > + (RISC_V_PROCESSOR_TYPE4_DATA_HOB)); > > + if (ProcessorDataHobPtr =3D=3D NULL) { > > + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC > Coreplex RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n")); > > + ASSERT (FALSE); > > + } > > + > > + ZeroMem((VOID *)&SmbiosDataHob, sizeof > > +(RISC_V_PROCESSOR_SMBIOS_DATA_HOB)); > > + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; > > + SmbiosDataHob.L1InstCache =3D NULL; > > + SmbiosDataHob.L1DataCache =3D NULL; > > + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; > > + SmbiosDataHob.L3Cache =3D NULL; > > + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); > > + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB > > +*)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof > > +(RISC_V_PROCESSOR_SMBIOS_DATA_HOB)); > > + if (SmbiosDataHobPtr =3D=3D NULL) { > > + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC > Coreplex RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n")); > > + ASSERT (FALSE); > > + } > > + *SmbiosHobPtr =3D SmbiosDataHobPtr; > > + DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__)); > > + return EFI_SUCCESS; > > +} > > diff --git > > > a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoH > > obLib.inf > > > b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoH > > obLib.inf > > new file mode 100644 > > index 00000000..915021f9 > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreI > > +++ nfoHobLib.inf > > @@ -0,0 +1,58 @@ > > +## @file > > +# Library instance to create core information HOB # # Copyright (c) > > +2019, Hewlett Packard Enterprise Development LP. All rights > > +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## > > + > > +[Defines] > > + INF_VERSION =3D 0x00010005 >=20 > Please bump specification version. >=20 > > + BASE_NAME =3D SiliconSiFiveU5MCCoreplexInfoLib > > + FILE_GUID =3D 4E397A71-5164-4E69-9884-70CBE274= 0AAB > > + MODULE_TYPE =3D PEIM > > + VERSION_STRING =3D 1.0 > > + LIBRARY_CLASS =3D SiliconSiFiveU5MCCoreplexInfoLib > > + > > +# > > +# The following information is for reference only and not required by= the > build tools. > > +# > > +# VALID_ARCHITECTURES =3D RISCV > > +# > > + > > +[Sources] > > + CoreInfoHob.c > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + Platform/RiscV/RiscVPlatformPkg.dec > > + Platform/RiscV/SiFive/U500Pkg/U500.dec > > + Silicon/SiFive/SiFive.dec > > + RiscVPkg/RiscVPkg.dec >=20 > Please sort alphabetically. >=20 > > + > > +[LibraryClasses] > > + BaseLib > > + PcdLib > > + MemoryAllocationLib > > + PrintLib > > + SiliconSiFiveE51CoreInfoLib > > + SiliconSiFiveU54CoreInfoLib >=20 > Please sort alphabetically. >=20 > > + > > +[Guids] > > + gUefiRiscVPlatformU500PkgTokenSpaceGuid >=20 > I'm reasonably sure you don't need to declare the TokenSpaceGuid in orde= r > to access the Pcds. >=20 > > + > > +[Ppis] > > + > > +[FixedPcd] > > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid > > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid > > + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid > > + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid > > + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid > > + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU5MCCoreplexGuid > > + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores > > + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported > > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount > > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId >=20 > Please sort alphabetically. >=20 > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPla > > tformTimerLib.S > > b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPla > > tformTimerLib.S > > new file mode 100644 > > index 00000000..bb4aafb9 > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/Risc > > +++ VPlatformTimerLib.S > > @@ -0,0 +1,48 @@ > > +//------------------------------------------------------------------- > > +----------- > > +// > > +// SiFive U500 Timer CSR functions. > > +// > > +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > +rights reserved.
// // SPDX-License-Identifier: > > +BSD-2-Clause-Patent // > > +//------------------------------------------------------------------- > > +----------- > > +#include > > +#include > > +#include > > + > > +.data > > + > > +.text > > +.align 3 > > + > > +.global ASM_PFX(RiscVReadMachineTimer) .global > > +ASM_PFX(RiscVSetMachineTimerCmp) .global > > +ASM_PFX(RiscVReadMachineTimerCmp) > > + > > +// > > +// Read machine timer CSR. > > +// @retval a0 : 64-bit machine timer. > > +// > > +ASM_PFX (RiscVReadMachineTimer): > > + li t1, CLINT_REG_MTIME > > + ld a0, (t1) > > + ret > > + > > +// > > +// Set machine timer compare CSR. > > +// @param a0 : UINT64 > > +// > > +ASM_PFX (RiscVSetMachineTimerCmp): > > + li t1, CLINT_REG_MTIMECMP0 > > + sd a0, (t1) > > + ret > > + > > +// > > +// Read machine timer compare CSR. > > +// @param a0 : UINT64 > > +// > > +ASM_PFX (RiscVReadMachineTimerCmp): > > + li t1, CLINT_REG_MTIMECMP0 > > + ld a0, (t1) > > + ret > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPla > > tformTimerLib.inf > > b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPla > > tformTimerLib.inf > > new file mode 100644 > > index 00000000..62771b68 > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/Risc > > +++ VPlatformTimerLib.inf > > @@ -0,0 +1,39 @@ > > +## @file > > +# RISC-V CPU lib to override timer mechanism for U500 platform. > > +# > > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > +rights reserved.
# Copyright (c) 2007 - 2010, Intel Corporation. > > +All rights reserved.
# # SPDX-License-Identifier: > > +BSD-2-Clause-Patent # ## > > + > > +[Defines] > > + INF_VERSION =3D 0x00010005 >=20 > Please bump specification version. >=20 > > + BASE_NAME =3D RiscVPlatformTimerLib > > + FILE_GUID =3D AFA75BBD-DE9D-4E77-BD88-1EA401BE= 931D > > + MODULE_TYPE =3D BASE > > + VERSION_STRING =3D 1.0 > > + LIBRARY_CLASS =3D RiscVPlatformTimerLib > > + > > +# > > +# The following information is for reference only and not required by= the > build tools. > > +# > > +# VALID_ARCHITECTURES =3D RISCV32 RISCV64 > > +# > > + > > +[Sources] > > + > > +[Sources.RISCV32] > > + RiscVPlatformTimerLib.s > > + >=20 > Please drop RISCV32 for now. >=20 > > +[Sources.RISCV64] > > + RiscVPlatformTimerLib.s > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + RiscVPkg/RiscVPkg.dec > > + Platform/RiscV/SiFive/U500Pkg/U500.dec >=20 > Please sort alphabetically. >=20 > > + > > + > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf > > b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf > > new file mode 100644 > > index 00000000..85af1fbd > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.in > > +++ f > > @@ -0,0 +1,31 @@ > > +## @file > > +# Library instance for SerialIo library class > > +# > > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > +rights reserved.
# Copyright (c) 2006 - 2014, Intel Corporation. > > +All rights reserved.
# # SPDX-License-Identifier: > > +BSD-2-Clause-Patent # ## > > + > > +[Defines] > > + INF_VERSION =3D 0x00010005 >=20 > Please bump specification version. >=20 > > + BASE_NAME =3D U500SerialPortLib > > + MODULE_UNI_FILE =3D U500SerialPortLib.uni > > + FILE_GUID =3D FCC4FD2B-2FF6-4FFA-B363-7C1111E5= DCE9 > > + MODULE_TYPE =3D BASE > > + VERSION_STRING =3D 1.0 > > + LIBRARY_CLASS =3D SerialPortLib > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + RiscVPkg/RiscVPkg.dec > > + Platform/RiscV/RiscVPlatformPkg.dec >=20 > Please sort alphabetically. >=20 > > + > > +[LibraryClasses] > > + BaseLib > > + IoLib > > + RiscVOpensbiLib > > + > > +[Sources] > > + SerialPortLib.c > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c > > b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c > > new file mode 100644 > > index 00000000..e51bf9c1 > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib. > > +++ c > > @@ -0,0 +1,241 @@ > > +/** @file > > + UART Serial Port library functions > > + > > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All > > + rights reserved.
Copyright (c) 2006 - 2016, Intel Corporation. > > + All rights reserved.
> > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +#define REG32(p, i) ((p)[(i) >> 2]) >=20 > Please use the IoLib functions instead. >=20 > > + > > +//--------------------------------------------- > > +// UART Register Offsets > > +//--------------------------------------------- > > + > > +#define UART_REG_IP 0x14 > > + #define UART_IP_RXWM 0x02 >=20 > Please drop indentation at start of line. >=20 > > + > > +//--------------------------------------------- > > +// UART Settings > > +//--------------------------------------------- > > + > > +#define U500_UART_ADDR 0x54000000 > > +#define U500_UART_BAUDRATE 115200 > > +#define U500_SYS_CLK 100000000 > > + > > +/** > > + Initialize the serial device hardware. > > + > > + If no initialization is required, then return RETURN_SUCCESS. > > + If the serial device was successfuly initialized, then return > RETURN_SUCCESS. > > + If the serial device could not be initialized, then return > RETURN_DEVICE_ERROR. > > + > > + @retval RETURN_SUCCESS The serial device was initialized. > > + @retval RETURN_DEVICE_ERROR The serail device could not be > initialized. > > + > > +**/ > > +RETURN_STATUS > > +EFIAPI > > +SerialPortInitialize ( > > + VOID > > + ) > > +{ > > + if (sifive_uart_init (U500_UART_ADDR, U500_SYS_CLK/2, > U500_UART_BAUDRATE) !=3D 0) { > > + return EFI_DEVICE_ERROR; >=20 > Indentation is only 2 spaces. >=20 > > + } > > + return RETURN_SUCCESS; > > +} > > + > > +/** > > + Write data from buffer to serial device. > > + > > + Writes NumberOfBytes data bytes from Buffer to the serial device. > > + The number of bytes actually written to the serial device is return= ed. > > + If the return value is less than NumberOfBytes, then the write oper= ation > failed. > > + > > + If Buffer is NULL, then ASSERT(). > > + > > + If NumberOfBytes is zero, then return 0. > > + > > + @param Buffer Pointer to the data buffer to be written. > > + @param NumberOfBytes Number of bytes to written to the serial > device. > > + > > + @retval 0 NumberOfBytes is 0. > > + @retval >0 The number of bytes written to the serial = device. > > + If this value is less than NumberOfBytes, = then the write > operation failed. > > + > > +**/ > > +UINTN > > +EFIAPI > > +SerialPortWrite ( > > + IN UINT8 *Buffer, > > + IN UINTN NumberOfBytes > > + ) > > +{ > > + UINTN i; >=20 > I >=20 > > + > > + if (Buffer =3D=3D NULL) { > > + return 0; > > + } > > + > > + for(i=3D0; i < NumberOfBytes; i++) { >=20 > for (I =3D 0; I < NumberOfBytes; I++) { >=20 > > + sifive_uart_putc (Buffer[i]); > > + } > > + > > + return i; > > +} > > + > > + > > +/** > > + Reads data from a serial device into a buffer. > > + > > + @param Buffer Pointer to the data buffer to store the da= ta read > from the serial device. > > + @param NumberOfBytes Number of bytes to read from the serial > device. > > + > > + @retval 0 NumberOfBytes is 0. > > + @retval >0 The number of bytes read from the serial d= evice. > > + If this value is less than NumberOfBytes, = then the read > operation failed. > > + > > +**/ > > +UINTN > > +EFIAPI > > +SerialPortRead ( > > + OUT UINT8 *Buffer, > > + IN UINTN NumberOfBytes > > + ) > > +{ > > + UINTN i; >=20 > I >=20 > > + > > + if (NULL =3D=3D Buffer) { > > + return 0; > > + } > > + > > + for(i=3D0; i < NumberOfBytes; i++) { >=20 > for (I =3D 0; I < NumberOfBytes; I++) { >=20 > > + Buffer[i] =3D (UINT8)sifive_uart_getc (); } > > + > > + return i; > > +} > > + > > +/** > > + Polls a serial device to see if there is any data waiting to be rea= d. > > + > > + Polls aserial device to see if there is any data waiting to be read= . > > + If there is data waiting to be read from the serial device, then TR= UE is > returned. > > + If there is no data waiting to be read from the serial device, then= FALSE is > returned. > > + > > + @retval TRUE Data is waiting to be read from the serial= device. > > + @retval FALSE There is no data waiting to be read from t= he serial > device. > > + > > +**/ > > +BOOLEAN > > +EFIAPI > > +SerialPortPoll ( > > + VOID > > + ) > > +{ > > + static volatile UINT32 * const uart =3D (void *)(U500_UART_ADDR); >=20 > Please use IoLib functions instead. >=20 > > + UINT32 ip; >=20 > IP >=20 > > + > > + ip =3D REG32(uart, UART_REG_IP); > > + if(ip & UART_IP_RXWM) { >=20 > Space before ( >=20 > > + return TRUE; > > + } > > + else { >=20 > } else { >=20 > / > Leif >=20 > > + return FALSE; > > + } > > +} > > + > > +/** > > + Sets the control bits on a serial device. > > + > > + @param Control Sets the bits of Control that are set= table. > > + > > + @retval RETURN_SUCCESS The new control bits were set on the > serial device. > > + @retval RETURN_UNSUPPORTED The serial device does not support > this operation. > > + @retval RETURN_DEVICE_ERROR The serial device is not functioning > correctly. > > + > > +**/ > > +RETURN_STATUS > > +EFIAPI > > +SerialPortSetControl ( > > + IN UINT32 Control > > + ) > > +{ > > + > > + return RETURN_SUCCESS; > > +} > > + > > +/** > > + Retrieve the status of the control bits on a serial device. > > + > > + @param Control A pointer to return the current contr= ol signals > from the serial device. > > + > > + @retval RETURN_SUCCESS The control bits were read from the s= erial > device. > > + @retval RETURN_UNSUPPORTED The serial device does not support > this operation. > > + @retval RETURN_DEVICE_ERROR The serial device is not functioning > correctly. > > + > > +**/ > > +RETURN_STATUS > > +EFIAPI > > +SerialPortGetControl ( > > + OUT UINT32 *Control > > + ) > > +{ > > + *Control =3D 0; > > + return RETURN_SUCCESS; > > +} > > + > > +/** > > + Sets the baud rate, receive FIFO depth, transmit/receice time out, > > +parity, > > + data bits, and stop bits on a serial device. > > + > > + @param BaudRate The requested baud rate. A BaudRate value= of 0 > will use the > > + device's default interface speed. > > + On output, the value actually set. > > + @param ReveiveFifoDepth The requested depth of the FIFO on the > receive side of the > > + serial interface. A ReceiveFifoDepth valu= e of 0 will use > > + the device's default FIFO depth. > > + On output, the value actually set. > > + @param Timeout The requested time out for a single chara= cter in > microseconds. > > + This timeout applies to both the transmit= and receive side of > the > > + interface. A Timeout value of 0 will use = the device's default > time > > + out value. > > + On output, the value actually set. > > + @param Parity The type of parity to use on this serial = device. A > Parity value of > > + DefaultParity will use the device's defau= lt parity value. > > + On output, the value actually set. > > + @param DataBits The number of data bits to use on the ser= ial > device. A DataBits > > + vaule of 0 will use the device's default = data bit setting. > > + On output, the value actually set. > > + @param StopBits The number of stop bits to use on this se= rial > device. A StopBits > > + value of DefaultStopBits will use the dev= ice's default > number of > > + stop bits. > > + On output, the value actually set. > > + > > + @retval RETURN_SUCCESS The new attributes were set on th= e > serial device. > > + @retval RETURN_UNSUPPORTED The serial device does not suppor= t > this operation. > > + @retval RETURN_INVALID_PARAMETER One or more of the attributes > has an unsupported value. > > + @retval RETURN_DEVICE_ERROR The serial device is not function= ing > correctly. > > + > > +**/ > > +RETURN_STATUS > > +EFIAPI > > +SerialPortSetAttributes ( > > + IN OUT UINT64 *BaudRate, > > + IN OUT UINT32 *ReceiveFifoDepth, > > + IN OUT UINT32 *Timeout, > > + IN OUT EFI_PARITY_TYPE *Parity, > > + IN OUT UINT8 *DataBits, > > + IN OUT EFI_STOP_BITS_TYPE *StopBits > > + ) > > +{ > > + return RETURN_SUCCESS; > > +} > > diff --git > > a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib. > > uni > > b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib. > > uni > > new file mode 100644 > > index 00000000..49163bd8 > > --- /dev/null > > +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPort > > +++ Lib.uni > > @@ -0,0 +1,16 @@ > > +// /** @file > > +// Library instance for SerialIo library class // // Library instance > > +for SerialIO library class. > > +// > > +// Copyright (c) 2006 - 2014, Intel Corporation. All rights > > +reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // > > +// **/ > > + > > + > > +#string STR_MODULE_ABSTRACT #language en-US "Library inst= ance > for SerialIO library class" > > + > > +#string STR_MODULE_DESCRIPTION #language en-US "Library > instance for SerialIO library class." > > + > > -- > > 2.12.0.windows.1 > > > > > > > > >=20 >=20