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From: "Abner Chang" <abner.chang@hpe.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
	"Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com>
Cc: Liming Gao <liming.gao@intel.com>,
	Michael D Kinney <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
Date: Tue, 24 Sep 2019 01:54:28 +0000	[thread overview]
Message-ID: <CS1PR8401MB1192E94A77BC09833BAFE745FF840@CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <15C6EB9A049FF8A4.24160@groups.io>


CC Maintainers.
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Monday, September 23, 2019 8:32 AM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29]
> MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
> 
> RISC-V MMIO library instance.  RISC-V only supports memory map I/O.
> 
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
>  .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf      |   8 +-
>  MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c     | 601
> +++++++++++++++++++++
>  2 files changed, 607 insertions(+), 2 deletions(-)  create mode 100644
> MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> 
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> index 457cce9..fbb568e 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> @@ -2,13 +2,14 @@
>  #  Instance of I/O Library using compiler intrinsics.
>  #
>  #  I/O Library that uses compiler intrinsics to perform IN and OUT instructions
> -#  for IA-32 and x64.  On IPF, I/O port requests are translated into MMIO
> requests.
> +#  for IA-32, x64 and RISC-V.  On IPF, I/O port requests are translated into
> MMIO requests.
>  #  MMIO requests are forwarded directly to memory.  For EBC, I/O port
> requests  #  ASSERT().
>  #
>  #  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>  #
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>  #
> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +#  Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development
> +LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -25,7 +26,7 @@
> 
> 
>  #
> -#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64
> +#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64 RISCV64
>  #
> 
>  [Sources]
> @@ -55,6 +56,9 @@
>  [Sources.AARCH64]
>    IoLibArm.c
> 
> +[Sources.RISCV64]
> +  IoLibRiscV.c
> +
>  [Packages]
>    MdePkg/MdePkg.dec
> 
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> new file mode 100644
> index 0000000..789928b
> --- /dev/null
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c
> @@ -0,0 +1,601 @@
> +/** @file
> +  Common I/O Library routines for RISC-V
> +
> +  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
> +
> +  This program and the accompanying materials  are licensed and made
> + available under the terms and conditions of the BSD License  which
> + accompanies this distribution. The full text of the license may be
> + found at
> + INVALID URI REMOVED
> 3A__opensource.org_lic
> + enses_bsd-
> 2Dlicense.php&d=DwIBAg&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4V
> +
> gi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=iiSSnOQeIcsWwWSNpZOq8Z8FU
> hf-ZXBIKZ
> + -k2RKjtSw&s=JXcajsH1FkirFiWOe0VJ0qh1HCibFZd6W9j87D8J98k&e=
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> +**/
> +
> +#include "BaseIoLibIntrinsicInternal.h"
> +
> +/**
> +  Reads an 8-bit MMIO register.
> +
> +  Reads the 8-bit MMIO register specified by Address. The 8-bit read
> + value is  returned. This function must guarantee that all MMIO read
> + and write  operations are serialized.
> +
> +  If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> +  @param  Address The MMIO register to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioRead8 (
> +  IN      UINTN                     Address
> +  )
> +{
> +  return *(volatile UINT8*)Address;
> +}
> +
> +/**
> +  Writes an 8-bit MMIO register.
> +
> +  Writes the 8-bit MMIO register specified by Address with the value
> + specified  by Value and returns Value. This function must guarantee
> + that all MMIO read  and write operations are serialized.
> +
> +  If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> +  @param  Address The MMIO register to write.
> +  @param  Value   The value to write to the MMIO register.
> +
> +  @return Value.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioWrite8 (
> +  IN      UINTN                     Address,
> +  IN      UINT8                     Value
> +  )
> +{
> +  *(volatile UINT8 *)Address = Value;
> +  return Value;
> +}
> +
> +/**
> +  Reads a 16-bit MMIO register.
> +
> +  Reads the 16-bit MMIO register specified by Address. The 16-bit read
> + value is  returned. This function must guarantee that all MMIO read
> + and write  operations are serialized.
> +
> +  If 16-bit MMIO register operations are not supported, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address The MMIO register to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioRead16 (
> +  IN      UINTN                     Address
> +  )
> +{
> +  return *(volatile UINT16 *)Address;
> +}
> +
> +/**
> +  Writes a 16-bit MMIO register.
> +
> +  Writes the 16-bit MMIO register specified by Address with the value
> + specified  by Value and returns Value. This function must guarantee
> + that all MMIO read  and write operations are serialized.
> +
> +  If 16-bit MMIO register operations are not supported, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address The MMIO register to write.
> +  @param  Value   The value to write to the MMIO register.
> +
> +  @return Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioWrite16 (
> +  IN      UINTN                     Address,
> +  IN      UINT16                    Value
> +  )
> +{
> +  *(volatile UINT16 *)Address = Value;
> +  return Value;
> +}
> +
> +/**
> +  Reads a 32-bit MMIO register.
> +
> +  Reads the 32-bit MMIO register specified by Address. The 32-bit read
> + value is  returned. This function must guarantee that all MMIO read
> + and write  operations are serialized.
> +
> +  If 32-bit MMIO register operations are not supported, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address The MMIO register to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioRead32 (
> +  IN      UINTN                     Address
> +  )
> +{
> +  return *(volatile UINT32 *)Address;
> +}
> +
> +/**
> +  Writes a 32-bit MMIO register.
> +
> +  Writes the 32-bit MMIO register specified by Address with the value
> + specified  by Value and returns Value. This function must guarantee
> + that all MMIO read  and write operations are serialized.
> +
> +  If 32-bit MMIO register operations are not supported, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address The MMIO register to write.
> +  @param  Value   The valu  return *(volatile UINT8*)Address;
> +                  to write to the MMIO register.
> +
> +  @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioWrite32 (
> +  IN      UINTN                     Address,
> +  IN      UINT32                    Value
> +  )
> +{
> +  *(volatile UINT32 *)Address = Value;
> +  return Value;
> +}
> +
> +/**
> +  Reads a 64-bit MMIO register.
> +
> +  Reads the 64-bit MMIO register specified by Address. The 64-bit read
> + value is  returned. This function must guarantee that all MMIO read
> + and write  operations are serialized.
> +
> +  If 64-bit MMIO register operations are not supported, then ASSERT().
> +  If Address is not aligned on a 64-bit boundary, then ASSERT().
> +
> +  @param  Address The MMIO register to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioRead64 (
> +  IN      UINTN                     Address
> +  )
> +{
> +  return *(volatile UINT64 *)Address;
> +}
> +
> +/**
> +  Writes a 64-bit MMIO register.
> +
> +  Writes the 64-bit MMIO register specified by Address with the value
> + specified  by Value and returns Value. This function must guarantee
> + that all MMIO read  and write operations are serialized.
> +
> +  If 64-bit MMIO register operations are not supported, then ASSERT().
> +  If Address is not aligned on a 64-bit boundary, then ASSERT().
> +
> +  @param  Address The MMIO register to write.
> +  @param  Value   The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioWrite64 (
> +  IN      UINTN                     Address,
> +  IN      UINT64                    Value
> +  )
> +{
> +  *(volatile UINT64 *)Address = Value;
> +  return Value;
> +}
> +
> +/**
> +  Reads an 8-bit I/O port.
> +
> +  Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 8-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port  The I/O port to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +IoRead8 (
> +  IN      UINTN                     Port
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Writes an 8-bit I/O port.
> +
> +  Writes the 8-bit I/O port specified by Port with the value specified
> + by Value  and returns Value. This function must guarantee that all I/O
> + read and write  operations are serialized.
> +
> +  If 8-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port  The I/O port to write.
> +  @param  Value The value to write to the I/O port.
> +
> +  @return The value written the I/O port.
> +
> +**/
> +
> +UINT8
> +EFIAPI
> +IoWrite8 (
> +  IN      UINTN                     Port,
> +  IN      UINT8                     Value
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Reads a 16-bit I/O port.
> +
> +  Reads the 16-bit I/O port specified by Port. The 16-bit read value is
> returned.
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 16-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port  The I/O port to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoRead16 (
> +  IN      UINTN                     Port
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Writes a 16-bit I/O port.
> +
> +  Writes the 16-bit I/O port specified by Port with the value specified
> + by Value  and returns Value. This function must guarantee that all I/O
> + read and write  operations are serialized.
> +
> +  If 16-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port  The I/O port to write.
> +  @param  Value The value to write to the I/O port.
> +
> +  @return The value written the I/O port.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoWrite16 (
> +  IN      UINTN                     Port,
> +  IN      UINT16                    Value
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Reads a 32-bit I/O port.
> +
> +  Reads the 32-bit I/O port specified by Port. The 32-bit read value is
> returned.
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 32-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port  The I/O port to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoRead32 (
> +  IN      UINTN                     Port
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Writes a 32-bit I/O port.
> +
> +  Writes the 32-bit I/O port specified by Port with the value specified
> + by Value  and returns Value. This function must guarantee that all I/O
> + read and write  operations are serialized.
> +
> +  If 32-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port  The I/O port to write.
> +  @param  Value The value to write to the I/O port.
> +
> +  @return The value written the I/O port.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoWrite32 (
> +  IN      UINTN                     Port,
> +  IN      UINT32                    Value
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Reads a 64-bit I/O port.
> +
> +  Reads the 64-bit I/O port specified by Port. The 64-bit read value is
> returned.
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 64-bit I/O port operations are not supported, then ASSERT().
> +  If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> +  @param  Port  The I/O port to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoRead64 (
> +  IN      UINTN                     Port
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Writes a 64-bit I/O port.
> +
> +  Writes the 64-bit I/O port specified by Port with the value specified
> + by Value  and returns Value. This function must guarantee that all I/O
> + read and write  operations are serialized.
> +
> +  If 64-bit I/O port operations are not supported, then ASSERT().
> +  If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> +  @param  Port  The I/O port to write.
> +  @param  Value The value to write to the I/O port.
> +
> +  @return The value written to the I/O port.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoWrite64 (
> +  IN      UINTN                     Port,
> +  IN      UINT64                    Value
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +  return 0;
> +}
> +
> +/**
> +  Reads an 8-bit I/O port fifo into a block of memory.
> +
> +  Reads the 8-bit I/O fifo port specified by Port.
> +  The port is read Count times, and the read data is  stored in the
> + provided Buffer.
> +
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 8-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port    The I/O port to read.
> +  @param  Count   The number of times to read I/O port.
> +  @param  Buffer  The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo8 (
> +  IN      UINTN                     Port,
> +  IN      UINTN                     Count,
> +  OUT     VOID                      *Buffer
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +}
> +
> +/**
> +  Writes a block of memory into an 8-bit I/O port fifo.
> +
> +  Writes the 8-bit I/O fifo port specified by Port.
> +  The port is written Count times, and the write data is  retrieved
> + from the provided Buffer.
> +
> +  This function must guarantee that all I/O write and write operations
> + are  serialized.
> +
> +  If 8-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port    The I/O port to write.
> +  @param  Count   The number of times to write I/O port.
> +  @param  Buffer  The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo8 (
> +  IN      UINTN                     Port,
> +  IN      UINTN                     Count,
> +  IN      VOID                      *Buffer
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +}
> +
> +/**
> +  Reads a 16-bit I/O port fifo into a block of memory.
> +
> +  Reads the 16-bit I/O fifo port specified by Port.
> +  The port is read Count times, and the read data is  stored in the
> + provided Buffer.
> +
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 16-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port    The I/O port to read.
> +  @param  Count   The number of times to read I/O port.
> +  @param  Buffer  The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo16 (
> +  IN      UINTN                     Port,
> +  IN      UINTN                     Count,
> +  OUT     VOID                      *Buffer
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +}
> +
> +/**
> +  Writes a block of memory into a 16-bit I/O port fifo.
> +
> +  Writes the 16-bit I/O fifo port specified by Port.
> +  The port is written Count times, and the write data is  retrieved
> + from the provided Buffer.
> +
> +  This function must guarantee that all I/O write and write operations
> + are  serialized.
> +
> +  If 16-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port    The I/O port to write.
> +  @param  Count   The number of times to write I/O port.
> +  @param  Buffer  The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo16 (
> +  IN      UINTN                     Port,
> +  IN      UINTN                     Count,
> +  IN      VOID                      *Buffer
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +}
> +
> +/**
> +  Reads a 32-bit I/O port fifo into a block of memory.
> +
> +  Reads the 32-bit I/O fifo port specified by Port.
> +  The port is read Count times, and the read data is  stored in the
> + provided Buffer.
> +
> +  This function must guarantee that all I/O read and write operations
> + are  serialized.
> +
> +  If 32-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port    The I/O port to read.
> +  @param  Count   The number of times to read I/O port.
> +  @param  Buffer  The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo32 (
> +  IN      UINTN                     Port,
> +  IN      UINTN                     Count,
> +  OUT     VOID                      *Buffer
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +}
> +
> +/**
> +  Writes a block of memory into a 32-bit I/O port fifo.
> +
> +  Writes the 32-bit I/O fifo port specified by Port.
> +  The port is written Count times, and the write data is  retrieved
> + from the provided Buffer.
> +
> +  This function must guarantee that all I/O write and write operations
> + are  serialized.
> +
> +  If 32-bit I/O port operations are not supported, then ASSERT().
> +
> +  @param  Port    The I/O port to write.
> +  @param  Count   The number of times to write I/O port.
> +  @param  Buffer  The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo32 (
> +  IN      UINTN                     Port,
> +  IN      UINTN                     Count,
> +  IN      VOID                      *Buffer
> +  )
> +{
> +  DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n",
> +__FUNCTION__));
> +  ASSERT (FALSE);
> +}
> --
> 2.7.4
> 
> 
> 


  parent reply	other threads:[~2019-09-24  1:55 UTC|newest]

Thread overview: 108+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-23  0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
2019-09-26 22:26   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-09-26 22:29   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
2019-09-26 22:41   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2019-09-26 22:44   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
2019-09-26 22:45   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2019-09-26 22:46   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-09-26 22:56   ` [edk2-devel] " Leif Lindholm
2019-10-14 16:47     ` Abner Chang
2019-10-14 18:23       ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-10-01  8:44   ` [edk2-devel] " Philippe Mathieu-Daudé
2019-09-23  0:31 ` Abner Chang
2019-09-26 23:30   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-09-26 23:39   ` [edk2-devel] " Leif Lindholm
2019-10-01  8:49     ` Philippe Mathieu-Daudé
2019-10-01  9:07       ` Leif Lindholm
2019-10-02  1:30         ` Abner Chang
2019-10-02  9:13           ` Leif Lindholm
2019-10-02 16:14             ` Abner Chang
2019-10-02 16:27               ` Andrew Fish
2019-10-02 16:35                 ` Leif Lindholm
2019-10-03  0:52                   ` Abner Chang
2019-10-03  8:38                     ` Leif Lindholm
2019-10-03 11:34                       ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2019-09-26 23:46   ` [edk2-devel] " Leif Lindholm
2019-10-15  4:02     ` Abner Chang
2019-10-15 10:31       ` Leif Lindholm
2019-10-15 10:56         ` Abner Chang
     [not found]     ` <15CDB6324F411B37.30896@groups.io>
2019-10-15  4:26       ` Abner Chang
2019-10-15 10:41         ` Leif Lindholm
2019-10-15 10:59           ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-09-26 23:47   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-09-27  0:19   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
2019-09-30 22:51   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
2019-09-30 22:51   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
2019-09-30 18:31   ` [edk2-devel] " Leif Lindholm
2019-10-15  2:32     ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
2019-09-30 19:15   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
2019-09-30 19:46   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
2019-09-30 20:03   ` [edk2-devel] " Leif Lindholm
2019-10-15  1:21     ` Abner Chang
2019-10-15  8:35       ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
2019-09-30 20:15   ` [edk2-devel] " Leif Lindholm
2019-09-30 20:44     ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2019-09-30 20:31   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
2019-09-30 20:54   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
2019-09-30 20:56   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-09-30 21:11   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-09-26 22:09   ` [edk2-devel] " Leif Lindholm
2019-10-15  6:18     ` Abner Chang
2019-10-15 10:56       ` Leif Lindholm
2019-10-15 11:13         ` Abner Chang
2019-10-16  5:06         ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 20:50   ` [edk2-devel] " Leif Lindholm
2019-10-15  6:31     ` Abner Chang
2019-10-15 11:00       ` Leif Lindholm
2019-10-15 11:03         ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2019-09-30 22:39   ` [edk2-devel] " Leif Lindholm
2019-10-14 11:27     ` Abner Chang
2019-10-14 11:56       ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
2019-09-26 22:24   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
2019-09-30 22:48   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Abner Chang
2019-09-30 22:50   ` [edk2-devel] " Leif Lindholm
     [not found] ` <15C6EB9824DD2A88.29693@groups.io>
2019-09-24  1:52   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
     [not found] ` <15C6EB994C26E5C4.2053@groups.io>
2019-09-24  1:52   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
     [not found] ` <15C6EB9950232DB5.29693@groups.io>
2019-09-24  1:53   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
     [not found] ` <15C6EB9A049FF8A4.24160@groups.io>
2019-09-24  1:54   ` Abner Chang [this message]
     [not found] ` <15C6EB9B3E887BEB.29693@groups.io>
2019-09-24  1:55   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
     [not found] ` <15C6EB9A40C408A0.24160@groups.io>
2019-09-24  1:56   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
     [not found] ` <15C6EB9B872A5B83.24160@groups.io>
2019-09-24  1:57   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
     [not found] ` <15C6EB99CBC780B5.2053@groups.io>
2019-09-24  1:57   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
     [not found] ` <15C6EB9A9BD83853.2053@groups.io>
2019-09-24  1:58   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
     [not found] ` <15C6EB9AEB7BB057.24160@groups.io>
2019-09-24  1:58   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
     [not found] ` <15C6EB99608359A3.24160@groups.io>
2019-09-24  1:59   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
     [not found] ` <15C6EB9D6C0EC3B0.29693@groups.io>
2019-09-24  2:00   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
     [not found] ` <15C6EB98AD6CCCEB.24160@groups.io>
2019-09-24  2:01   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
     [not found] ` <15C6EB9F04387439.29693@groups.io>
2019-09-24  2:02   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 22:22 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Leif Lindholm
2019-10-15  6:39   ` Abner Chang

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