Re: [PATCH v8 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address

["Dong, Eric" <eric.dong@intel.com>]

Hi Wei,

Thanks for your patches.

I have include my review-by for it, and create PR https://github.com/tianocore/edk2/pull/1131 for it.

Thanks,
Eric
-----Original Message-----
From: Sheng, W <w.sheng@intel.com> 
Sent: Wednesday, November 18, 2020 9:20 AM
To: Laszlo Ersek <lersek@redhat.com>; devel@edk2.groups.io; Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>
Cc: Kumar, Rahul1 <rahul1.kumar@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
Subject: RE: [PATCH v8 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address

Hi Eric, Ray,
Could you help to give confirm for merge these patches?
Thank you.
BR
Sheng Wei

> -----Original Message-----
> From: Laszlo Ersek <lersek@redhat.com>
> Sent: 2020年11月18日 4:02
> To: Sheng, W <w.sheng@intel.com>; devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; 
> Kumar,
> Rahul1 <rahul1.kumar@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
> Subject: Re: [PATCH v8 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page 
> table depth with page table address
> 
> On 11/16/20 04:18, Sheng Wei wrote:
> > When trying to get page table base, if mInternalCr3 is zero, it will 
> > use  the page table from CR3, and reflect the page table depth by 
> > CR4 LA57
> bit.
> > If mInternalCr3 is non zero, it will use the page table from
> > mInternalCr3  and reflect the page table depth of mInternalCr3 at same time.
> > In the case of X64, we use m5LevelPagingNeeded to reflect the depth 
> > of the page table. And in the case of IA32, it will not the page 
> > table depth  information.
> >
> > This patch is a bug fix when enable CET feature with 5 level paging.
> > The SMM page tables are allocated / initialized in PiCpuSmmEntry().
> > When CET is enabled, PiCpuSmmEntry() must further modify the 
> > attribute of  shadow stack pages. This page table is not set to CR3 in PiCpuSmmEntry().
> >  So the page table base address is set to mInternalCr3 for modifty 
> > the page table attribute. It could not use CR4 LA57 bit to reflect 
> > the page table depth for mInternalCr3.
> > So we create a architecture-specific implementation GetPageTable() 
> > with
> >  2 output parameters. One parameter is used to output the page table 
> > address. Another parameter is used to reflect if it is 5 level 
> > paging or not.
> >
> > Correct the Cr3 typo
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015
> >
> > Signed-off-by: Sheng Wei <w.sheng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Rahul Kumar <rahul1.kumar@intel.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> >
> > Sheng Wei (2):
> >   UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo
> >   UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table
> >     address
> >
> >  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c           | 26 ++++++++++++-
> >  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h         | 13 ++++---
> >  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 35
> +++++-------------
> >  UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c            | 43
> ++++++++++++++++++----
> >  4 files changed, 77 insertions(+), 40 deletions(-)
> >
> 
> series
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> 
> The 2nd patch needs an ACK from Eric or Ray; then we can merge this series.
> 
> (It is a bugfix so it can go in even during the hard feature freeze. 
> But we should merge it as soon as we can.)
> 
> Thanks,
> Laszlo