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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: Ni, Ray =20 Sent: Tuesday, February 9, 2021 10:17 PM To: devel@edk2.groups.io Cc: Dong, Eric ; Laszlo Ersek ; Kum= ar, Rahul1 Subject: [PATCH v3 3/4] UefiCpuPkg/MpInitLib: Use NASM struc to avoid hardc= ode offset In Windows environment, "dumpbin /disasm" is used to verify the disassembly= before and after using NASM struc doesn't change. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 5 +- UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 43 -------- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 80 +++++++------- UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 103 ++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 5 +- UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 45 -------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 92 ++++++++-------- 7 files changed, 193 insertions(+), 180 deletions(-) delete mode 100644 U= efiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc create mode 100644 UefiCpuPkg/Library/MpInitLib/MpEqu.inc delete mode 100644 UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 1771575c69..860a9750e2 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -1,7 +1,7 @@ ## @file # MP Initialize Library instance for DXE driver. #-# Copyright = (c) 2016 - 2020, Intel Corporation. All rights reserved.
+# Copyright (= c) 2016 - 2021, Intel Corporation. All rights reserved.
# SPDX-License= -Identifier: BSD-2-Clause-Patent # ##@@ -22,14 +22,13 @@ [Defines] # [Sources.IA32]- Ia32/MpEqu.inc Ia32/MpFuncs.nasm [Sources.X64]- X6= 4/MpEqu.inc X64/MpFuncs.nasm [Sources.common]+ MpEqu.inc DxeMpLib.c = MpLib.c MpLib.hdiff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc = b/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc deleted file mode 100644 index 4f5a7c859a..0000000000 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc +++ /dev/null @@ -1,43 +0,0 @@ -;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved= .
-; SPDX-License-Identifier: BSD-2-Clause-Patent-;-; Module Name:-;-; = MpEqu.inc-;-; Abstract:-;-; This is the equates file for Multiple Proces= sor support-;-;------------------------------------------------------------= ---------------------VacantFlag equ 00h-NotVacant= Flag equ 0ffh--CPU_SWITCH_STATE_IDLE equ = 0-CPU_SWITCH_STATE_STORED equ 1-CPU_SWITCH_STATE_LOADED = equ 2--LockLocation equ (SwitchToRealPro= cEnd - RendezvousFunnelProcStart)-StackStartAddressLocation equ = LockLocation + 04h-StackSizeLocation equ LockLocation + = 08h-ApProcedureLocation equ LockLocation + 0Ch-GdtrLocatio= n equ LockLocation + 10h-IdtrLocation = equ LockLocation + 16h-BufferStartLocation equ = LockLocation + 1Ch-ModeOffsetLocation equ LockLocation + = 20h-ApIndexLocation equ LockLocation + 24h-CodeSegment= Location equ LockLocation + 28h-DataSegmentLocation = equ LockLocation + 2Ch-EnableExecuteDisableLocation equ = LockLocation + 30h-Cr3Location equ LockLocation + = 34h-InitFlagLocation equ LockLocation + 38h-CpuInfoLoca= tion equ LockLocation + 3Ch-NumApsExecutingLocation = equ LockLocation + 40h-InitializeFloatingPointUnitsAddress equ = LockLocation + 48h-ModeTransitionMemoryLocation equ LockLocation + = 4Ch-ModeTransitionSegmentLocation equ LockLocation + 50h-ModeHighMem= oryLocation equ LockLocation + 52h-ModeHighSegmentLocation = equ LockLocation + 56h-diff --git a/UefiCpuPkg/Library/MpInitLib= /Ia32/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm index 2eaddc93bc..4363ad9a18 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -39,21 +39,21 @@ BITS 16 mov fs, ax mov gs, ax - mov si, BufferSta= rtLocation+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart) = mov ebx, [si] - mov si, DataSegmentLocation+ mov = si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment) mov edx, [si] = ; ; Get start address of 32-bit code in low memory (<1MB) ;- = mov edi, ModeTransitionMemoryLocation+ mov edi, MP_CPU_EX= CHANGE_INFO_FIELD (ModeTransitionMemory) - mov si, GdtrLocation+ = mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile) o32 lgdt [= cs:si] - mov si, IdtrLocation+ mov si, MP_CPU_EXCHANGE_= INFO_FIELD (IdtrProfile) o32 lidt [cs:si] ;@@ -82,7 +82,7 @@ Fla= t32Start: ; protected mode entry point mov esi, ebx mov edi, esi- add edi, Ena= bleExecuteDisableLocation+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (= EnableExecuteDisable) cmp byte [edi], 0 jz SkipEna= bleExecuteDisable @@ -96,7 +96,7 @@ Flat32Start: = ; protected mode entry point wrmsr mov edi, esi- add edi, Cr3Location+ a= dd edi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3) mov eax, dword= [edi] mov cr3, eax @@ -110,35 +110,35 @@ Flat32Start: = ; protected mode entry point SkipEnableExecuteDisable: mov edi, esi- add edi, Ini= tFlagLocation+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (InitFlag) = cmp dword [edi], 1 ; 1 =3D=3D ApInitConfig jnz Get= ApicId ; Increment the number of APs executing here as early as possib= le ; This is decremented in C code when AP is finished executing mo= v edi, esi- add edi, NumApsExecutingLocation+ add = edi, MP_CPU_EXCHANGE_INFO_FIELD (NumApsExecuting) lock inc dword [e= di] ; AP init mov edi, esi- add edi, LockLocation= + add edi, MP_CPU_EXCHANGE_INFO_FIELD (Lock) mov eax, = NotVacantFlag mov edi, esi- add edi, ApIndexLocation+= add edi, MP_CPU_EXCHANGE_INFO_FIELD (ApIndex) mov ebx= , 1 lock xadd dword [edi], ebx ; EBX =3D ApIndex++ = inc ebx ; EBX is CpuNumber mov = edi, esi- add edi, StackSizeLocation+ add edi, MP_= CPU_EXCHANGE_INFO_FIELD (StackSize) mov eax, [edi] mov = ecx, ebx inc ecx mul ecx = ; EAX =3D StackSize * (CpuNumber + 1) mov edi, esi- add = edi, StackStartAddressLocation+ add edi, MP_CPU_EXCHANGE_IN= FO_FIELD (StackStart) add eax, [edi] mov esp, eax = jmp CProcedureInvoke@@ -171,18 +171,18 @@ GetProcessorNumber: ; Note that BSP may become an AP due to SwitchBsp() ; xor = ebx, ebx- lea eax, [esi + CpuInfoLocation]+ lea e= ax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)] mov edi, [eax]= GetNextProcNumber:- cmp [edi], edx ; API= C ID match?+ cmp dword [edi + CPU_INFO_IN_HOB.InitialApicId], ed= x ; APIC ID match? jz ProgramStack- add edi, 20+ = add edi, CPU_INFO_IN_HOB_size inc ebx jmp = GetNextProcNumber ProgramStack:- mov esp, [edi + 12]+ mov = esp, dword [edi + CPU_INFO_IN_HOB.ApTopOfStack] CProcedureInvoke: = push ebp ; push BIST data at top of AP stack@@ -195,1= 1 +195,11 @@ CProcedureInvoke: push ebx ; Push ApIndex mov eax, esi- = add eax, LockLocation+ add eax, MP_CPU_EXCHANGE_INFO_OF= FSET push eax ; push address of exchange info data = buffer mov edi, esi- add edi, ApProcedureLocation+ = add edi, MP_CPU_EXCHANGE_INFO_FIELD (CFunction) mov eax,= [edi] call eax ; Invoke C function@@ -262,17 +262= ,17 @@ ASM_PFX(AsmGetAddressMap): mov ebp,esp mov ebx, [ebp + 24h]- mov dw= ord [ebx], RendezvousFunnelProcStart- mov dword [ebx + 4h], Flat= 32Start - RendezvousFunnelProcStart- mov dword [ebx + 8h], Rende= zvousFunnelProcEnd - RendezvousFunnelProcStart- mov dword [ebx + = 0Ch], AsmRelocateApLoopStart- mov dword [ebx + 10h], AsmRelocateA= pLoopEnd - AsmRelocateApLoopStart- mov dword [ebx + 14h], Flat32S= tart - RendezvousFunnelProcStart- mov dword [ebx + 18h], SwitchTo= RealProcEnd - SwitchToRealProcStart ; SwitchToRealSize- mov = dword [ebx + 1Ch], SwitchToRealProcStart - RendezvousFunnelProcStart ; Swi= tchToRealOffset- mov dword [ebx + 20h], SwitchToRealProcStart - F= lat32Start ; SwitchToRealNoNxOffset- mov dword [ebx= + 24h], 0 ; SwitchToRealPM= 16ModeOffset- mov dword [ebx + 28h], 0 = ; SwitchToRealPM16ModeSize+ mov dword [ebx = + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddress], RendezvousFunnelProcSta= rt+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], Fl= at32Start - RendezvousFunnelProcStart+ mov dword [ebx + MP_ASSEMB= LY_ADDRESS_MAP.RendezvousFunnelSize], RendezvousFunnelProcEnd - RendezvousF= unnelProcStart+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.Relocate= ApLoopFuncAddress], AsmRelocateApLoopStart+ mov dword [ebx + MP_A= SSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], AsmRelocateApLoopEnd - AsmRelo= cateApLoopStart+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTra= nsitionOffset], Flat32Start - RendezvousFunnelProcStart+ mov dwor= d [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], SwitchToRealProcEnd - S= witchToRealProcStart+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.Sw= itchToRealOffset], SwitchToRealProcStart - RendezvousFunnelProcStart+ mo= v dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], Swit= chToRealProcStart - Flat32Start+ mov dword [ebx + MP_ASSEMBLY_ADD= RESS_MAP.SwitchToRealPM16ModeOffset], 0+ mov dword [ebx + MP_ASSE= MBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], 0 popad ret@@ -302,18 = +302,18 @@ ASM_PFX(AsmExchangeRole): mov eax, cr0 push eax - sgdt [esi + 8]- s= idt [esi + 14]+ sgdt [esi + CPU_EXCHANGE_ROLE_INFO.Gdtr]+ = sidt [esi + CPU_EXCHANGE_ROLE_INFO.Idtr] ; Store the its StackP= ointer- mov [esi + 4],esp+ mov [esi + CPU_EXCHANGE_ROLE= _INFO.StackPointer],esp ; update its switch state to STORED- mov = byte [esi], CPU_SWITCH_STATE_STORED+ mov byte [esi + CPU_EXC= HANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED WaitForOtherStored: ; = wait until the other CPU finish storing its state- cmp byte [edi]= , CPU_SWITCH_STATE_STORED+ cmp byte [edi + CPU_EXCHANGE_ROLE_INFO= .State], CPU_SWITCH_STATE_STORED jz OtherStored pause j= mp WaitForOtherStored@@ -321,21 +321,21 @@ WaitForOtherStored: OtherStored: ; Since another CPU already stored its state, load them = ; load GDTR value- lgdt [edi + 8]+ lgdt [edi + CPU_EXC= HANGE_ROLE_INFO.Gdtr] ; load IDTR value- lidt [edi + 14]+ = lidt [edi + CPU_EXCHANGE_ROLE_INFO.Idtr] ; load its future Stack= Pointer- mov esp, [edi + 4]+ mov esp, [edi + CPU_EXCHAN= GE_ROLE_INFO.StackPointer] ; update the other CPU's switch state to LO= ADED- mov byte [edi], CPU_SWITCH_STATE_LOADED+ mov byte= [edi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED WaitForOthe= rLoaded: ; wait until the other CPU finish loading new state, ; oth= erwise the data in stack may corrupt- cmp byte [esi], CPU_SWITCH_= STATE_LOADED+ cmp byte [esi + CPU_EXCHANGE_ROLE_INFO.State], CPU_= SWITCH_STATE_LOADED jz OtherLoaded pause jmp Wai= tForOtherLoadeddiff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCp= uPkg/Library/MpInitLib/MpEqu.inc new file mode 100644 index 0000000000..46c2b5c116 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -0,0 +1,103 @@ +;-------------------------------------------------------------------------= ----- ;+; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved= .
+; SPDX-License-Identifier: BSD-2-Clause-Patent+;+; Module Name:+;+; = MpEqu.inc+;+; Abstract:+;+; This is the equates file for Multiple Proces= sor support+;+;------------------------------------------------------------= -------------------+%include "Nasm.inc"++VacantFlag equ = 00h+NotVacantFlag equ 0ffh++CPU_SWITCH_STATE_= IDLE equ 0+CPU_SWITCH_STATE_STORED equ 1+CPU_SW= ITCH_STATE_LOADED equ 2++;+; Equivalent NASM structure of MP_A= SSEMBLY_ADDRESS_MAP+;+struc MP_ASSEMBLY_ADDRESS_MAP+ .RendezvousFunnelAddr= ess CTYPE_UINTN 1+ .ModeEntryOffset CTYPE_UINTN 1+ .R= endezvousFunnelSize CTYPE_UINTN 1+ .RelocateApLoopFuncAddress = CTYPE_UINTN 1+ .RelocateApLoopFuncSize CTYPE_UINTN 1+ .ModeTransi= tionOffset CTYPE_UINTN 1+ .SwitchToRealSize CTYPE_UI= NTN 1+ .SwitchToRealOffset CTYPE_UINTN 1+ .SwitchToRealNoNxOff= set CTYPE_UINTN 1+ .SwitchToRealPM16ModeOffset CTYPE_UINTN 1+ .= SwitchToRealPM16ModeSize CTYPE_UINTN 1+endstruc++;+; Equivalent NASM s= tructure of IA32_DESCRIPTOR+;+struc IA32_DESCRIPTOR+ .Limit = CTYPE_UINT16 1+ .Base CTYPE_UINTN 1+en= dstruc++;+; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO+;+struc CPU= _EXCHANGE_ROLE_INFO+ ; State is defined as UINT8 in C header file+ ; Defi= ne it as UINTN here to guarantee the fields that follow State+ ; is natura= lly aligned. The structure layout doesn't change.+ .State = CTYPE_UINTN 1+ .StackPointer CTYPE_UINTN 1+ .Gdt= r CTYPE_UINT8 IA32_DESCRIPTOR_size+ .Idtr = CTYPE_UINT8 IA32_DESCRIPTOR_size+endstruc++;+; Equivalent= NASM structure of CPU_INFO_IN_HOB+;+struc CPU_INFO_IN_HOB+ .InitialApicId= CTYPE_UINT32 1+ .ApicId CTYPE_UINT= 32 1+ .Health CTYPE_UINT32 1+ .ApTopOfStack = CTYPE_UINT64 1+endstruc++;+; Equivalent NASM structure of MP_CPU= _EXCHANGE_INFO+;+struc MP_CPU_EXCHANGE_INFO+ .Lock: = CTYPE_UINTN 1+ .StackStart: CTYPE_UINTN 1+ .StackSize= : CTYPE_UINTN 1+ .CFunction: CTYPE_U= INTN 1+ .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size+ = .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size+ .BufferSt= art: CTYPE_UINTN 1+ .ModeOffset: CTYPE_= UINTN 1+ .ApIndex: CTYPE_UINTN 1+ .CodeSegment: = CTYPE_UINTN 1+ .DataSegment: CTYPE_UINTN 1+ = .EnableExecuteDisable: CTYPE_UINTN 1+ .Cr3: = CTYPE_UINTN 1+ .InitFlag: CTYPE_UINTN 1+ .CpuInfo= : CTYPE_UINTN 1+ .NumApsExecuting: CTYPE= _UINTN 1+ .CpuMpData: CTYPE_UINTN 1+ .InitializeFloati= ngPointUnits: CTYPE_UINTN 1+ .ModeTransitionMemory: CTYPE_UINT32 1= + .ModeTransitionSegment: CTYPE_UINT16 1+ .ModeHighMemory: = CTYPE_UINT32 1+ .ModeHighSegment: CTYPE_UINT16 1+ .En= able5LevelPaging: CTYPE_BOOLEAN 1+ .SevEsIsEnabled: = CTYPE_BOOLEAN 1+ .GhcbBase: CTYPE_UINTN 1+endstruc++= MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelProc= Start)+%define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFS= ET + MP_CPU_EXCHANGE_INFO. %+ Field)diff --git a/UefiCpuPkg/Library/MpInitL= ib/PeiMpInitLib.inf b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf index 34abf25d43..49b0ffe8be 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -1,7 +1,7 @@ ## @file # MP Initialize Library instance for PEI driver. #-# Copyright = (c) 2016 - 2020, Intel Corporation. All rights reserved.
+# Copyright (= c) 2016 - 2021, Intel Corporation. All rights reserved.
# SPDX-License= -Identifier: BSD-2-Clause-Patent # ##@@ -22,14 +22,13 @@ [Defines] # [Sources.IA32]- Ia32/MpEqu.inc Ia32/MpFuncs.nasm [Sources.X64]- X6= 4/MpEqu.inc X64/MpFuncs.nasm [Sources.common]+ MpEqu.inc PeiMpLib.c = MpLib.c MpLib.hdiff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b= /UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc deleted file mode 100644 index c92daaaffd..0000000000 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ /dev/null @@ -1,45 +0,0 @@ -;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved= .
-; SPDX-License-Identifier: BSD-2-Clause-Patent-;-; Module Name:-;-; = MpEqu.inc-;-; Abstract:-;-; This is the equates file for Multiple Proces= sor support-;-;------------------------------------------------------------= ---------------------VacantFlag equ 00h-NotVacant= Flag equ 0ffh--CPU_SWITCH_STATE_IDLE equ = 0-CPU_SWITCH_STATE_STORED equ 1-CPU_SWITCH_STATE_LOADED = equ 2--LockLocation equ (SwitchToRealPro= cEnd - RendezvousFunnelProcStart)-StackStartAddressLocation equ = LockLocation + 08h-StackSizeLocation equ LockLocation + = 10h-ApProcedureLocation equ LockLocation + 18h-GdtrLocatio= n equ LockLocation + 20h-IdtrLocation = equ LockLocation + 2Ah-BufferStartLocation equ = LockLocation + 34h-ModeOffsetLocation equ LockLocation + = 3Ch-ApIndexLocation equ LockLocation + 44h-CodeSegment= Location equ LockLocation + 4Ch-DataSegmentLocation = equ LockLocation + 54h-EnableExecuteDisableLocation equ = LockLocation + 5Ch-Cr3Location equ LockLocation + = 64h-InitFlagLocation equ LockLocation + 6Ch-CpuInfoLoca= tion equ LockLocation + 74h-NumApsExecutingLocation = equ LockLocation + 7Ch-InitializeFloatingPointUnitsAddress equ = LockLocation + 8Ch-ModeTransitionMemoryLocation equ LockLocation + = 94h-ModeTransitionSegmentLocation equ LockLocation + 98h-ModeHighMem= oryLocation equ LockLocation + 9Ah-ModeHighSegmentLocation = equ LockLocation + 9Eh-Enable5LevelPagingLocation equ = LockLocation + 0A0h-SevEsIsEnabledLocation equ LockLocation += 0A1h-GhcbBaseLocation equ LockLocation + 0A2hdiff --gi= t a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpIn= itLib/X64/MpFuncs.nasm index 5b588f2dcb..db297f5cca 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -43,21 +43,21 @@ BITS 16 mov fs, ax mov gs, ax - mov si, BufferSta= rtLocation+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart) = mov ebx, [si] - mov si, DataSegmentLocation+ mov = si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment) mov edx, [si] = ; ; Get start address of 32-bit code in low memory (<1MB) ;- = mov edi, ModeTransitionMemoryLocation+ mov edi, MP_CPU_EX= CHANGE_INFO_FIELD (ModeTransitionMemory) - mov si, GdtrLocation+ = mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile) o32 lgdt [= cs:si] - mov si, IdtrLocation+ mov si, MP_CPU_EXCHANGE_= INFO_FIELD (IdtrProfile) o32 lidt [cs:si] ;@@ -85,7 +85,7 @@ Fla= t32Start: ; protected mode entry point ; ; Enable execute disable bit ;- mov esi, EnableExe= cuteDisableLocation+ mov esi, MP_CPU_EXCHANGE_INFO_FIELD (EnableE= xecuteDisable) cmp byte [ebx + esi], 0 jz SkipEnable= ExecuteDisableBit @@ -101,7 +101,7 @@ SkipEnableExecuteDisableBit: mov eax, cr4 bts eax, 5 - mov esi, Enable5= LevelPagingLocation+ mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Enable5= LevelPaging) cmp byte [ebx + esi], 0 jz SkipEnable5L= evelPaging @@ -117,7 +117,7 @@ SkipEnable5LevelPaging: ; ; Load page table ;- mov esi, Cr3Location = ; Save CR3 in ecx+ mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3) = ; Save CR3 in ecx mov ecx, [ebx + esi] mov = cr3, ecx ; Load CR3 @@ -139,47 +139,47 @@ SkipEnable5L= evelPaging: ; ; Far jump to 64-bit code ;- mov edi, ModeHighMemo= ryLocation+ mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeHighMemory) = add edi, ebx jmp far [edi] BITS 64 LongModeStart: mo= v esi, ebx- lea edi, [esi + InitFlagLocation]+ lea = edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)] cmp qword = [edi], 1 ; ApInitConfig jnz GetApicId ; Increment the= number of APs executing here as early as possible ; This is decremente= d in C code when AP is finished executing mov edi, esi- add = edi, NumApsExecutingLocation+ add edi, MP_CPU_EXCHANGE_INFO= _FIELD (NumApsExecuting) lock inc dword [edi] ; AP init mov = edi, esi- add edi, LockLocation+ add edi, MP_CPU= _EXCHANGE_INFO_FIELD (Lock) mov rax, NotVacantFlag mov = edi, esi- add edi, ApIndexLocation+ add edi, MP_CPU_= EXCHANGE_INFO_FIELD (ApIndex) mov ebx, 1 lock xadd dword [e= di], ebx ; EBX =3D ApIndex++ inc ebx = ; EBX is CpuNumber ; program stack mov ed= i, esi- add edi, StackSizeLocation+ add edi, MP_CPU_EXC= HANGE_INFO_FIELD (StackSize) mov eax, dword [edi] mov = ecx, ebx inc ecx mul ecx = ; EAX =3D StackSize * (CpuNumber + 1) mov edi, esi- add = edi, StackStartAddressLocation+ add edi, MP_CPU_EXCHANGE_INF= O_FIELD (StackStart) add rax, qword [edi] mov rsp, ra= x - lea edi, [esi + SevEsIsEnabledLocation]+ lea edi, [= esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)] cmp byte [edi= ], 1 ; SevEsIsEnabled jne CProcedureInvoke @@ -193,7 +193= ,7 @@ LongModeStart: mov ecx, ebx mul ecx ;= EAX =3D SIZE_4K * 2 * CpuNumber mov edi, esi- add edi= , GhcbBaseLocation+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (GhcbBase= ) add rax, qword [edi] mov rdx, rax shr rd= x, 32@@ -202,7 +202,7 @@ LongModeStart: jmp CProcedureInvoke GetApicId:- lea edi, [esi + Sev= EsIsEnabledLocation]+ lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD = (SevEsIsEnabled)] cmp byte [edi], 1 ; SevEsIsEnabled = jne DoCpuid @@ -296,18 +296,18 @@ GetProcessorNumber: ; Note that BSP may become an AP due to SwitchBsp() ; xor = ebx, ebx- lea eax, [esi + CpuInfoLocation]+ lea e= ax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)] mov rdi, [eax]= GetNextProcNumber:- cmp dword [rdi], edx = ; APIC ID match?+ cmp dword [rdi + CPU_INFO_IN_HOB.InitialApicId= ], edx ; APIC ID match? jz ProgramStack- = add rdi, 20+ add rdi, CPU_INFO_IN_HOB_size inc = ebx jmp GetNextProcNumber ProgramStack:- mov = rsp, qword [rdi + 12]+ mov rsp, qword [rdi + CPU_INFO_IN_HOB.ApT= opOfStack] CProcedureInvoke: push rbp ; Push BIST = data at top of AP stack@@ -315,17 +315,17 @@ CProcedureInvoke: push rbp mov rbp, rsp - mov rax, qword [esi= + InitializeFloatingPointUnitsAddress]+ mov rax, qword [esi + MP= _CPU_EXCHANGE_INFO_FIELD (InitializeFloatingPointUnits)] sub rsp= , 20h call rax ; Call assembly function to initiali= ze FPU per UEFI spec add rsp, 20h mov edx, ebx = ; edx is ApIndex mov ecx, esi- add ecx, LockLocati= on ; rcx is address of exchange info data buffer+ add ecx, MP_CPU= _EXCHANGE_INFO_OFFSET ; rcx is address of exchange info data buffer mo= v edi, esi- add edi, ApProcedureLocation+ add ed= i, MP_CPU_EXCHANGE_INFO_FIELD (CFunction) mov rax, qword [edi] = sub rsp, 20h@@ -661,18 +661,18 @@ AsmRelocateApLoopEnd: global ASM_PFX(AsmGetAddressMap) ASM_PFX(AsmGetAddressMap): lea = rax, [ASM_PFX(RendezvousFunnelProc)]- mov qword [rcx], rax- m= ov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart- = mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelPro= cStart+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnel= Address], rax+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntry= Offset], LongModeStart - RendezvousFunnelProcStart+ mov qword [rc= x + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize], RendezvousFunnelProcEnd = - RendezvousFunnelProcStart lea rax, [ASM_PFX(AsmRelocateApLoop)= ]- mov qword [rcx + 18h], rax- mov qword [rcx + 20h], A= smRelocateApLoopEnd - AsmRelocateApLoopStart- mov qword [rcx + 28= h], Flat32Start - RendezvousFunnelProcStart- mov qword [rcx + 30h= ], SwitchToRealProcEnd - SwitchToRealProcStart ; SwitchToRealSize-= mov qword [rcx + 38h], SwitchToRealProcStart - RendezvousFunnelP= rocStart ; SwitchToRealOffset- mov qword [rcx + 40h], SwitchTo= RealProcStart - Flat32Start ; SwitchToRealNoNxOffset- m= ov qword [rcx + 48h], PM16Mode - RendezvousFunnelProcStart = ; SwitchToRealPM16ModeOffset- mov qword [rcx + 50h], Switc= hToRealProcEnd - PM16Mode ; SwitchToRealPM16ModeSize+= mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddre= ss], rax+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoop= FuncSize], AsmRelocateApLoopEnd - AsmRelocateApLoopStart+ mov qwo= rd [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - Rend= ezvousFunnelProcStart+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.S= witchToRealSize], SwitchToRealProcEnd - SwitchToRealProcStart+ mov = qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], SwitchToRealPro= cStart - RendezvousFunnelProcStart+ mov qword [rcx + MP_ASSEMBLY_= ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start+ = mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffse= t], PM16Mode - RendezvousFunnelProcStart+ mov qword [rcx + MP_ASS= EMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], SwitchToRealProcEnd - PM16Mode= ret ;----------------------------------------------------------------= ---------------------@@ -715,18 +715,18 @@ ASM_PFX(AsmExchangeRole): ;Store EFLAGS, GDTR and IDTR regiter to stack pushfq- sgdt = [rsi + 16]- sidt [rsi + 26]+ sgdt [rsi + CPU_EXCHANGE_= ROLE_INFO.Gdtr]+ sidt [rsi + CPU_EXCHANGE_ROLE_INFO.Idtr] ; S= tore the its StackPointer- mov [rsi + 8], rsp+ mov [rsi= + CPU_EXCHANGE_ROLE_INFO.StackPointer], rsp ; update its switch state= to STORED- mov byte [rsi], CPU_SWITCH_STATE_STORED+ mov = byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED WaitF= orOtherStored: ; wait until the other CPU finish storing its state- = cmp byte [rdi], CPU_SWITCH_STATE_STORED+ cmp byte [rdi + C= PU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED jz OtherS= tored pause jmp WaitForOtherStored@@ -734,21 +734,21 @@ Wait= ForOtherStored: OtherStored: ; Since another CPU already stored its state, load them = ; load GDTR value- lgdt [rdi + 16]+ lgdt [rdi + CPU_EX= CHANGE_ROLE_INFO.Gdtr] ; load IDTR value- lidt [rdi + 26]+ = lidt [rdi + CPU_EXCHANGE_ROLE_INFO.Idtr] ; load its future Stac= kPointer- mov rsp, [rdi + 8]+ mov rsp, [rdi + CPU_EXCHA= NGE_ROLE_INFO.StackPointer] ; update the other CPU's switch state to L= OADED- mov byte [rdi], CPU_SWITCH_STATE_LOADED+ mov byt= e [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED WaitForOth= erLoaded: ; wait until the other CPU finish loading new state, ; ot= herwise the data in stack may corrupt- cmp byte [rsi], CPU_SWITCH= _STATE_LOADED+ cmp byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU= _SWITCH_STATE_LOADED jz OtherLoaded pause jmp Wa= itForOtherLoaded--=20 2.27.0.windows.1