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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: Ni, Ray =20 Sent: Wednesday, May 12, 2021 12:53 PM To: devel@edk2.groups.io Cc: Dong, Eric ; Laszlo Ersek ; Kum= ar, Rahul1 Subject: [PATCH] UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limit= ation 5-level paging can be enabled on CPU which supports up to 52 physical address size. But when the feature was enabled, the 48 address size limit was not removed and the 5-level paging testing didn't access address >=3D 2^48. So the issue wasn't detected until recently an address >=3D 2^48 is accessed. Change-Id: Iaedc73be318d4b4122071efc3ba6e967a4b58fc3 Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index fd6583f9d1..89143810b6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1887,11 +1887,13 @@ InitializeMpServiceData ( IN UINTN ShadowStackSize ) { - UINT32 Cr3; - UINTN Index; - UINT8 *GdtTssTables; - UINTN GdtTableStepSize; - CPUID_VERSION_INFO_EDX RegEdx; + UINT32 Cr3; + UINTN Index; + UINT8 *GdtTssTables; + UINTN GdtTableStepSize; + CPUID_VERSION_INFO_EDX RegEdx; + UINT32 MaxExtendedFunction; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; =20 // // Determine if this CPU supports machine check @@ -1918,9 +1920,17 @@ InitializeMpServiceData ( // Initialize physical address mask // NOTE: Physical memory above virtual address limit is not supported !!= ! // - AsmCpuid (0x80000008, (UINT32*)&Index, NULL, NULL, NULL); - gPhyMask =3D LShiftU64 (1, (UINT8)Index) - 1; - gPhyMask &=3D (1ull << 48) - EFI_PAGE_SIZE; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L); + if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL); + } else { + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; + } + gPhyMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) = - 1; + // + // Clear the low 12 bits + // + gPhyMask &=3D 0xfffffffffffff000ULL; =20 // // Create page tables --=20 2.31.1.windows.1