Hi Sheng W

Just a reminder, please make sure your update can work on pure EDKII platform both IA32 and X64.

 

I recommend you validate the OVMF with SMM both IA32 and X64 to ensure there is no impact to the existing platform.

 

Thank you

Yao Jiewen

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Ni, Ray
Sent: Tuesday, October 27, 2020 5:44 PM
To: Sheng, W <w.sheng@intel.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Adjust level paging type for Internal CR3

 

No. You cannot extern a variable defined only for x64. You may meet build failure in IA32 build.

 

From: Sheng, W <w.sheng@intel.com>
Sent: Tuesday, October 27, 2020 3:54 PM
To: devel@edk2.groups.io; Ni, Ray <ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Adjust level paging type for Internal CR3

 

Hi Ray,

Thank you for the review.

  1. Can you please separate the patch to two patches? One is to correct the Cr3 typo, the other is to fix the bug.

Sure. I will update the patch.

  1. Can you please add comments in Is5LevelPageTableBase() to explain why directly checking CR4 doesn't work sometimes? And when (For example, when the function is called from entrypoint and the CR3/CR4 haven't been written)?

Sure. I will update the patch.

  1. "When mInternalCr3 is used, get paging level type by a variable which is set when mInternalCr3 is generated." This commit message isn't so meaningful. It just translates the C logic to plain text. Better to explain the case when the functions called from entrypoint the page table is set to mInternalCr3, gSmmFeatureEnable5LevelPaging reflects the page table type pointed by mInternalCr3.

Sure. I will update the commit message.

  1. I cannot find below variable. Did you miss some code change in the patch? // // Variables from Protected Mode SMI Entry Template // extern BOOLEAN gSmmFeatureEnable5LevelPaging;

gSmmFeatureEnable5LevelPaging is in platform smiEntry.nasm.

Yes, It is not a good variable here.

Do you think it is better to use extern “BOOLEAN                             m5LevelPagingNeeded;” in file Edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c ?

Thank you.

BR

Sheng Wei

 

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Ni, Ray
Sent: 2020年10月27日 9:27
To: Sheng, W <w.sheng@intel.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Adjust level paging type for Internal CR3

 

The overall logic looks good to me and I agree to add an internal function like the patch.

Some minor comments:

  1. Can you please separate the patch to two patches? One is to correct the Cr3 typo, the other is to fix the bug.
  2. Can you please add comments in Is5LevelPageTableBase() to explain why directly checking CR4 doesn't work sometimes? And when (For example, when the function is called from entrypoint and the CR3/CR4 haven't been written)?
  3. "When mInternalCr3 is used, get paging level type by a variable which is set when mInternalCr3 is generated." This commit message isn't so meaningful. It just translates the C logic to plain text. Better to explain the case when the functions called from entrypoint the page table is set to mInternalCr3, gSmmFeatureEnable5LevelPaging reflects the page table type pointed by mInternalCr3.
  4. I cannot find below variable. Did you miss some code change in the patch? // // Variables from Protected Mode SMI Entry Template // extern BOOLEAN gSmmFeatureEnable5LevelPaging;