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Hi Ray,

Could you help to merge the patch of support 5 level= paging iommu to edk2platform branch?

Do you need more check ?

Thank you.

BR

Sheng Wei

 

From: Sheng, W
Sent: 2020= =C4=EA12=D4= =C24=C8=D5 11:44
To: Huang, Jenny <jenny.huang@intel.com>; Yao, Jiewen <jiew= en.yao@intel.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <ranga= sai.v.chaganty@intel.com>; Feng, Roger <roger.feng@intel.com>
Subject: RE: [PATCH v5] IntelSiliconPkg/VTd: Add iommu 5 level pagin= g support

 

Hi Jenny,

Thank you for the review.

I add your name under " Reviewed-by " t= o the patch.

 

@Yao, Jiewen

Do you have more comments about this patch?<= /o:p>

Thank you.

BR

Sheng Wei

 

> ----= -Original Message-----

> From= : Huang, Jenny <jenny.huang@int= el.com>

> Sent= : 2020=C4=EA12=D4= =C24=C8=D5 11:33

> To: = Sheng, W <w.sheng@intel.com>= ; Yao, Jiewen <jiewen.yao@intel.= com>;

> devel@edk2.groups.io

> Cc: = Ni, Ray <ray.ni@intel.com>; C= haganty, Rangasai V

> <= rangasai.v.chaganty@intel.= com>; Feng, Roger <roger.= feng@intel.com>

> Subj= ect: RE: [PATCH v5] IntelSiliconPkg/VTd: Add iommu 5 level paging support

>

> Reviewed-by: Jenny Huang < jenny.huang@intel.com= >

>

> -----Original Message-----

> From: Sheng, W <w.sheng@i= ntel.com>

> Sent: Tuesday, December 1, 2020 7:03 PM=

> To: Yao, Jiewen <jiewe= n.yao@intel.com>; devel@edk2.groups.io

> Cc: Ni, Ray <ray.ni@intel.= com>; Chaganty, Rangasai V

> <rangasai.v.c= haganty@intel.com>; Huang, Jenny <jenn= y.huang@intel.com>;

> Feng, Roger <roger.fen= g@intel.com>

> Subject: [PATCH v5] IntelSiliconPkg/VTd: Add= iommu 5 level paging support

>

> Hi Jiewen,

> About the patch of support 5 level paging io= mmu.

> Thank you for giving the review comments.

> I have done all the update.

> Could you give "review by" on this= patch ?

> Thank you.

> BR

> Sheng Wei

>

>

> > -----Original Message-----

> > From: Sheng, W

> > Sent: 2020=C4=EA11=D4=C224=C8=D5 13:44

> > To: Yao, Jiewen <= jiewen.yao@intel.com>; devel@edk2.groups.io

> > Cc: Ni, Ray <ray.ni@i= ntel.com>; Chaganty, Rangasai V

> > <rangasa= i.v.chaganty@intel.com>; Huang, Jenny <jenny.huang@intel.com>

> > Subject: RE: [PATCH v4] IntelSiliconPkg= /VTd: Add iommu 5 level paging

> > support

> >

> > Hi Jiewen, All,

> > Thank you for the review. I just check = and update the patch.

> > https://edk2.groups.i= o/g/devel/message/67865?p=3D,,,20,0,0,0::relevance,

> > ,posteri

> > d%3A2558558,20,2,0,78471874<= /p>

> > Could we continue the patch review ?

> > BR

> > Sheng Wei

> >

> > > -----Original Message-----

> > > From: Yao, Jiewen <jiewen.yao@intel.com>

> > > Sent: 2020=C4=EA11=D4=C223=C8=D5 16:44

> > > To: Sheng, W <w= .sheng@intel.com>; devel@edk2.groups.io

> > > Cc: Ni, Ray <ray= .ni@intel.com>; Chaganty, Rangasai V

> > > <ra= ngasai.v.chaganty@intel.com>; Huang, Jenny

> > > <jenny.huan= g@intel.com>

> > > Subject: RE: [PATCH v4] IntelSilic= onPkg/VTd: Add iommu 5 level

> > > paging support

> > >

> > > Thanks.

> > >

> > > I only reviewed the policy part. C= omment below:

> > >

> > > 1) I recommend you can merge below= 2 if into one - if

> > > ((mAcpiDmarTable-

> > > >HostAddressWidth <=3D 48) &= amp;&

> > > (mVtdUnitInformation[VtdIndex].Cap= Reg.Bits.SAGAW & BIT2) !=3D 0)) {

> > > You can use 2 lines, but there is = no need to use 2 if.

> > >

> > > +      if= (mAcpiDmarTable->HostAddressWidth <=3D 48) {

> > > +     &nb= sp;  if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) = !=3D 0)

> {

> > > +     &nb= sp;    mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D FALS= E;

> > > +     &nb= sp;  }

> > > +      }<= o:p>

> > >

> > > 2) I think below code has typo.

> > > The DEBUG message about 4-level an= d 5-level should be reversed.

> > > Also we should use DEBUG_INFO inst= ead of DEBUG_ERROR.

> > >

> > > +    if (mVtdUnitIn= formation[VtdIndex].Is5LevelPaging) {

> > > +      Co= ntextEntry->Bits.AddressWidth =3D 0x3;

> > > +      DE= BUG((DEBUG_ERROR, "Using 4-level page-table on VTD %d\n",

> > > VtdIndex));

> > > +    } else {<= /o:p>

> > > +      Co= ntextEntry->Bits.AddressWidth =3D 0x2;

> > > +      DE= BUG((DEBUG_ERROR, "Using 5-level page-table on VTD %d\n",

> > > VtdIndex));

> > > +    }

> > >

> > >

> > >

> > >

> > > > -----Original Message-----

> > > > From: Sheng, W <w.sheng@intel.com>

> > > > Sent: Monday, November 23, 20= 20 4:04 PM

> > > > To: devel@= edk2.groups.io

> > > > Cc: Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V

> > > > <rangasai.v.chaganty@intel.com>; Yao, Jiewen

> > > > <jiewen= .yao@intel.com>; Huang, Jenny <jenny.h= uang@intel.com>

> > > > Subject: [PATCH v4] IntelSili= conPkg/VTd: Add iommu 5 level paging

> > > > support

> > > >

> > > > Support iommu 5 level paging = for translation table.

> > > >

> > > > REF: https://bugzilla.tian= ocore.org/show_bug.cgi?id=3D3067

> > > >

> > > > Signed-off-by: Sheng Wei <= w.sheng@intel.com>

> > > > Cc: Ray Ni <ray.ni@intel.com>

> > > > Cc: Rangasai V Chaganty <<= a href=3D"mailto:rangasai.v.chaganty@intel.com">rangasai.v.chaganty@intel.com>

> > > > Cc: Jiewen Yao <jiewen.yao@intel.com>

> > > > Cc: Jenny Huang <jenny.huang@intel.com>

> > > > ---

> > > >  .../Feature/VTd/IntelVT= dDxe/DmaProtection.c        |  = ; 4 +-

> > > >  .../Feature/VTd/IntelVT= dDxe/DmaProtection.h        |  19 += -

> > > >  .../Feature/VTd/IntelVT= dDxe/TranslationTable.c     | 281

> > +++++++++++++++--

> > > > ----

> > > >  .../Feature/VTd/IntelVT= dDxe/TranslationTableEx.c   |  31 ++-

> > > >  .../Feature/VTd/IntelVT= dDxe/VtdReg.c          &n= bsp;    |  10 +-

> > > >  5 files changed, 245 in= sertions(+), 100 deletions(-)

> > > >

> > > > diff --git

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > c

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > c

> > > > index 9b6135ef..628565ee 1006= 44

> > > > ---

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > c

> > > > +++

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > c

> > > > @@ -523,10 +523,10 @@ SetupVt= d (

> > > >    for (Index = =3D 0; Index < mVtdUnitNumber; Index++) {

> > > >     = DEBUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index,<= /o:p>

> > > > mVtdUnitInformation[Index].Se= gment));

> > > >     = if (mVtdUnitInformation[Index].ExtRootEntryTable !=3D NULL) {

> > > > -    &nbs= p; DumpDmarExtContextEntryTable

> > > > (mVtdUnitInformation[Index].E= xtRootEntryTable);

> > > > +    &nbs= p; DumpDmarExtContextEntryTable

> > > > (mVtdUnitInformation[Index].E= xtRootEntryTable,

> > > > mVtdUnitInformation[Index].Is= 5LevelPaging);

> > > >     = }

> > > >     = if (mVtdUnitInformation[Index].RootEntryTable !=3D NULL) {

> > > > -    &nbs= p; DumpDmarContextEntryTable

> > > > (mVtdUnitInformation[Index].R= ootEntryTable);

> > > > +    &nbs= p; DumpDmarContextEntryTable

> > > > (mVtdUnitInformation[Index].R= ootEntryTable,

> > > > mVtdUnitInformation[Index].Is= 5LevelPaging);

> > > >     = }

> > > >    }

> > > >

> > > > diff --git

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > h

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > h

> > > > index a3331db8..f641cea0 1006= 44

> > > > ---

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > h

> > > > +++

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/DmaProtection.

> > > > h

> > > > @@ -77,6 +77,7 @@ typedef str= uct {

> > > >    BOOLEAN&nbs= p;            &= nbsp;            Has= DirtyContext;

> > > >    BOOLEAN&nbs= p;            &= nbsp;            Has= DirtyPages;

> > > >    PCI_DEVICE_= INFORMATION           Pci= DeviceInfo;

> > > > +  BOOLEAN  &n= bsp;            = ;           Is5LevelPagin= g;

> > > >  } VTD_UNIT_INFORMATION;=

> > > >

> > > >  //

> > > > @@ -375,31 +376,37 @@ ParseDm= arAcpiTableRmrr (

> > > >  /**

> > > >    Dump DMAR c= ontext entry table.

> > > >

> > > > -  @param[in]  Root= Entry DMAR root entry.

> > > > +  @param[in]  Root= Entry       DMAR root entry.

> > > > +  @param[in]  Is5L= evelPaging  If it is the 5 level paging.

> > > >  **/

> > > >  VOID

> > > >  DumpDmarContextEntryTab= le (

> > > > -  IN VTD_ROOT_ENTRY *Ro= otEntry

> > > > +  IN VTD_ROOT_ENTRY *Ro= otEntry,

> > > > +  IN BOOLEAN Is5LevelPa= ging

> > > >    );

> > > >

> > > >  /**

> > > >    Dump DMAR e= xtended context entry table.

> > > >

> > > > -  @param[in]  ExtR= ootEntry DMAR extended root entry.

> > > > +  @param[in]  ExtR= ootEntry    DMAR extended root entry.

> > > > +  @param[in]  Is5L= evelPaging  If it is the 5 level paging.

> > > >  **/

> > > >  VOID

> > > >  DumpDmarExtContextEntry= Table (

> > > > -  IN VTD_EXT_ROOT_ENTRY= *ExtRootEntry

> > > > +  IN VTD_EXT_ROOT_ENTRY= *ExtRootEntry,  IN BOOLEAN Is5LevelPaging

> > > >    );

> > > >

> > > >  /**

> > > >    Dump DMAR s= econd level paging entry.

> > > >

> > > > -  @param[in]  Seco= ndLevelPagingEntry The second level paging entry.

> > > > +  @param[in]  Seco= ndLevelPagingEntry  The second level paging entry.

> > > > +  @param[in]  Is5L= evelPaging          If it is t= he 5 level paging.

> > > >  **/

> > > >  VOID

> > > >  DumpSecondLevelPagingEn= try (

> > > > -  IN VOID *SecondLevelP= agingEntry

> > > > +  IN VOID *SecondLevelP= agingEntry,  IN BOOLEAN Is5LevelPaging

> > > >    );

> > > >

> > > >  /**

> > > > diff --git

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/Translatio

> > > > nT

> > > > ab

> > > > le.c

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/Translatio

> > > > nT

> > > > ab

> > > > le.c

> > > > index 201d663d..6c786b40 1006= 44

> > > > ---

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/Translatio

> > > > nT

> > > > ab

> > > > le.c

> > > > +++

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/Translatio

> > > > nT ab le.c @@ -128,11 +128,26= @@ CreateContextEntry (

> > > >

> > > >      = ;DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n",

> > > > mVtdUnitInformation[VtdIndex]= .Segment, SourceId.Bits.Bus,

> > > > SourceId.Bits.Device, SourceI= d.Bits.Function));

> > > >

> > > > -    if ((mVtd= UnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)

> {

> > > > -    &nbs= p; DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on

> > > > VTD %d !!!!\n", VtdIndex= ));

> > > > +    mVtdUnitI= nformation[VtdIndex].Is5LevelPaging =3D FALSE;

> > > > +    if ((mVtd= UnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT3) !=3D 0)<= /p>

> {

> > > > +    &nbs= p; mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D TRUE;

> > > > +    &nbs= p; if (mAcpiDmarTable->HostAddressWidth <=3D 48) {

> > > > +    &nbs= p;   if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW &

> > > > + BIT2) !=3D 0)

> > {

> > > > +    &nbs= p;     mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D= FALSE;

> > > > +    &nbs= p;   }

> > > > +    &nbs= p; }

> > > > +    } else if= ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW &

> > > > + BIT2) =3D=3D

> > > > 0) {

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported

> > > > + on

> > > > VTD %d !!!!\n", VtdIndex= ));

> > > >     =    return EFI_UNSUPPORTED;

> > > >     = }

> > > > -    ContextEn= try->Bits.AddressWidth =3D 0x2;

> > > > +

> > > > +    if (mVtdU= nitInformation[VtdIndex].Is5LevelPaging) {

> > > > +    &nbs= p; ContextEntry->Bits.AddressWidth =3D 0x3;

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "Using 4-level page-table on VTD %d\n",

> > > > VtdIndex));

> > > > +    } else {<= o:p>

> > > > +    &nbs= p; ContextEntry->Bits.AddressWidth =3D 0x2;

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "Using 5-level page-table on VTD %d\n",

> > > > VtdIndex));

> > > > +    }

> > > >    }

> > > >

> > > >    FlushPageTa= bleMemory (VtdIndex,

> > > > (UINTN)mVtdUnitInformation[Vt= dIndex].RootEntryTable,

> > > > EFI_PAGES_TO_SIZE(EntryTableP= ages));

> > > > @@ -148,6 +163,7 @@ CreateCon= textEntry (

> > > >    @param[in]&= nbsp; MemoryBase          = ;        The base of the memory.

> > > >    @param[in]&= nbsp; MemoryLimit         &nbs= p;       The limit of the memory.<= /p>

> > > >    @param[in]&= nbsp; IoMmuAccess         &nbs= p;       The IOMMU access.

> > > > +  @param[in]  Is5L= evelPaging           = ;   If it is the 5 level paging.

> > > >

> > > >    @return The= second level paging entry.

> > > >  **/

> > > > @@ -157,16 +173,23 @@ CreateS= econdLevelPagingEntryTable (

> > > >    IN VTD_SECO= ND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,

> > > >    IN UINT64&n= bsp;            = ;           MemoryBase,

> > > >    IN UINT64&n= bsp;            = ;           MemoryLimit,<= o:p>

> > > > -  IN UINT64  =             &nb= sp;         IoMmuAccess<= /p>

> > > > +  IN UINT64  =              &n= bsp;        IoMmuAccess,=

> > > > +  IN BOOLEAN  = ;            &n= bsp;        Is5LevelPaging

> > > >    )

> > > >  {

> > > > +  UINTN  &nbs= p;            &= nbsp;          Index5;

> > > >    UINTN =             &nb= sp;            Index= 4;

> > > >    UINTN =             &nb= sp;            Index= 3;

> > > >    UINTN =             &nb= sp;            Index= 2;

> > > > +  UINTN  &nbs= p;            &= nbsp;          Lvl5Start;=

> > > > +  UINTN  &nbs= p;            &= nbsp;          Lvl5End;

> > > > +  UINTN  &nbs= p;            &= nbsp;          Lvl4PagesStart;=

> > > > +  UINTN  &nbs= p;            &= nbsp;          Lvl4PagesEnd;

> > > >    UINTN =             &nb= sp;            Lvl4S= tart;

> > > >    UINTN =             &nb= sp;            Lvl4E= nd;

> > > >    UINTN =             &nb= sp;            Lvl3S= tart;

> > > >    UINTN =             &nb= sp;            Lvl3E= nd;

> > > > +  VTD_SECOND_LEVEL_PAGI= NG_ENTRY  *Lvl5PtEntry;

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY  *Lvl4PtEntry;

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY  *Lvl3PtEntry;

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY  *Lvl2PtEntry; @@ -184,7 +207,7

> > > @@

> > > > CreateSecondLevelPagingEntryT= able (

> > > >    if (SecondL= evelPagingEntry =3D=3D NULL) {

> > > >     = SecondLevelPagingEntry =3D AllocateZeroPages (1);

> > > >     = if (SecondLevelPagingEntry =3D=3D NULL) {

> > > > -    &nbs= p; DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n"));

> > > > +     &nb= sp;DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 or LVL5 PT.

> > > > + \n"));

> > > >     =    return NULL;

> > > >     = }

> > > >     = FlushPageTableMemory (VtdIndex,

> > > > (UINTN)SecondLevelPagingEntry= , EFI_PAGES_TO_SIZE(1)); @@ -197,66

> > > > +220,109 @@ CreateSecondLevel= PagingEntryTable (

> > > >     = return SecondLevelPagingEntry;

> > > >    }

> > > >

> > > > -  Lvl4Start =3D RShiftU= 64 (BaseAddress, 39) & 0x1FF;

> > > > -  Lvl4End =3D RShiftU64= (EndAddress - 1, 39) & 0x1FF;

> > > > +  if (Is5LevelPaging) {=

> > > > +    Lvl5Start= =3D RShiftU64 (BaseAddress, 48) & 0x1FF;

> > > > +    Lvl5End = =3D RShiftU64 (EndAddress - 1, 48) & 0x1FF;

> > > > +    DEBUG ((D= EBUG_INFO,"  Lvl5Start - 0x%x, Lvl5End - 0x%x\n",=

> > > > + Lvl5Start,

> > > > Lvl5End));

> > > >

> > > > -  DEBUG ((DEBUG_INFO,&q= uot;  Lvl4Start - 0x%x, Lvl4End - 0x%x\n",

> > > > Lvl4Start, Lvl4End));

> > > > +    Lvl4Start= =3D RShiftU64 (BaseAddress, 39) & 0x1FF;

> > > > +    Lvl4End = =3D RShiftU64 (EndAddress - 1, 39) & 0x1FF;

> > > >

> > > > -  Lvl4PtEntry =3D (VTD_= SECOND_LEVEL_PAGING_ENTRY

> > > > *)SecondLevelPagingEntry;

> > > > -  for (Index4 =3D Lvl4S= tart; Index4 <=3D Lvl4End; Index4++) {

> > > > -    if (Lvl4P= tEntry[Index4].Uint64 =3D=3D 0) {

> > > > -    &nbs= p; Lvl4PtEntry[Index4].Uint64 =3D (UINT64)(UINTN)AllocateZeroPages (1);

> > > > -    &nbs= p; if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) {

> > > > -    &nbs= p;   DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 PAGE FAIL

> > > > (0x%x)!!!!!!\n", Index4)= );

> > > > -    &nbs= p;   ASSERT(FALSE);

> > > > -    &nbs= p;   return NULL;

> > > > -    &nbs= p; }

> > > > -    &nbs= p; FlushPageTableMemory (VtdIndex,

> (UINTN)Lvl4PtEntry[Index4].Uint64,

> > > > SIZE_4KB);

> > > > -    &nbs= p; SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4],=

> > > > EDKII_IOMMU_ACCESS_READ | EDK= II_IOMMU_ACCESS_WRITE);

> > > > -    }

> > > > +    Lvl4Pages= Start =3D (Lvl5Start<<9) | Lvl4Start;

> > > > +    Lvl4Pages= End =3D (Lvl5End<<9) | Lvl4End;

> > > > +    DEBUG ((D= EBUG_INFO,"  Lvl4PagesStart - 0x%x, Lvl4PagesEnd -

> > > > + 0x%x\n",

> > > > Lvl4PagesStart, Lvl4PagesEnd)= );

> > > >

> > > > -    Lvl3Start= =3D RShiftU64 (BaseAddress, 30) & 0x1FF;

> > > > -    if (ALIGN= _VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <=3D

> > > > EndAddress) {

> > > > -    &nbs= p; Lvl3End =3D SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) - 1;

> > > > -    } else {<= o:p>

> > > > -    &nbs= p; Lvl3End =3D RShiftU64 (EndAddress - 1, 30) & 0x1FF;

> > > > +    Lvl5PtEnt= ry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)SecondLevelPagingEntry;

> > > > +  } else {

> > > > +    Lvl5Start= =3D RShiftU64 (BaseAddress, 48) & 0x1FF;

> > > > +    Lvl5End = =3D Lvl5Start;

> > > > +

> > > > +    Lvl4Start= =3D RShiftU64 (BaseAddress, 39) & 0x1FF;

> > > > +    Lvl4End = =3D RShiftU64 (EndAddress - 1, 39) & 0x1FF;

> > > > +    DEBUG ((D= EBUG_INFO,"  Lvl4Start - 0x%x, Lvl4End - 0x%x\n",=

> > > > + Lvl4Start,

> > > > Lvl4End));

> > > > +

> > > > +    Lvl4PtEnt= ry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)SecondLevelPagingEntry;

> > > > +  }

> > > > +

> > > > +  for (Index5 =3D Lvl5S= tart; Index5 <=3D Lvl5End; Index5++) {

> > > > +    if (Is5Le= velPaging) {

> > > > +    &nbs= p; if (Lvl5PtEntry[Index5].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;   Lvl5PtEntry[Index5].Uint64 =3D (UINT64)(UINTN)AllocateZeroPa= ges (1);

> > > > +    &nbs= p;   if (Lvl5PtEntry[Index5].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;     DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 P= AGE FAIL

> > > > (0x%x)!!!!!!\n", Index5)= );

> > > > +    &nbs= p;     ASSERT(FALSE);

> > > > +    &nbs= p;     return NULL;

> > > > +    &nbs= p;   }

> > > > +    &nbs= p;   FlushPageTableMemory (VtdIndex,

> > > > + (UINTN)Lvl5PtEntry[Index5].= Uint64,

> > > > SIZE_4KB);

> > > > +    &nbs= p;   SetSecondLevelPagingEntryAttribute (&Lvl5PtEntry[Index5]= ,

> > > > EDKII_IOMMU_ACCESS_READ | EDK= II_IOMMU_ACCESS_WRITE);

> > > > +    &nbs= p; }

> > > > +    &nbs= p; Lvl4Start =3D Lvl4PagesStart & 0x1FF;

> > > > +    &nbs= p; if (((Index5+1)<<9) > Lvl4PagesEnd) {

> > > > +    &nbs= p;   Lvl4End =3D SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) -=

> 1;;

> > > > +    &nbs= p;   Lvl4PagesStart =3D (Index5+1)<<9;

> > > > +    &nbs= p; } else {

> > > > +     &nb= sp;  Lvl4End =3D Lvl4PagesEnd & 0x1FF;

> > > > +    &nbs= p; }

> > > > +    &nbs= p; DEBUG ((DEBUG_INFO,"  Lvl5(0x%x): Lvl4Start - 0x%x, Lvl4End

> > > > + - 0x%x\n",<= /p>

> > > > Index5, Lvl4Start, Lvl4End));=

> > > > +    &nbs= p; Lvl4PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl5PtEntry[Index5].Bits.AddressLo,

> > > > Lvl5PtEntry[Index5].Bits.Addr= essHi);

> > > >     = }

> > > > -    DEBUG ((D= EBUG_INFO,"  Lvl4(0x%x): Lvl3Start - 0x%x, Lvl3End -

> 0x%x\n",

> > > > Index4, Lvl3Start, Lvl3End));=

> > > >

> > > > -    Lvl3PtEnt= ry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl4PtEntry[Index4].Bits.AddressLo,

> > > > Lvl4PtEntry[Index4].Bits.Addr= essHi);

> > > > -    for (Inde= x3 =3D Lvl3Start; Index3 <=3D Lvl3End; Index3++) {

> > > > -    &nbs= p; if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) {

> > > > -    &nbs= p;   Lvl3PtEntry[Index3].Uint64 =3D (UINT64)(UINTN)AllocateZeroPa= ges (1);

> > > > -    &nbs= p;   if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) {

> > > > -    &nbs= p;     DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL3 P= AGE FAIL (0x%x,

> > > > 0x%x)!!!!!!\n", Index4, = Index3));

> > > > +    for (Inde= x4 =3D Lvl4Start; Index4 <=3D Lvl4End; Index4++) {

> > > > +    &nbs= p; if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;   Lvl4PtEntry[Index4].Uint64 =3D (UINT64)(UINTN)AllocateZeroPa= ges (1);

> > > > +    &nbs= p;   if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;     DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 P= AGE FAIL

> > > > (0x%x)!!!!!!\n", Index4)= );

> > > >     =        ASSERT(FALSE);

> > > >     =        return NULL;

> > > >     =      }

> > > > -    &nbs= p;   FlushPageTableMemory (VtdIndex,

> (UINTN)Lvl3PtEntry[Index3].Uint64,

> > > > SIZE_4KB);

> > > > -    &nbs= p;   SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3]= ,

> > > > EDKII_IOMMU_ACCESS_READ | EDK= II_IOMMU_ACCESS_WRITE);

> > > > +    &nbs= p;   FlushPageTableMemory (VtdIndex,

> > > > + (UINTN)Lvl4PtEntry[Index4].= Uint64,

> > > > SIZE_4KB);

> > > > +    &nbs= p;   SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4]= ,

> > > > EDKII_IOMMU_ACCESS_READ | EDK= II_IOMMU_ACCESS_WRITE);

> > > > +    &nbs= p; }

> > > > +

> > > > +    &nbs= p; Lvl3Start =3D RShiftU64 (BaseAddress, 30) & 0x1FF;

> > > > +    &nbs= p; if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <=3D=

> > > > EndAddress) {

> > > > +    &nbs= p;   Lvl3End =3D SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) -=

> 1;

> > > > +    &nbs= p; } else {

> > > > +    &nbs= p;   Lvl3End =3D RShiftU64 (EndAddress - 1, 30) & 0x1FF;=

> > > >     =    }

> > > > +    &nbs= p; DEBUG ((DEBUG_INFO,"  Lvl4(0x%x): Lvl3Start - 0x%x, Lvl3End

> > > > + - 0x%x\n",<= /p>

> > > > Index4, Lvl3Start, Lvl3End));=

> > > >

> > > > -    &nbs= p; Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl3PtEntry[Index3].Bits.AddressLo,

> > > > Lvl3PtEntry[Index3].Bits.Addr= essHi);

> > > > -    &nbs= p; for (Index2 =3D 0; Index2 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index2++) {

> > > > -    &nbs= p;   Lvl2PtEntry[Index2].Uint64 =3D BaseAddress;

> > > > -    &nbs= p;   SetSecondLevelPagingEntryAttribute (&Lvl2PtEntry[Index2]= ,

> > > > IoMmuAccess);

> > > > -    &nbs= p;   Lvl2PtEntry[Index2].Bits.PageSize =3D 1;

> > > > -    &nbs= p;   BaseAddress +=3D SIZE_2MB;

> > > > +    &nbs= p; Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl4PtEntry[Index4].Bits.AddressLo,

> > > > Lvl4PtEntry[Index4].Bits.Addr= essHi);

> > > > +    &nbs= p; for (Index3 =3D Lvl3Start; Index3 <=3D Lvl3End; Index3++) {

> > > > +    &nbs= p;   if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;     Lvl3PtEntry[Index3].Uint64 =3D (UINT64)(UINTN)Al= locateZeroPages

> (1);

> > > > +    &nbs= p;     if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) {<= /o:p>

> > > > +    &nbs= p;       DEBUG ((DEBUG_ERROR,"!!!!!! ALL= OCATE LVL3 PAGE FAIL

> > > > + (0x%x,

> > > > 0x%x)!!!!!!\n", Index4, = Index3));

> > > > +    &nbs= p;       ASSERT(FALSE);

> > > > +    &nbs= p;       return NULL;

> > > > +    &nbs= p;     }

> > > > +    &nbs= p;     FlushPageTableMemory (VtdIndex,

> > > > + (UINTN)Lvl3PtEntry[Index3].= Uint64,

> > > > SIZE_4KB);

> > > > +    &nbs= p;     SetSecondLevelPagingEntryAttribute

> > > > + (&Lvl3PtEntry[Index3],<= o:p>

> > > > EDKII_IOMMU_ACCESS_READ | EDK= II_IOMMU_ACCESS_WRITE);

> > > > +    &nbs= p;   }

> > > > +

> > > > +    &nbs= p;   Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl3PtEntry[Index3].Bits.AddressLo,

> > > > Lvl3PtEntry[Index3].Bits.Addr= essHi);

> > > > +    &nbs= p;   for (Index2 =3D 0; Index2 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index2++) {

> > > > +    &nbs= p;     Lvl2PtEntry[Index2].Uint64 =3D BaseAddress;=

> > > > +    &nbs= p;     SetSecondLevelPagingEntryAttribute

> > > > + (&Lvl2PtEntry[Index2],<= o:p>

> > > > IoMmuAccess);

> > > > +    &nbs= p;     Lvl2PtEntry[Index2].Bits.PageSize =3D 1;

> > > > +    &nbs= p;     BaseAddress +=3D SIZE_2MB;

> > > > +    &nbs= p;     if (BaseAddress >=3D MemoryLimit) {

> > > > +     &nb= sp;      break;

> > > > +    &nbs= p;     }

> > > > +    &nbs= p;   }

> > > > +    &nbs= p;   FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry,

> > > > + SIZE_4KB);

> > > >     =      if (BaseAddress >=3D MemoryLimit) {<= /p>

> > > >     =        break;

> > > >     =      }

> > > >     =    }

> > > > -    &nbs= p; FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB);

> > > > +    &nbs= p; FlushPageTableMemory (VtdIndex,

> > > > + (UINTN)&Lvl3PtEntry[Lvl= 3Start],

> > > > (UINTN)&Lvl3PtEntry[Lvl3E= nd + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]);

> > > >     =    if (BaseAddress >=3D MemoryLimit) {

> > > >     =      break;

> > > >     =    }

> > > >     = }

> > > > -    FlushPage= TableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start],

> > > > (UINTN)&Lvl3PtEntry[Lvl3E= nd + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]);

> > > > -    if (BaseA= ddress >=3D MemoryLimit) {

> > > > -    &nbs= p; break;

> > > > -    }

> > > > +    FlushPage= TableMemory (VtdIndex,

> > > > + (UINTN)&Lvl4PtEntry[Lvl= 4Start],

> > > > (UINTN)&Lvl4PtEntry[Lvl4E= nd + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]);

> > > >    }

> > > > -  FlushPageTableMemory = (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start],

> > > > (UINTN)&Lvl4PtEntry[Lvl4E= nd + 1] -

> > > > (UINTN)&Lvl4PtEntry[Lvl4S= tart]);

> > > > +  FlushPageTableMemory = (VtdIndex, (UINTN)&Lvl5PtEntry[Lvl5Start],

> > > > (UINTN)&Lvl5PtEntry[Lvl5E= nd + 1] -

> > > > (UINTN)&Lvl5PtEntry[Lvl5S= tart]);

> > > >

> > > >    return Seco= ndLevelPagingEntry;

> > > >  }

> > > > @@ -266,26 +332,28 @@ CreateS= econdLevelPagingEntryTable (

> > > >

> > > >    @param[in]&= nbsp; VtdIndex          &= nbsp;         The index of the VTd = engine.

> > > >    @param[in]&= nbsp; IoMmuAccess         &nbs= p;       The IOMMU access.

> > > > +  @param[in]  Is5L= evelPaging           = ;   If it is the 5 level paging.

> > > >

> > > >    @return The= second level paging entry.

> > > >  **/

> > > >  VTD_SECOND_LEVEL_PAGING= _ENTRY *

> > > >  CreateSecondLevelPaging= Entry (

> > > >    IN UINTN&nb= sp;  VtdIndex,

> > > > -  IN UINT64  IoMmu= Access

> > > > +  IN UINT64  IoMmu= Access,

> > > > +  IN BOOLEAN Is5LevelPa= ging

> > > >    )

> > > >  {

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY *SecondLevelPagingEntry;

> > > >

> > > >    SecondLevel= PagingEntry =3D NULL;

> > > > -  SecondLevelPagingEntr= y =3D CreateSecondLevelPagingEntryTable

> > > > (VtdIndex, SecondLevelPagingE= ntry, 0, mBelow4GMemoryLimit,

> > > > IoMmuAccess);

> > > > +  SecondLevelPagingEntr= y =3D CreateSecondLevelPagingEntryTable

> > > > + (VtdIndex,

> > > > SecondLevelPagingEntry, 0, mB= elow4GMemoryLimit, IoMmuAccess,

> > > > Is5LevelPaging);

> > > >    if (SecondL= evelPagingEntry =3D=3D NULL) {

> > > >     = return NULL;

> > > >    }

> > > >

> > > >    if (mAbove4= GMemoryLimit !=3D 0) {

> > > >     = ASSERT (mAbove4GMemoryLimit > BASE_4GB);

> > > > -    SecondLev= elPagingEntry =3D CreateSecondLevelPagingEntryTable

> > (VtdIndex,

> > > > SecondLevelPagingEntry, SIZE_= 4GB, mAbove4GMemoryLimit,

> > IoMmuAccess);

> > > > +    SecondLev= elPagingEntry =3D CreateSecondLevelPagingEntryTable

> > > > + (VtdIndex,

> > > > SecondLevelPagingEntry, SIZE_= 4GB, mAbove4GMemoryLimit,

> > > > IoMmuAccess, Is5LevelPaging);=

> > > >     = if (SecondLevelPagingEntry =3D=3D NULL) {

> > > >     =    return NULL;

> > > >     = }

> > > > @@ -326,11 +394,13 @@ SetupTr= anslationTable (

> > > >  /**

> > > >    Dump DMAR c= ontext entry table.

> > > >

> > > > -  @param[in]  Root= Entry DMAR root entry.

> > > > +  @param[in]  Root= Entry       DMAR root entry.

> > > > +  @param[in]  Is5L= evelPaging  If it is the 5 level paging.

> > > >  **/

> > > >  VOID

> > > >  DumpDmarContextEntryTab= le (

> > > > -  IN VTD_ROOT_ENTRY *Ro= otEntry

> > > > +  IN VTD_ROOT_ENTRY *Ro= otEntry,

> > > > +  IN BOOLEAN Is5LevelPa= ging

> > > >    )

> > > >  {

> > > >    UINTN =             &nb= sp;   Index;

> > > > @@ -359,7 +429,7 @@ DumpDmarC= ontextEntryTable (

> > > >     =    if (ContextEntry[Index2].Bits.Present =3D=3D 0) {

> > > >     =      continue;

> > > >     =    }

> > > > -    &nbs= p; DumpSecondLevelPagingEntry ((VOID

> > > > *)(UINTN)VTD_64BITS_ADDRESS(C= ontextEntry[Index2].Bits.SecondLevelP

> > > > ag

> > > > e

> > > > TranslationPointerLo,

> > > > ContextEntry[Index2].Bits.Sec= ondLevelPageTranslationPointerHi));

> > > > +    &nbs= p; DumpSecondLevelPagingEntry ((VOID

> > > > *)(UINTN)VTD_64BITS_ADDRESS(C= ontextEntry[Index2].Bits.SecondLevelP

> > > > ag

> > > > e

> > > > TranslationPointerLo,

> > > > ContextEntry[Index2].Bits.Sec= ondLevelPageTranslationPointerHi),

> > > > Is5LevelPaging);

> > > >     = }

> > > >    }

> > > >    DEBUG ((DEB= UG_INFO,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"));

> > > > @@ -368,17 +438,22 @@ DumpDma= rContextEntryTable (

> > > >  /**

> > > >    Dump DMAR s= econd level paging entry.

> > > >

> > > > -  @param[in]  Seco= ndLevelPagingEntry The second level paging entry.

> > > > +  @param[in]  Seco= ndLevelPagingEntry  The second level paging entry.

> > > > +  @param[in]  Is5L= evelPaging          If it is t= he 5 level paging.

> > > >  **/

> > > >  VOID

> > > >  DumpSecondLevelPagingEn= try (

> > > > -  IN VOID *SecondLevelP= agingEntry

> > > > +  IN VOID *SecondLevelP= agingEntry,  IN BOOLEAN Is5LevelPaging

> > > >    )

> > > >  {

> > > > +  UINTN  &nbs= p;            &= nbsp;          Index5;

> > > >    UINTN =             &nb= sp;            Index= 4;

> > > >    UINTN =             &nb= sp;            Index= 3;

> > > >    UINTN =             &nb= sp;            Index= 2;

> > > >    UINTN =             &nb= sp;            Index= 1;

> > > > +  UINTN   &nb= sp;            =           Lvl5IndexEnd;

> > > > +  VTD_SECOND_LEVEL_PAGI= NG_ENTRY  *Lvl5PtEntry;

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY  *Lvl4PtEntry;

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY  *Lvl3PtEntry;

> > > >    VTD_SECOND_= LEVEL_PAGING_ENTRY  *Lvl2PtEntry; @@ -386,38

> +461,53

> > > @@

> > > > DumpSecondLevelPagingEntry (<= o:p>

> > > >

> > > >    DEBUG ((DEB= UG_VERBOSE,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"))= ;

> > > >    DEBUG ((DEB= UG_VERBOSE,"DMAR Second Level Page Table:\n"));

> > > > +  DEBUG ((DEBUG_VERBOSE= ,"SecondLevelPagingEntry Base - 0x%x,

> > > > Is5LevelPaging - %d\n", = SecondLevelPagingEntry, Is5LevelPaging));

> > > >

> > > > -  DEBUG ((DEBUG_VERBOSE= ,"SecondLevelPagingEntry Base - 0x%x\n",

> > > > SecondLevelPagingEntry));

> > > > +  Lvl5IndexEnd =3D Is5L= evelPaging ?

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY) : 1;

> > > >    Lvl4PtEntry= =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)SecondLevelPagingEntry;

> > > > -  for (Index4 =3D 0; In= dex4 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index4++) {

> > > > -    if (Lvl4P= tEntry[Index4].Uint64 !=3D 0) {

> > > > -    &nbs= p; DEBUG ((DEBUG_VERBOSE,"  Lvl4Pt Entry(0x%03x) - 0x%016lx\n&quo= t;,

> > Index4,

> > > > Lvl4PtEntry[Index4].Uint64));=

> > > > -    }

> > > > -    if (Lvl4P= tEntry[Index4].Uint64 =3D=3D 0) {

> > > > -    &nbs= p; continue;

> > > > -    }

> > > > -    Lvl3PtEnt= ry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl4PtEntry[Index4].Bits.AddressLo,

> > > > Lvl4PtEntry[Index4].Bits.Addr= essHi);

> > > > -    for (Inde= x3 =3D 0; Index3 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index3++) {

> > > > -    &nbs= p; if (Lvl3PtEntry[Index3].Uint64 !=3D 0) {

> > > > -    &nbs= p;   DEBUG ((DEBUG_VERBOSE,"    Lvl3Pt Entry(= 0x%03x) - 0x%016lx\n",

> > > > Index3, Lvl3PtEntry[Index3].U= int64));

> > > > +  Lvl5PtEntry =3D (VTD_= SECOND_LEVEL_PAGING_ENTRY

> > > > *)SecondLevelPagingEntry;

> > > > +

> > > > +  for (Index5 =3D 0; In= dex5 < Lvl5IndexEnd; Index5++) {

> > > > +    if (Is5Le= velPaging) {

> > > > +    &nbs= p; if (Lvl5PtEntry[Index5].Uint64 !=3D 0) {

> > > > +    &nbs= p;   DEBUG ((DEBUG_VERBOSE,"  Lvl5Pt Entry(0x%03x) -

> > > > + 0x%016lx\n",

> > > > Index5, Lvl5PtEntry[Index5].U= int64));

> > > >     =    }

> > > > -    &nbs= p; if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) {

> > > > +    &nbs= p; if (Lvl5PtEntry[Index5].Uint64 =3D=3D 0) {

> > > >     =      continue;

> > > >     =    }

> > > > +    &nbs= p; Lvl4PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl5PtEntry[Index5].Bits.AddressLo,

> > > > Lvl5PtEntry[Index5].Bits.Addr= essHi);

> > > > +    }

> > > >

> > > > -    &nbs= p; Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl3PtEntry[Index3].Bits.AddressLo,

> > > > Lvl3PtEntry[Index3].Bits.Addr= essHi);

> > > > -    &nbs= p; for (Index2 =3D 0; Index2 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index2++) {

> > > > -    &nbs= p;   if (Lvl2PtEntry[Index2].Uint64 !=3D 0) {

> > > > -    &nbs= p;     DEBUG ((DEBUG_VERBOSE,"   &n= bsp;  Lvl2Pt Entry(0x%03x) -

> 0x%016lx\n",

> > > > Index2, Lvl2PtEntry[Index2].U= int64));

> > > > +    for (Inde= x4 =3D 0; Index4 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index4++) {

> > > > +    &nbs= p; if (Lvl4PtEntry[Index4].Uint64 !=3D 0) {

> > > > +    &nbs= p;   DEBUG ((DEBUG_VERBOSE,"  Lvl4Pt Entry(0x%03x) -

> > > > + 0x%016lx\n",

> > > > Index4, Lvl4PtEntry[Index4].U= int64));

> > > > +    &nbs= p; }

> > > > +    &nbs= p; if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;   continue;

> > > > +    &nbs= p; }

> > > > +    &nbs= p; Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl4PtEntry[Index4].Bits.AddressLo,

> > > > Lvl4PtEntry[Index4].Bits.Addr= essHi);

> > > > +    &nbs= p; for (Index3 =3D 0; Index3 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index3++) {

> > > > +    &nbs= p;   if (Lvl3PtEntry[Index3].Uint64 !=3D 0) {

> > > > +    &nbs= p;     DEBUG ((DEBUG_VERBOSE,"   Lvl3Pt = Entry(0x%03x) - 0x%016lx\n",

> > > > Index3, Lvl3PtEntry[Index3].U= int64));

> > > >     =      }

> > > > -    &nbs= p;   if (Lvl2PtEntry[Index2].Uint64 =3D=3D 0) {

> > > > +    &nbs= p;   if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) {

> > > >      = ;      continue;

> > > >     =      }

> > > > -    &nbs= p;   if (Lvl2PtEntry[Index2].Bits.PageSize =3D=3D 0) {=

> > > > -    &nbs= p;     Lvl1PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl2PtEntry[Index2].Bits.AddressLo,

> > > > Lvl2PtEntry[Index2].Bits.Addr= essHi);

> > > > -    &nbs= p;     for (Index1 =3D 0; Index1 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index1++) {

> > > > -    &nbs= p;       if (Lvl1PtEntry[Index1].Uint64 !=3D = 0) {

> > > > -    &nbs= p;         DEBUG ((DEBUG_VERBOSE,&q= uot;        Lvl1Pt Entry(0x%03x) -<= /o:p>

> > > 0x%016lx\n",

> > > > Index1, Lvl1PtEntry[Index1].U= int64));

> > > > +

> > > > +    &nbs= p;   Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl3PtEntry[Index3].Bits.AddressLo,

> > > > Lvl3PtEntry[Index3].Bits.Addr= essHi);

> > > > +     &nb= sp;  for (Index2 =3D 0; Index2 <

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index2++) {

> > > > +    &nbs= p;     if (Lvl2PtEntry[Index2].Uint64 !=3D 0) {

> > > > +    &nbs= p;       DEBUG ((DEBUG_VERBOSE," &n= bsp;  Lvl2Pt Entry(0x%03x) -

> 0x%016lx\n",

> > > > Index2, Lvl2PtEntry[Index2].U= int64));

> > > > +    &nbs= p;     }

> > > > +    &nbs= p;     if (Lvl2PtEntry[Index2].Uint64 =3D=3D 0) {<= /o:p>

> > > > +    &nbs= p;       continue;

> > > > +    &nbs= p;     }

> > > > +    &nbs= p;     if (Lvl2PtEntry[Index2].Bits.PageSize =3D=3D 0) = {

> > > > +    &nbs= p;       Lvl1PtEntry =3D (VTD_SECOND_LEVEL_PA= GING_ENTRY

> > > > *)(UINTN)VTD_64BITS_ADDRESS(L= vl2PtEntry[Index2].Bits.AddressLo,

> > > > Lvl2PtEntry[Index2].Bits.Addr= essHi);

> > > > +    &nbs= p;       for (Index1 =3D 0; Index1 <<= /o:p>

> > > > SIZE_4KB/sizeof(VTD_SECOND_LE= VEL_PAGING_ENTRY); Index1++) {

> > > > +    &nbs= p;         if (Lvl1PtEntry[Index1].= Uint64 !=3D 0) {

> > > > +    &nbs= p;           DEBUG ((DEBU= G_VERBOSE,"      Lvl1Pt Entry(0x%03x) -<= /o:p>

> > > 0x%016lx\n",

> > > > Index1, Lvl1PtEntry[Index1].U= int64));

> > > > +    &nbs= p;         }

> > > >     =          }

> > > >     =        }

> > > >     =      }

> > > > @@ -510,6 +600,7 @@ PageAttri= buteToLength (

> > > >    @param[in]&= nbsp;  VtdIndex         &= nbsp;       The index used to identify a VTd<= o:p>

> engine.

> > > >    @param[in]&= nbsp;  SecondLevelPagingEntry   The second level paging entr= y in

> > > > VTd table for the device.

> > > >    @param[in]&= nbsp;  Address         &n= bsp;        The address to be checked.

> > > > +  @param[in]  = ; Is5LevelPaging          = ; If it is the 5 level paging.

> > > >    @param[out]=   PageAttributes         =   The page attribute of the page

> entry.

> > > >

> > > >    @return The= page entry.

> > > > @@ -519,6 +610,7 @@ GetSecond= LevelPageTableEntry (

> > > >    IN  UI= NTN            =              Vt= dIndex,

> > > >    IN  VT= D_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,

> > > >    IN  PH= YSICAL_ADDRESS          &= nbsp;   Address,

> > > > +  IN  BOOLEAN = ;            &n= bsp;         Is5LevelPaging,

> > > >    OUT PAGE_AT= TRIBUTE           &n= bsp;    *PageAttribute

> > > >    )

> > > >  {

> > > > @@ -526,17 +618,38 @@ GetSeco= ndLevelPageTableEntry (

> > > >    UINTN =             &nb= sp;   Index2;

> > > >    UINTN =             &nb= sp;   Index3;

> > > >    UINTN =             &nb= sp;   Index4;

> > > > +  UINTN  &nbs= p;            &= nbsp; Index5;

> > > >    UINT64 = ;            &n= bsp;  *L1PageTable;

> > > >    UINT64 = ;            &n= bsp;  *L2PageTable;

> > > >    UINT64 = ;            &n= bsp;  *L3PageTable;

> > > >    UINT64 = ;            &n= bsp;  *L4PageTable;

> > > > +  UINT64  &nb= sp;            = *L5PageTable;

> > > >

> > > > +  Index5 =3D ((UINTN)RS= hiftU64 (Address, 48)) &

> > > > + PAGING_VTD_INDEX_MASK;=

> > > >    Index4 =3D = ((UINTN)RShiftU64 (Address, 39)) &

> PAGING_VTD_INDEX_MASK;

> > > >    Index3 =3D = ((UINTN)Address >> 30) & PAGING_VTD_INDEX_MASK;

> > > >    Index2 =3D = ((UINTN)Address >> 21) & PAGING_VTD_INDEX_MASK;

> > > >    Index1 =3D = ((UINTN)Address >> 12) & PAGING_VTD_INDEX_MASK;

> > > >

> > > > -  L4PageTable =3D (UINT= 64 *)SecondLevelPagingEntry;

> > > > +  if (Is5LevelPaging) {=

> > > > +    L5PageTab= le =3D (UINT64 *)SecondLevelPagingEntry;

> > > > +    if (L5Pag= eTable[Index5] =3D=3D 0) {

> > > > +    &nbs= p; L5PageTable[Index5] =3D (UINT64)(UINTN)AllocateZeroPages (1);=

> > > > +    &nbs= p; if (L5PageTable[Index5] =3D=3D 0) {

> > > > +    &nbs= p;   DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL5 PAGE FAIL

> > > > (0x%x)!!!!!!\n", Index4)= );

> > > > +    &nbs= p;   ASSERT(FALSE);

> > > > +    &nbs= p;   *PageAttribute =3D PageNone;

> > > > +    &nbs= p;   return NULL;

> > > > +    &nbs= p; }

> > > > +    &nbs= p; FlushPageTableMemory (VtdIndex, (UINTN)L5PageTable[Index5],

> > > > SIZE_4KB);

> > > > +    &nbs= p; SetSecondLevelPagingEntryAttribute

> > > > ((VTD_SECOND_LEVEL_PAGING_ENT= RY *)&L5PageTable[Index5],

> > > > EDKII_IOMMU_ACCESS_READ | EDK= II_IOMMU_ACCESS_WRITE);

> > > > +    &nbs= p; FlushPageTableMemory (VtdIndex,

> > > > + (UINTN)&L5PageTable[Ind= ex5],

> > > > sizeof(L5PageTable[Index5]));=

> > > > +    }

> > > > +    L4PageTab= le =3D (UINT64 *)(UINTN)(L5PageTable[Index5] &

> > > > PAGING_4K_ADDRESS_MASK_64);

> > > > +  } else {

> > > > +    L4PageTab= le =3D (UINT64 *)SecondLevelPagingEntry;  }

> > > > +

> > > >    if (L4PageT= able[Index4] =3D=3D 0) {

> > > >     = L4PageTable[Index4] =3D (UINT64)(UINTN)AllocateZeroPages (1);

> > > >     = if (L4PageTable[Index4] =3D=3D 0) { @@ -785,7 +898,7 @@

> > > > SetSecondLevelPagingAttribute= (

> > > >    }

> > > >

> > > >    while (Leng= th !=3D 0) {

> > > > -    PageEntry= =3D GetSecondLevelPageTableEntry (VtdIndex,

> > > > SecondLevelPagingEntry, BaseA= ddress, &PageAttribute);

> > > > +    PageEntry= =3D GetSecondLevelPageTableEntry (VtdIndex,

> > > > SecondLevelPagingEntry, BaseA= ddress,

> > > > mVtdUnitInformation[VtdIndex]= .Is5LevelPaging, &PageAttribute);

> > > >     = if (PageEntry =3D=3D NULL) {

> > > >     =    DEBUG ((DEBUG_ERROR, "PageEntry - NULL\n"));

> > > >     =    return RETURN_UNSUPPORTED;

> > > > @@ -913,7 +1026,7 @@ SetAcces= sAttribute (

> > > >

> > > >    if (ExtCont= extEntry !=3D NULL) {

> > > >     = if (ExtContextEntry->Bits.Present =3D=3D 0) {

> > > > -    &nbs= p; SecondLevelPagingEntry =3D CreateSecondLevelPagingEntry (VtdIndex,<= /o:p>

> 0);

> > > > +    &nbs= p; SecondLevelPagingEntry =3D CreateSecondLevelPagingEntry

> > > > + (VtdIndex, 0,

> > > > mVtdUnitInformation[VtdIndex]= .Is5LevelPaging);

> > > >     =    DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%0= 4x

> > > > B%02x D%02x F%02x) New\n"= ;, SecondLevelPagingEntry, Segment,

> > > > SourceId.Bits.Bus, SourceId.B= its.Device, SourceId.Bits.Function));

> > > >     =    Pt =3D (UINT64)RShiftU64

> > > > ((UINT64)(UINTN)SecondLevelPa= gingEntry,

> > > > 12);

> > > >

> > > > @@ -922,7 +1035,7 @@ SetAcces= sAttribute (

> > > >     =    ExtContextEntry->Bits.DomainIdentifier =3D DomainIdentifier= ;

> > > >     =    ExtContextEntry->Bits.Present =3D 1;

> > > >     =    FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry,

> > > > sizeof(*ExtContextEntry));

> > > > -    &nbs= p; DumpDmarExtContextEntryTable

> > > > (mVtdUnitInformation[VtdIndex= ].ExtRootEntryTable);

> > > > +    &nbs= p; DumpDmarExtContextEntryTable

> > > > (mVtdUnitInformation[VtdIndex= ].ExtRootEntryTable,

> > > > mVtdUnitInformation[VtdIndex]= .Is5LevelPaging);

> > > >     =    mVtdUnitInformation[VtdIndex].HasDirtyContext =3D TRUE;

> > > >     = } else {

> > > >     =    SecondLevelPagingEntry =3D (VOID

> > > > *)(UINTN)VTD_64BITS_ADDRESS(E= xtContextEntry-

> > > > >Bits.SecondLevelPageTrans= lationPointerLo, ExtContextEntry-

> > > > >Bits.SecondLevelPageTrans= lationPointerHi);

> > > > @@ -930,7 +1043,7 @@ SetAcces= sAttribute (

> > > >     = }

> > > >    } else if (= ContextEntry !=3D NULL) {

> > > >     = if (ContextEntry->Bits.Present =3D=3D 0) {

> > > > -    &nbs= p; SecondLevelPagingEntry =3D CreateSecondLevelPagingEntry (VtdIndex,<= /o:p>

> 0);

> > > > +    &nbs= p; SecondLevelPagingEntry =3D CreateSecondLevelPagingEntry

> > > > + (VtdIndex, 0,

> > > > mVtdUnitInformation[VtdIndex]= .Is5LevelPaging);

> > > >     =    DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%0= 4x

> > > > B%02x D%02x F%02x) New\n"= ;, SecondLevelPagingEntry, Segment,

> > > > SourceId.Bits.Bus, SourceId.B= its.Device, SourceId.Bits.Function));

> > > >     =    Pt =3D (UINT64)RShiftU64

> > > > ((UINT64)(UINTN)SecondLevelPa= gingEntry,

> > > > 12);

> > > >

> > > > @@ -939,7 +1052,7 @@ SetAcces= sAttribute (

> > > >     =    ContextEntry->Bits.DomainIdentifier =3D DomainIdentifier;

> > > >     =    ContextEntry->Bits.Present =3D 1;

> > > >     =    FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry,

> > > > sizeof(*ContextEntry));<= /o:p>

> > > > -    &nbs= p; DumpDmarContextEntryTable

> > > > (mVtdUnitInformation[VtdIndex= ].RootEntryTable);

> > > > +    &nbs= p; DumpDmarContextEntryTable

> > > > (mVtdUnitInformation[VtdIndex= ].RootEntryTable,

> > > > mVtdUnitInformation[VtdIndex]= .Is5LevelPaging);

> > > >     =    mVtdUnitInformation[VtdIndex].HasDirtyContext =3D TRUE;

> > > >     = } else {

> > > >     =    SecondLevelPagingEntry =3D (VOID

> > > > *)(UINTN)VTD_64BITS_ADDRESS(C= ontextEntry-

> > > > >Bits.SecondLevelPageTrans= lationPointerLo, ContextEntry-

> > > > >Bits.SecondLevelPageTrans= lationPointerHi);

> > > > @@ -1000,7 +1113,7 @@ AlwaysE= nablePageAttribute (

> > > >

> > > >    if (mVtdUni= tInformation[VtdIndex].FixedSecondLevelPagingEntry =3D=3D 0) {

> > > >     = DEBUG((DEBUG_INFO, "CreateSecondLevelPagingEntry - %d\n",

> > > > VtdIndex));

> > > > -    mVtdUnitI= nformation[VtdIndex].FixedSecondLevelPagingEntry =3D

> > > > CreateSecondLevelPagingEntry = (VtdIndex, EDKII_IOMMU_ACCESS_READ |

> > > > EDKII_IOMMU_ACCESS_WRITE);

> > > > +    mVtdUnitI= nformation[VtdIndex].FixedSecondLevelPagingEntry =3D

> > > > CreateSecondLevelPagingEntry = (VtdIndex, EDKII_IOMMU_ACCESS_READ |

> > > > EDKII_IOMMU_ACCESS_WRITE,

> > > > mVtdUnitInformation[VtdIndex]= .Is5LevelPaging);

> > > >    }

> > > >

> > > >    SecondLevel= PagingEntry =3D

> > > > mVtdUnitInformation[VtdIndex]= .FixedSecondLevelPagingEntry;

> > > > diff --git

> > > >

> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/= IntelVTdDxe/TranslationTableEx.

> > > > c

> > > >

> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/= IntelVTdDxe/TranslationTableEx.

> > > > c

> > > > index 0ed9e3ca..a4466891 1006= 44

> > > > ---

> > > >

> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/= IntelVTdDxe/TranslationTableEx.

> > > > c

> > > > +++

> > > >

> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/= IntelVTdDxe/TranslationTableEx.

> > > > c

> > > > @@ -78,11 +78,28 @@ CreateExt= ContextEntry (

> > > >

> > > >     = DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n",

> > > > mVtdUnitInformation[VtdIndex]= .Segment, SourceId.Bits.Bus,

> > > > SourceId.Bits.Device, SourceI= d.Bits.Function));

> > > >

> > > > -    if ((mVtd= UnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)

> {

> > > > -    &nbs= p; DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on

> > > > VTD %d !!!!\n", VtdIndex= ));

> > > > +    mVtdUnitI= nformation[VtdIndex].Is5LevelPaging =3D FALSE;

> > > > +    if ((mVtd= UnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT3) !=3D 0)<= /p>

> {

> > > > +    &nbs= p; mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D TRUE;

> > > > +    &nbs= p; if (mAcpiDmarTable->HostAddressWidth <=3D 48) {

> > > > +    &nbs= p;   if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW &

> > > > + BIT2) !=3D 0)

> > {

> > > > +    &nbs= p;     mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D= FALSE;

> > > > +    &nbs= p;   }

> > > > +    &nbs= p; }

> > > > +    } else if= ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW &

> > > > + BIT2) =3D=3D

> > > > 0) {

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported

> > > > + on

> > > > VTD %d !!!!\n", VtdIndex= ));

> > > >     =    return EFI_UNSUPPORTED;

> > > >     = }

> > > > -    ExtContex= tEntry->Bits.AddressWidth =3D 0x2;

> > > > +

> > > > +    if (mVtdU= nitInformation[VtdIndex].Is5LevelPaging) {

> > > > +    &nbs= p; ExtContextEntry->Bits.AddressWidth =3D 0x3;

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "Using 4-level page-table on VTD %d\n",

> > > > VtdIndex));

> > > > +    } else {<= o:p>

> > > > +    &nbs= p; ExtContextEntry->Bits.AddressWidth =3D 0x2;

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "Using 5-level page-table on VTD %d\n",

> > > > VtdIndex));

> > > > +    }

> > > > +

> > > > +

> > > >    }

> > > >

> > > >    FlushPageTa= bleMemory (VtdIndex,

> > > > (UINTN)mVtdUnitInformation[Vt= dIndex].ExtRootEntryTable,

> > > > EFI_PAGES_TO_SIZE(EntryTableP= ages));

> > > > @@ -93,11 +110,13 @@ CreateEx= tContextEntry (

> > > >  /**

> > > >    Dump DMAR e= xtended context entry table.

> > > >

> > > > -  @param[in]  ExtR= ootEntry DMAR extended root entry.

> > > > +  @param[in]  ExtR= ootEntry    DMAR extended root entry.

> > > > +  @param[in]  Is5L= evelPaging  If it is the 5 level paging.

> > > >  **/

> > > >  VOID

> > > >  DumpDmarExtContextEntry= Table (

> > > > -  IN VTD_EXT_ROOT_ENTRY= *ExtRootEntry

> > > > +  IN VTD_EXT_ROOT_ENTRY= *ExtRootEntry,  IN BOOLEAN Is5LevelPaging

> > > >    )

> > > >  {

> > > >    UINTN =             &nb= sp;   Index;

> > > > @@ -127,7 +146,7 @@ DumpDmarE= xtContextEntryTable (

> > > >     =    if (ExtContextEntry[Index2].Bits.Present =3D=3D 0) {

> > > >     =      continue;

> > > >     =    }

> > > > -    &nbs= p; DumpSecondLevelPagingEntry ((VOID

> > > > *)(UINTN)VTD_64BITS_ADDRESS(E= xtContextEntry[Index2].Bits.SecondLev

> > > > el

> > > > Pa

> > > > geTranslationPointerLo,<= /o:p>

> > > > ExtContextEntry[Index2].Bits.= SecondLevelPageTranslationPointerHi))

> > > > ;

> > > > +    &nbs= p; DumpSecondLevelPagingEntry ((VOID

> > > > *)(UINTN)VTD_64BITS_ADDRESS(E= xtContextEntry[Index2].Bits.SecondLev

> > > > el

> > > > Pa

> > > > geTranslationPointerLo,<= /o:p>

> > > > ExtContextEntry[Index2].Bits.= SecondLevelPageTranslationPointerHi),

> > > > Is5LevelPaging);

> > > >     = }

> > > >

> > > >     = if (ExtRootEntry[Index].Bits.UpperPresent =3D=3D 0) { diff --git

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/VtdReg.c

> > > > b/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/VtdReg.c

> > > > index 699639ba..686d235f 1006= 44

> > > > ---

> > > > a/Silicon/Intel/IntelSiliconP= kg/Feature/VTd/IntelVTdDxe/VtdReg.c

> > > > +++ b/Silicon/Intel/IntelSili= conPkg/Feature/VTd/IntelVTdDxe/VtdReg

> > > > +++ .c

> > > > @@ -174,8 +174,14 @@ PrepareV= tdConfig (

> > > >     = if ((mVtdUnitInformation[Index].CapReg.Bits.SLLPS & BIT0) =3D=3D 0) {<= o:p>

> > > >     =    DEBUG((DEBUG_WARN, "!!!! 2MB super page is not supported = on

> > > > VTD %d !!!!\n", Index));=

> > > >     = }

> > > > -    if ((mVtd= UnitInformation[Index].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {=

> > > > -    &nbs= p; DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on

> > > > VTD %d !!!!\n", Index));=

> > > > +    if ((mVtd= UnitInformation[Index].CapReg.Bits.SAGAW & BIT3) !=3D 0) {

> > > > +    &nbs= p; DEBUG((DEBUG_INFO, "Support 5-level page-table on VTD

> > > > + %d\n",

> > > > Index));

> > > > +    }

> > > > +    if ((mVtd= UnitInformation[Index].CapReg.Bits.SAGAW & BIT2) !=3D 0) {

> > > > +    &nbs= p; DEBUG((DEBUG_INFO, "Support 4-level page-table on VTD

> > > > + %d\n",

> > > > Index));

> > > > +    }

> > > > +    if ((mVtd= UnitInformation[Index].CapReg.Bits.SAGAW & (BIT3 |

> > > > + BIT2)) =3D=3D 0)=

> > > > {

> > > > +    &nbs= p; DEBUG((DEBUG_ERROR, "!!!! Page-table type 0x%X is not

> > > > + supported on

> > > > VTD %d !!!!\n", Index, m= VtdUnitInformation[Index].CapReg.Bits.SAGAW));

> > > >     =    return ;

> > > >     = }

> > > >

> > > > --

> > > > 2.16.2.windows.1

 

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