Re: [edk2-devel] [PATCH v6 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo

["Sheng Wei" <w.sheng@intel.com>]

Hi Laszlo,
Thank you.
I will add the R-b part.
BR
Sheng Wei

> -----Original Message-----
> From: Laszlo Ersek <lersek@redhat.com>
> Sent: 2020年11月11日 3:05
> To: devel@edk2.groups.io; Sheng, W <w.sheng@intel.com>
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar,
> Rahul1 <rahul1.kumar@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
> Subject: Re: [edk2-devel] [PATCH v6 1/2] UefiCpuPkg/PiSmmCpuDxeSmm:
> Correct the Cr3 typo
> 
> Wei,
> 
> can you please explain why you didn't pick up my R-b, which I have given
> *twice* for this patch?
> 
> https://edk2.groups.io/g/devel/message/66872
> https://edk2.groups.io/g/devel/message/67006
> 
> Do you understand what it means to "pick up an R-b"?
> 
> https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-git-
> guide-for-edk2-contributors-and-maintainers#contrib-28
> 
> Laszlo
> 
> On 11/10/20 03:24, Sheng Wei wrote:
> > Change the variable name from mInternalGr3 to mInternalCr3.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015
> >
> > Signed-off-by: Sheng Wei <w.sheng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Rahul Kumar <rahul1.kumar@intel.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > ---
> >  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10
> +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> > index ebfc46ad45..d67f036aea 100644
> > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> > @@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
> >    {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},  };
> >
> > -UINTN  mInternalGr3;
> > +UINTN  mInternalCr3;
> >
> >  /**
> >    Set the internal page table base address.
> > @@ -46,7 +46,7 @@ SetPageTableBase (
> >    IN UINTN   Cr3
> >    )
> >  {
> > -  mInternalGr3 = Cr3;
> > +  mInternalCr3 = Cr3;
> >  }
> >
> >  /**
> > @@ -59,8 +59,8 @@ GetPageTableBase (
> >    VOID
> >    )
> >  {
> > -  if (mInternalGr3 != 0) {
> > -    return mInternalGr3;
> > +  if (mInternalCr3 != 0) {
> > +    return mInternalCr3;
> >    }
> >    return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);  } @@ -252,7
> > +252,7 @@ ConvertPageEntryAttribute (
> >    if ((Attributes & EFI_MEMORY_RO) != 0) {
> >      if (IsSet) {
> >        NewPageEntry &= ~(UINT64)IA32_PG_RW;
> > -      if (mInternalGr3 != 0) {
> > +      if (mInternalCr3 != 0) {
> >          // Environment setup
> >          // ReadOnly page need set Dirty bit for shadow stack
> >          NewPageEntry |= IA32_PG_D;
> >