From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0075.outbound.protection.outlook.com [104.47.33.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39FF421A16EC1 for ; Thu, 15 Jun 2017 09:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=mf3NCKhArUwg15g5/dqBW3Dw0xfqkeBmQuO1SOXwwsE=; b=le8dLy9jdkOoKj3rgXQUrOZwiNeQvF3u/b4uGUu3Qk14B6jim4Gr02t+MAuB+w7xNa535RjRydd/ZHhstnJmEMZvyV8N2qSfBlJUDP7yVYkENLUN1R8qfW3TkaMYmzR7tUdsdF8NY3HIzKGDWyPLIFG+sMMBG+D0Bf8HTCqSQAA= Received: from CY4PR12MB1702.namprd12.prod.outlook.com (10.175.62.136) by CY4PR12MB1237.namprd12.prod.outlook.com (10.168.167.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1157.12; Thu, 15 Jun 2017 16:28:43 +0000 Received: from CY4PR12MB1702.namprd12.prod.outlook.com ([10.175.62.136]) by CY4PR12MB1702.namprd12.prod.outlook.com ([10.175.62.136]) with mapi id 15.01.1157.017; Thu, 15 Jun 2017 16:28:42 +0000 From: "Kirkendall, Garrett" To: "Fan, Jeff" , "Duran, Leo" , "edk2-devel@lists.01.org" CC: "Justen, Jordan L" , "Gao, Liming" Thread-Topic: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD. Thread-Index: AQHS3t3fiLioPhknh02fenpw1a0q96IabdBQgAAGkGCAAgEYAIAI2ClwgADIo2A= Date: Thu, 15 Jun 2017 16:28:42 +0000 Message-ID: References: <1496764741-6327-1-git-send-email-leo.duran@amd.com> <1496764741-6327-3-git-send-email-leo.duran@amd.com> <542CF652F8836A4AB8DBFAAD40ED192A4C60651E@shsmsx102.ccr.corp.intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C606544@shsmsx102.ccr.corp.intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C60B3CE@shsmsx102.ccr.corp.intel.com> In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C60B3CE@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=amd.com; x-originating-ip: [165.204.77.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; CY4PR12MB1237; 20:Zk/MDYw0gVpdewndR1gihbEj6S9CfZoGcaWZtZCVN6dgL2dohlqwACzhAvh0fjWTWbGv0hR9U7sjPQBIqpAHkUscxg0A1ZWausI1pZDh9zlZyW9+4766AIVmSHVjwYv5/EWzIxJUZq1+xX5l+ST4wkHRlzTsOlG2YKqtGPjc+cKZcUjE/8XzIpsn09OGJswBlTHxGE6bF74YIXiBeANVY8QPij2BBmmL1pCbWa4JkoJBlR2X5DsZpoyKx9wV3oY7 x-forefront-antispam-report: SFV:SKI; SCL:-1SFV:NSPM; SFS:(10009020)(6009001)(6029001)(39840400002)(39450400003)(39850400002)(39400400002)(39410400002)(39860400002)(13464003)(377454003)(8676002)(8936002)(81166006)(53936002)(6436002)(38730400002)(6246003)(966005)(33656002)(72206003)(86362001)(2900100001)(4326008)(6506006)(7736002)(25786009)(102836003)(3846002)(53946003)(54906002)(55016002)(6116002)(9686003)(99286003)(77096006)(6306002)(53546009)(122556002)(93886004)(5660300001)(50986999)(189998001)(229853002)(76176999)(54356999)(305945005)(74316002)(2906002)(3280700002)(478600001)(14454004)(66066001)(2950100002)(3660700001)(7696004)(2501003)(579004)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR12MB1237; H:CY4PR12MB1702.namprd12.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; x-ms-traffictypediagnostic: CY4PR12MB1237: x-ms-office365-filtering-correlation-id: 53cedb52-98bb-4a26-5558-08d4b40b9638 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081); SRVR:CY4PR12MB1237; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(166708455590820)(767451399110)(162533806227266)(81227570615382)(228905959029699); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(93006095)(93001095)(3002001)(10201501046)(100000703101)(100105400095)(6055026)(6041248)(20161123558100)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123555025)(20161123560025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:CY4PR12MB1237; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:CY4PR12MB1237; x-forefront-prvs: 0339F89554 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jun 2017 16:28:42.2590 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1237 Subject: Re: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Jun 2017 16:27:28 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Jeff, that would be a good option for determining that the processor is man= ufactured by AMD. It looks like you correctly found this in the "AMD64 Arc= hitecture Programmer's Manual Volume 3: General-Purpose and System Instruct= ions, Appendix E". Also, if more precise identification is needed, Family Model and Stepping c= an be obtained from "CPUID Fn0000_0001_EAX Family, Model, Stepping Identifi= ers" also documented there. GARRETT KIRKENDALL SMTS Firmware Engineer | CTE 7171 Southwest Parkway, Austin, TX 78735 USA=20 AMD=A0=A0 facebook=A0 |=A0 amd.com > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Fan, Jeff > Sent: Thursday, June 15, 2017 3:52 AM > To: Duran, Leo ; edk2-devel@lists.01.org > Cc: Justen, Jordan L ; Gao, Liming > > Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify > GetProcessorLocationByApicId() to support AMD. >=20 > Leo, >=20 > Could you use the CPUID Fn0000_0000_E[D,C,B]X values as below to identify > AMD processor? >=20 > Table E-1. CPUID Fn0000_0000_E[D,C,B]X values Register Value Description > CPUID Fn0000_0000_EBX 6874_7541h The ASCII characters "h t u A". > CPUID Fn0000_0000_ECX 444D_4163h The ASCII characters "D M A c". > CPUID Fn0000_0000_EDX 6974_6E65h The ASCII characters "i t n e". >=20 > Maybe, your guys have other better solution. >=20 > Thanks! > Jeff > -----Original Message----- > From: Duran, Leo [mailto:leo.duran@amd.com] > Sent: Saturday, June 10, 2017 4:12 AM > To: Fan, Jeff; edk2-devel@lists.01.org > Cc: Justen, Jordan L; Gao, Liming > Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify > GetProcessorLocationByApicId() to support AMD. >=20 > Hi Jeff, > Please see my replies below. > Thanks, > Leo. >=20 > > -----Original Message----- > > From: Fan, Jeff [mailto:jeff.fan@intel.com] > > Sent: Thursday, June 08, 2017 12:37 AM > > To: Fan, Jeff ; Duran, Leo ; > > edk2-devel@lists.01.org > > Cc: Justen, Jordan L ; Gao, Liming > > > > Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify > > GetProcessorLocationByApicId() to support AMD. > > > > Leo, > > > > Correct some words in below mail body. > > > > Jeff > > > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > > Fan, Jeff > > Sent: Thursday, June 08, 2017 1:34 PM > > To: Leo Duran; edk2-devel@lists.01.org > > Cc: Justen, Jordan L; Gao, Liming > > Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify > > GetProcessorLocationByApicId() to support AMD. > > > > Leo, > > > > 1. If Intel SDM supports the ExtendedCpuIdIndex >=3D > > CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the following > > code may cause unexpected result for Intel processor. > > if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) > > May we use another way to check AMD or Intel processor? > [Duran, Leo] Any specific suggestions? Thanks. >=20 > > > > 2. Goto Statements should not be used (in general) except for error > > handling > > (https://github.com/tianocore- > > docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf) >=20 > [Duran, Leo] OK, I will not use 'goto' in this case. >=20 > > > > Thanks! > > Jeff > > > > -----Original Message----- > > From: Leo Duran [mailto:leo.duran@amd.com] > > Sent: Tuesday, June 06, 2017 11:59 PM > > To: edk2-devel@lists.01.org > > Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh > > Subject: [PATCH v3 2/2] UefiCpuPkg: Modify > > GetProcessorLocationByApicId() to support AMD. > > > > Cc: Jordan Justen > > Cc: Jeff Fan > > Cc: Liming Gao > > Cc: Brijesh Singh > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Leo Duran > > --- > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 > > +++++++++++++++------ > > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 > +++++++++++++++-- > > ---- > > 2 files changed, 184 insertions(+), 76 deletions(-) mode change > > 100644 =3D> > > 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > > > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > old mode 100644 > > new mode 100755 > > index f81bbb2..02dfabc > > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > @@ -4,6 +4,8 @@ > > This local APIC library instance supports xAPIC mode only. > > > > Copyright (c) 2010 - 2016, Intel Corporation. All rights > > reserved.
> > + Copyright (c) 2017, AMD Inc. All rights reserved.
> > + > > This program and the accompanying materials > > are licensed and made available under the terms and conditions of > > the BSD License > > which accompanies this distribution. The full text of the license > > may be found at @@ -15,6 +17,7 @@ **/ > > > > #include > > +#include > > #include > > #include > > > > @@ -966,20 +969,29 @@ GetProcessorLocationByApicId ( > > OUT UINT32 *Thread OPTIONAL > > ) > > { > > - BOOLEAN TopologyLeafSupported; > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; > > + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; > > + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; > > + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; > > + UINT32 MaxStandardCpuIdIndex; > > + UINT32 MaxExtendedCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + UINT32 MaxThreadPerPackageMask; > > + UINT32 ActualThreadPerPackageMask; > > + UINT32 MaxCoresPerNode; > > + UINT32 CorePerNodeMask; > > + UINT32 ApicIdShift; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > > > // > > // Check if the processor is capable of supporting more than one > > logical processor. > > @@ -987,10 +999,10 @@ GetProcessorLocationByApicId ( > > AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > if (Thread !=3D NULL) { > > - *Thread =3D 0; > > + *Thread =3D 0; > > } > > if (Core !=3D NULL) { > > - *Core =3D 0; > > + *Core =3D 0; > > } > > if (Package !=3D NULL) { > > *Package =3D 0; > > @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId ( > > CoreBits =3D 0; > > > > // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // Get the max index of CPUID > > // > > - TopologyLeafSupported =3D FALSE; > > - > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > > NULL); > > + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > > NULL, NULL, > > + NULL); > > > > // > > // If the extended topology enumeration leaf is available, it > > // is the preferred mechanism for enumerating topology. > > // > > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > AsmCpuidEx( > > CPUID_EXTENDED_TOPOLOGY, > > 0, > > @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId ( > > // supported on that processor. > > // > > if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > - TopologyLeafSupported =3D TRUE; > > - > > // > > // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration > > parameters to extract > > // the SMT sub-field of x2APIC ID. > > @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId ( > > } > > SubIndex++; > > } while (LevelType !=3D > > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + goto GetLocation; > > } > > } > > > > - if (!TopologyLeafSupported) { > > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > > NULL); > > - MaxLogicProcessorsPerPackage =3D > > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > NULL, NULL, NULL); > > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > > + NULL); MaxLogicProcessorsPerPackage =3D > > + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + > > + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > NULL, NULL, NULL); > > + if (CacheParamsEax.Uint32 !=3D 0) { > > MaxCoresPerPackage =3D > > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + goto GetBits; > > } > > - else { > > + } > > + > > + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { > > + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > > &AmdExtendedCpuSigEcx.Uint32, NULL); > > + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > > + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > > &AmdProcessorTopologyEbx.Uint32, > > + &AmdProcessorTopologyEcx.Uint32, NULL); > > + > > + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / > > + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); > > + > > // > > - // Must be a single-core processor. > > + // Account for actual thread count (e.g., SMT disabled) > > // > > - MaxCoresPerPackage =3D 1; > > + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > > + MaxThreadPerPackageMask =3D 1 << > > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > > + ActualThreadPerPackageMask =3D 1; > > + while (ActualThreadPerPackageMask < > > + MaxLogicProcessorsPerPackage) > > { > > + ActualThreadPerPackageMask <<=3D 1; > > + } > > + > > + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > > + MaxCoresPerNode =3D MaxCoresPerPackage / > > + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); > > + > > + CorePerNodeMask =3D 1; > > + while (CorePerNodeMask < MaxCoresPerNode) { > > + CorePerNodeMask <<=3D 1; > > + } > > + CorePerNodeMask -=3D 1; > > + > > + ApicIdShift =3D 0; > > + do { > > + ApicIdShift +=3D 1; > > + ActualThreadPerPackageMask <<=3D 1; > > + } while (ActualThreadPerPackageMask < > > + MaxThreadPerPackageMask); > > + > > + // > > + // Adjust APIC Id to report concatenation of > Package|Core|Thread. > > + // > > + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> > > + ApicIdShift) | > > (InitialApicId & CorePerNodeMask); > > + } > > + > > + goto GetBits; > > } > > + } > > + > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage =3D 1; > > > > - ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > > MaxCoresPerPackage - 1) + 1); > > - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } > > +GetBits: > > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > > +MaxCoresPerPackage - 1) + 1); > > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); > > > > +GetLocation: > > if (Thread !=3D NULL) { > > - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > } > > if (Core !=3D NULL) { > > - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1)= ; > > + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > > } > > if (Package !=3D NULL) { > > *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); diff --gi= t > > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > index e690d2a..726e1e0 100644 > > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > @@ -5,6 +5,8 @@ > > which have xAPIC and x2APIC modes. > > > > Copyright (c) 2010 - 2016, Intel Corporation. All rights > > reserved.
> > + Copyright (c) 2017, AMD Inc. All rights reserved.
> > + > > This program and the accompanying materials > > are licensed and made available under the terms and conditions of > > the BSD License > > which accompanies this distribution. The full text of the license > > may be found at @@ -16,6 +18,7 @@ **/ > > > > #include > > +#include > > #include > > #include > > > > @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId ( > > OUT UINT32 *Thread OPTIONAL > > ) > > { > > - BOOLEAN TopologyLeafSupported; > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; > > + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; > > + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; > > + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; > > + UINT32 MaxStandardCpuIdIndex; > > + UINT32 MaxExtendedCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + UINT32 MaxThreadPerPackageMask; > > + UINT32 ActualThreadPerPackageMask; > > + UINT32 MaxCoresPerNode; > > + UINT32 CorePerNodeMask; > > + UINT32 ApicIdShift; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > > > // > > // Check if the processor is capable of supporting more than one > > logical processor. > > @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId ( > > AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > if (Thread !=3D NULL) { > > - *Thread =3D 0; > > + *Thread =3D 0; > > } > > if (Core !=3D NULL) { > > - *Core =3D 0; > > + *Core =3D 0; > > } > > if (Package !=3D NULL) { > > *Package =3D 0; > > @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId ( > > CoreBits =3D 0; > > > > // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // Get the max index of CPUID > > // > > - TopologyLeafSupported =3D FALSE; > > - > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > > NULL); > > + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > > NULL, NULL, > > + NULL); > > > > // > > // If the extended topology enumeration leaf is available, it > > // is the preferred mechanism for enumerating topology. > > // > > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > AsmCpuidEx( > > CPUID_EXTENDED_TOPOLOGY, > > 0, > > @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId ( > > // supported on that processor. > > // > > if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > - TopologyLeafSupported =3D TRUE; > > - > > // > > // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration > > parameters to extract > > // the SMT sub-field of x2APIC ID. > > @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId ( > > } > > SubIndex++; > > } while (LevelType !=3D > > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + goto GetLocation; > > } > > } > > > > - if (!TopologyLeafSupported) { > > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > > NULL); > > - MaxLogicProcessorsPerPackage =3D > > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > NULL, NULL, NULL); > > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > > + NULL); MaxLogicProcessorsPerPackage =3D > > + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + > > + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > NULL, NULL, NULL); > > + if (CacheParamsEax.Uint32 !=3D 0) { > > MaxCoresPerPackage =3D > > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + goto GetBits; > > } > > - else { > > + } > > + > > + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { > > + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > > &AmdExtendedCpuSigEcx.Uint32, NULL); > > + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > > + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > > &AmdProcessorTopologyEbx.Uint32, > > + &AmdProcessorTopologyEcx.Uint32, NULL); > > + > > + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / > > + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); > > + > > // > > - // Must be a single-core processor. > > + // Account for actual thread count (e.g., SMT disabled) > > // > > - MaxCoresPerPackage =3D 1; > > + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > > + MaxThreadPerPackageMask =3D 1 << > > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > > + ActualThreadPerPackageMask =3D 1; > > + while (ActualThreadPerPackageMask < > > + MaxLogicProcessorsPerPackage) > > { > > + ActualThreadPerPackageMask <<=3D 1; > > + } > > + > > + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > > + MaxCoresPerNode =3D MaxCoresPerPackage / > > + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); > > + > > + CorePerNodeMask =3D 1; > > + while (CorePerNodeMask < MaxCoresPerNode) { > > + CorePerNodeMask <<=3D 1; > > + } > > + CorePerNodeMask -=3D 1; > > + > > + ApicIdShift =3D 0; > > + do { > > + ApicIdShift +=3D 1; > > + ActualThreadPerPackageMask <<=3D 1; > > + } while (ActualThreadPerPackageMask < > > + MaxThreadPerPackageMask); > > + > > + // > > + // Adjust APIC Id to report concatenation of > Package|Core|Thread. > > + // > > + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> > > + ApicIdShift) | > > (InitialApicId & CorePerNodeMask); > > + } > > + > > + goto GetBits; > > } > > + } > > + > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage =3D 1; > > > > - ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > > MaxCoresPerPackage - 1) + 1); > > - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } > > +GetBits: > > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > > +MaxCoresPerPackage - 1) + 1); > > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); > > > > +GetLocation: > > if (Thread !=3D NULL) { > > - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > } > > if (Core !=3D NULL) { > > - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1)= ; > > + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > > } > > if (Package !=3D NULL) { > > *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > > -- > > 2.7.4 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel