From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=helo; client-ip=104.47.32.41; helo=nam01-sn1-obe.outbound.protection.outlook.com; envelope-from=leo.duran@amd.com; receiver=edk2-devel@lists.01.org Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0041.outbound.protection.outlook.com [104.47.32.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 718ED2115F53F for ; Tue, 5 Jun 2018 18:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ptZk6bl+ssoYKGsYV23ev9Dt/qEPTag514wSl8QFOq0=; b=4vq2b4fqSAxUPJ9LQ9NIfsLW90d0G1yrhEejOmQ2urAPRvp2rIM0CjFa2d7ZdmaC7hxt6om/U5Mim+rktoU2G1AJFI/9FM+oYoq/4QiLlNcYpm2akR4MFp6BAn9jLBkg80zS2TqflDehOGwJmd4QWlie7ONF6szTRgUNK/6gp0w= Received: from CY4PR12MB1815.namprd12.prod.outlook.com (10.175.63.21) by CY4PR12MB1782.namprd12.prod.outlook.com (10.175.63.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.841.14; Wed, 6 Jun 2018 01:05:01 +0000 Received: from CY4PR12MB1815.namprd12.prod.outlook.com ([fe80::4112:efc5:3d83:464]) by CY4PR12MB1815.namprd12.prod.outlook.com ([fe80::4112:efc5:3d83:464%3]) with mapi id 15.20.0820.015; Wed, 6 Jun 2018 01:05:01 +0000 From: "Duran, Leo" To: "Zeng, Star" , "Dong, Eric" CC: "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Thread-Index: AQHT85KA32p5JwR1qkCtnAFfoM8r16RAS5wAgAAoj7uAEcoNEIAAOV4AgAAFNDA= Date: Wed, 6 Jun 2018 01:05:01 +0000 Message-ID: References: <1527188850-4553-1-git-send-email-leo.duran@amd.com> <1527188850-4553-2-git-send-email-leo.duran@amd.com>, <0C09AFA07DD0434D9E2A0C6AEB0483103BAF1160@shsmsx102.ccr.corp.intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103BB53B9A@shsmsx102.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB0483103BB53B9A@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=leo.duran@amd.com; x-originating-ip: [2605:6000:e7cd:8500:1d2f:b64d:ba07:de82] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; CY4PR12MB1782; 7:bOD/TKAuTL7HGSHnwYRekJzcjaWwAYFAIN0wN6zIoMNapgi0n9jU5qFxZ8sQfVaTcNc9Z3pvb7wS24LNH6uc7p7OibIbdJb/e47m1nCYRIjfzKQTGflNu3/UsDDU2MJpRt5aNLTBEFY5WgSF5q7jarJirVyUCpdB894RYQcdl/TnfKjqsuQ6De3PI8uA2+8tYhUdrcmianbcjyFqwNHVaYH8Cd6Gz1r0Jk/0TryLI+PR8iyX+EXp+7nXko7GB8LG; 20:ipYunzCuJTO1m+d+ZyXeDri7GQuKs6S0np3d9Kdqh4Sf4xHzwqs64Un9prjP5ckEoXa9akA0A14NPsYD1I0wuJhPm2qoT/br6otMATL+yJ8tzCjzzoNFLH+qYmntxdIfq9d+/YuxM7Ie2G9+AJ374ihec3iELMv1Z9KlSEEom55BMQ+62JzK4LPTH3+EKaSrd/HyOYn6383faeR4mSTD6VcxUOjpPlw1QN4M5pp9QH6T6yNZEiJoYZLHRchEJUeO x-ms-exchange-antispam-srfa-diagnostics: SOS; x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(5600026)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020); SRVR:CY4PR12MB1782; x-ms-traffictypediagnostic: CY4PR12MB1782: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(31051911155226)(767451399110)(106291317490208)(162533806227266)(265313219721884)(228905959029699); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231254)(944501410)(52105095)(6055026)(149027)(150027)(6041310)(20161123562045)(20161123558120)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(6072148)(201708071742011)(7699016); SRVR:CY4PR12MB1782; BCL:0; PCL:0; RULEID:; SRVR:CY4PR12MB1782; x-forefront-prvs: 06952FC175 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(979002)(39860400002)(366004)(396003)(346002)(39380400002)(376002)(13464003)(189003)(199004)(46003)(45080400002)(478600001)(2900100001)(5250100002)(33656002)(86362001)(3280700002)(7736002)(446003)(106356001)(105586002)(2906002)(11346002)(476003)(6436002)(486006)(3660700001)(305945005)(55016002)(74316002)(68736007)(8936002)(8676002)(81156014)(81166006)(229853002)(5660300001)(6116002)(99286004)(76176011)(186003)(102836004)(6506007)(53546011)(7696005)(59450400001)(6246003)(25786009)(53936002)(4326008)(6306002)(9686003)(97736004)(15760500003)(966005)(93886005)(14454004)(316002)(110136005)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR12MB1782; H:CY4PR12MB1815.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Cw4Fwy3Tp32v+z/TBjZvN46hKQFOg/wqAF68CyexnDLnufd42wEeJKDMggdz+sJ4VUMA4IVA6fCs1KlHoOzXN4EvZF4FwkWwiYKIW/jUKdeShda11PYhVImtsQnGiBuCZQ8IrvhcppxkTeThNiTjLX3ZlOvkIb2aKytdQZa9BQ3T3GGEEFvhht8dV7DW9fwh spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: bbfba9c7-4c08-4fcb-63a6-08d5cb4987bf X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bbfba9c7-4c08-4fcb-63a6-08d5cb4987bf X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jun 2018 01:05:01.2530 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1782 Subject: Re: [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jun 2018 01:05:03 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Star, I came across a 16550 model (simulation) which required clearing IER, and i= t seems that's allowed in the 16650 spec, as noted here: http://www.ti.com/lit/ds/symlink/pc16550d.pdf 8.4.2 FIFO Polled Mode Operation With FCR0=3D1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART= in the FIFO Polled Mode of operation. Thanks, Leo. > -----Original Message----- > From: Zeng, Star [mailto:star.zeng@intel.com] > Sent: Tuesday, June 05, 2018 7:43 PM > To: Duran, Leo ; Dong, Eric > Cc: edk2-devel@lists.01.org; Zeng, Star > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > It will be better to have the information that may could be added into th= e > commit message. >=20 > 1. Did you meet real issue without this patch? > 2. what is the default value of IER in your case? >=20 >=20 > Thanks, > Star > -----Original Message----- > From: Duran, Leo [mailto:leo.duran@amd.com] > Sent: Wednesday, June 6, 2018 5:21 AM > To: Zeng, Star ; Dong, Eric > Cc: edk2-devel@lists.01.org > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Any updates on this patch? >=20 > Do you require to know my "default value of IER"? >=20 > Thanks, > Leo. >=20 > -----Original Message----- > From: edk2-devel On Behalf Of Duran, > Leo > Sent: Friday, May 25, 2018 8:38 AM > To: Zeng, Star ; edk2-devel@lists.01.org > Cc: Dong, Eric ; Zeng, Star > Subject: Re: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Don''t have access to test platform at this time. > But will report IER value if I,m able to. >=20 > Leo >=20 > Get Outlook for iOS > ________________________________ > From: Zeng, Star > Sent: Friday, May 25, 2018 6:13:16 AM > To: Duran, Leo; edk2-devel@lists.01.org > Cc: Dong, Eric; Zeng, Star > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Reviewed-by: Star Zeng >=20 > Just a little curious about > 1. Did you meet real issue without this patch? > 2. what is the default value of IER in your case? >=20 >=20 > Thanks, > Star > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Leo Duran > Sent: Friday, May 25, 2018 3:08 AM > To: edk2-devel@lists.01.org > Cc: Dong, Eric ; Zeng, Star > Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Put the UART in FIFO Polled Mode by clearing IER after setting FCR. > Also, add comments to show DLAB state for registers 0 and 1. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leo Duran > Cc: Star Zeng > CC: Eric Dong > --- > .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++= ++-- > -- > 1 file changed, 12 insertions(+), 4 deletions(-) >=20 > diff --git > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > index 0ccac96..6532c4d 100644 > --- > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > +++ > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550 > +++ .c > @@ -3,6 +3,8 @@ >=20 > (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
> Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2018, AMD Incorporated. All rights reserved.
> + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at @@ -30,10 +32,11 @@ // // 16550 UART register offsets and > bitfields // > -#define R_UART_RXBUF 0 > -#define R_UART_TXBUF 0 > -#define R_UART_BAUD_LOW 0 > -#define R_UART_BAUD_HIGH 1 > +#define R_UART_RXBUF 0 // LCR_DLAB =3D 0 > +#define R_UART_TXBUF 0 // LCR_DLAB =3D 0 > +#define R_UART_BAUD_LOW 0 // LCR_DLAB =3D 1 > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB =3D 1 > +#define R_UART_IER 1 // LCR_DLAB =3D 0 > #define R_UART_FCR 2 > #define B_UART_FCR_FIFOE BIT0 > #define B_UART_FCR_FIFO64 BIT5 > @@ -554,6 +557,11 @@ SerialPortInitialize ( > SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, > (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | > B_UART_FCR_FIFO64))); >=20 > // > + // Set FIFO Polled Mode by clearing IER after setting FCR // > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); > + > + // > // Put Modem Control Register(MCR) into its reset state of 0x00. > // > SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel