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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Don''t have access to test platform at this time. But will report IER value if I,m able to. Leo Get Outlook for iOS ________________________________ From: Zeng, Star Sent: Friday, May 25, 2018 6:13:16 AM To: Duran, Leo; edk2-devel@lists.01.org Cc: Dong, Eric; Zeng, Star Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: En= sure FIFO Polled Mode Reviewed-by: Star Zeng Just a little curious about 1. Did you meet real issue without this patch? 2. what is the default value of IER in your case? Thanks, Star -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Leo = Duran Sent: Friday, May 25, 2018 3:08 AM To: edk2-devel@lists.01.org Cc: Dong, Eric ; Zeng, Star Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure= FIFO Polled Mode Put the UART in FIFO Polled Mode by clearing IER after setting FCR. Also, add comments to show DLAB state for registers 0 and 1. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran Cc: Star Zeng CC: Eric Dong --- .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++++= ---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib1= 6550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550= .c index 0ccac96..6532c4d 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -3,6 +3,8 @@ (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2018, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -30,10 +32,11 @@ // // 16550 UART register offsets and bitfields // -#define R_UART_RXBUF 0 -#define R_UART_TXBUF 0 -#define R_UART_BAUD_LOW 0 -#define R_UART_BAUD_HIGH 1 +#define R_UART_RXBUF 0 // LCR_DLAB =3D 0 +#define R_UART_TXBUF 0 // LCR_DLAB =3D 0 +#define R_UART_BAUD_LOW 0 // LCR_DLAB =3D 1 +#define R_UART_BAUD_HIGH 1 // LCR_DLAB =3D 1 +#define R_UART_IER 1 // LCR_DLAB =3D 0 #define R_UART_FCR 2 #define B_UART_FCR_FIFOE BIT0 #define B_UART_FCR_FIFO64 BIT5 @@ -554,6 +557,11 @@ SerialPortInitialize ( SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8= (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); // + // Set FIFO Polled Mode by clearing IER after setting FCR + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); + + // // Put Modem Control Register(MCR) into its reset state of 0x00. // SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel