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Fri, 10 Apr 2020 23:37:48 +0000 Received: from CY4PR21MB0743.namprd21.prod.outlook.com ([fe80::90d:10d9:c5bc:5318]) by CY4PR21MB0743.namprd21.prod.outlook.com ([fe80::90d:10d9:c5bc:5318%12]) with mapi id 15.20.2921.009; Fri, 10 Apr 2020 23:37:48 +0000 From: "Bret Barkelew" To: "devel@edk2.groups.io" , "michael.kubacki@outlook.com" CC: Dandan Bi , Hao A Wu , Jian J Wang , Liming Gao , Ray Ni , Sean Brogan Subject: Re: [EXTERNAL] [edk2-devel] [PATCH v2 4/7] MdeModulePkg/XhciDxe: Use BaseLib linked list iteration macros Thread-Topic: [EXTERNAL] [edk2-devel] [PATCH v2 4/7] MdeModulePkg/XhciDxe: Use BaseLib linked list iteration macros Thread-Index: AQHWD3MF/Keg8/qX2U29CN5LCyNkr6hzAyDe Date: Fri, 10 Apr 2020 23:37:48 +0000 Message-ID: References: <20200410200218.24992-1-michael.kubacki@outlook.com>, In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Enabled=True;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SiteId=72f988bf-86f1-41af-91ab-2d7cd011db47;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SetDate=2020-04-10T23:37:35.0449179Z;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ContentBits=0;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Method=Privileged authentication-results: spf=none (sender IP is ) smtp.mailfrom=Bret.Barkelew@microsoft.com; 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boundary="_000_CY4PR21MB0743A6C9A6CE9D284BA80482EFDE0CY4PR21MB0743namp_" --_000_CY4PR21MB0743A6C9A6CE9D284BA80482EFDE0CY4PR21MB0743namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Bret Barkelew - Bret ________________________________ From: devel@edk2.groups.io on behalf of Michael Kub= acki via groups.io Sent: Friday, April 10, 2020 1:02:15 PM To: devel@edk2.groups.io Cc: Dandan Bi ; Hao A Wu ; Jian J= Wang ; Liming Gao ; Ray Ni ; Sean Brogan Subject: [EXTERNAL] [edk2-devel] [PATCH v2 4/7] MdeModulePkg/XhciDxe: Use = BaseLib linked list iteration macros From: Michael Kubacki REF:https://nam06.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fbu= gzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D1959&data=3D02%7C01%7CBret.B= arkelew%40microsoft.com%7C213b2a4ed0f945b3198d08d7dd8a26c6%7C72f988bf86f141= af91ab2d7cd011db47%7C1%7C0%7C637221457736485446&sdata=3D7GPq6ea%2Bhkt7a= 1swJftfbaO4M1yeCG4PN2pjx10vZHs%3D&reserved=3D0 Replaces usage of the linked list iteration macros defined in Xhci.h with the common definition in BaseLib.h. Cc: Dandan Bi Cc: Hao A Wu Cc: Jian J Wang Cc: Liming Gao Cc: Ray Ni Cc: Sean Brogan Signed-off-by: Michael Kubacki Reviewed-by: Guomin Jiang Reviewed-by: Hao A Wu --- MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 9 +++++---- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h | 9 +-------- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/P= ci/XhciDxe/XhciSched.c index c0c374fc4758..ab8957c546ee 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -3,6 +3,7 @@ XHCI transfer scheduling routines. Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -1051,7 +1052,7 @@ IsAsyncIntTrb ( LIST_ENTRY *Next; URB *CheckedUrb; - EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { + BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { CheckedUrb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList); if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) { *Urb =3D CheckedUrb; @@ -1346,7 +1347,7 @@ XhciDelAsyncIntTransfer ( Urb =3D NULL; - EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { + BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { Urb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList); if ((Urb->Ep.BusAddr =3D=3D BusAddr) && (Urb->Ep.EpAddr =3D=3D EpNum) && @@ -1386,7 +1387,7 @@ XhciDelAllAsyncIntTransfers ( URB *Urb; EFI_STATUS Status; - EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { + BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { Urb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList); // @@ -1578,7 +1579,7 @@ XhcMonitorAsyncRequests ( Xhc =3D (USB_XHCI_INSTANCE*) Context; - EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { + BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { Urb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList); // diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/Xh= ciDxe/Xhci.h index 72b4e084f14d..3285eb8798c0 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h @@ -3,6 +3,7 @@ Provides some data structure definitions used by the XHCI host controll= er driver. Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -82,14 +83,6 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; #define INT_INTER 3 #define INT_INTER_ASYNC 4 -// -// Iterate through the double linked list. This is delete-safe. -// Don't touch NextEntry -// -#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \ - for (Entry =3D (ListHead)->ForwardLink, NextEntry =3D Entry->ForwardLin= k;\ - Entry !=3D (ListHead); Entry =3D NextEntry, NextEntry =3D Entry->Fo= rwardLink) - #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field= ) #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFF= FFFFFF)) -- 2.16.3.windows.1 --_000_CY4PR21MB0743A6C9A6CE9D284BA80482EFDE0CY4PR21MB0743namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Reviewed-by: Bret Barkelew <bret.barkelew@micros= oft.com>

 

- Bret

 

From: devel@edk2.groups.io= <devel@edk2.groups.io> on behalf of Michael Kubacki via groups.io &l= t;michael.kubacki=3Doutlook.com@groups.io>
Sent: Friday, April 10, 2020 1:02:15 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Dandan Bi <dandan.bi@intel.com>; Hao A Wu <hao.a.wu@in= tel.com>; Jian J Wang <jian.j.wang@intel.com>; Liming Gao <limi= ng.gao@intel.com>; Ray Ni <ray.ni@intel.com>; Sean Brogan <sean= .brogan@microsoft.com>
Subject: [EXTERNAL] [edk2-devel] [PATCH v2 4/7] MdeModulePkg/XhciDx= e: Use BaseLib linked list iteration macros
 
From: Michael Kubacki <michael.kubacki@microso= ft.com>

REF:https://nam06.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fbu= gzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D1959&amp;data=3D02%7C01%7CBr= et.Barkelew%40microsoft.com%7C213b2a4ed0f945b3198d08d7dd8a26c6%7C72f988bf86= f141af91ab2d7cd011db47%7C1%7C0%7C637221457736485446&amp;sdata=3D7GPq6ea= %2Bhkt7a1swJftfbaO4M1yeCG4PN2pjx10vZHs%3D&amp;reserved=3D0

Replaces usage of the linked list iteration macros defined in Xhci.h
with the common definition in BaseLib.h.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Guomin Jiang <guomin.jiang@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
---
 MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 9 ++++= 3;----
 MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h      | = 9 +--------
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/P= ci/XhciDxe/XhciSched.c
index c0c374fc4758..ab8957c546ee 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -3,6 +3,7 @@
   XHCI transfer scheduling routines.
 
 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.&l= t;BR>
+Copyright (c) Microsoft Corporation.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -1051,7 +1052,7 @@ IsAsyncIntTrb (
   LIST_ENTRY        &nb= sp;     *Next;
   URB         &nbs= p;           *CheckedUrb;=
 
-  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfer= s) {
+  BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTra= nsfers) {
     CheckedUrb =3D EFI_LIST_CONTAINER (Entry, URB, Ur= bList);
     if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {        *Urb =3D CheckedUrb;
@@ -1346,7 +1347,7 @@ XhciDelAsyncIntTransfer (
 
   Urb =3D NULL;
 
-  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfer= s) {
+  BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTra= nsfers) {
     Urb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList);=
     if ((Urb->Ep.BusAddr =3D=3D BusAddr) &&= ;
         (Urb->Ep.EpAddr =3D=3D= EpNum) &&
@@ -1386,7 +1387,7 @@ XhciDelAllAsyncIntTransfers (
   URB         &nbs= p;           *Urb;
   EFI_STATUS        &nb= sp;     Status;
 
-  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfer= s) {
+  BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTra= nsfers) {
     Urb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList);=
 
     //
@@ -1578,7 +1579,7 @@ XhcMonitorAsyncRequests (
 
   Xhc    =3D (USB_XHCI_INSTANCE*) Context;
 
-  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfer= s) {
+  BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTra= nsfers) {
     Urb =3D EFI_LIST_CONTAINER (Entry, URB, UrbList);=
 
     //
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/Xh= ciDxe/Xhci.h
index 72b4e084f14d..3285eb8798c0 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
@@ -3,6 +3,7 @@
   Provides some data structure definitions used by the XHCI hos= t controller driver.
 
 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.&l= t;BR>
+Copyright (c) Microsoft Corporation.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -82,14 +83,6 @@ typedef struct _USB_DEV_CONTEXT   &n= bsp;  USB_DEV_CONTEXT;
 #define INT_INTER        &nb= sp;           3
 #define INT_INTER_ASYNC       &nb= sp;      4
 
-//
-// Iterate through the double linked list. This is delete-safe.
-// Don't touch NextEntry
-//
-#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \
-  for (Entry =3D (ListHead)->ForwardLink, NextEntry =3D Entry->= ;ForwardLink;\
-      Entry !=3D (ListHead); Entry =3D NextEntry= , NextEntry =3D Entry->ForwardLink)
-
 #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, = Field)
 
 #define XHC_LOW_32BIT(Addr64)      &nb= sp;   ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
--
2.16.3.windows.1




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