From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=yunshan.tu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BF19D2112946C for ; Tue, 11 Sep 2018 19:40:11 -0700 (PDT) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Sep 2018 19:40:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,362,1531810800"; d="dat'59?scan'59,208,59";a="90891062" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga002.jf.intel.com with ESMTP; 11 Sep 2018 19:39:08 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 11 Sep 2018 19:39:07 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.205]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.143]) with mapi id 14.03.0319.002; Wed, 12 Sep 2018 10:39:05 +0800 From: "Tu, Yunshan" To: "edk2-devel@lists.01.org" Thread-Topic: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fixed the klocwork issues. Thread-Index: AdRKQcLo+CTxd62ESTud7XXYDFEq5w== Date: Wed, 12 Sep 2018 02:39:04 +0000 Message-ID: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjFiN2U4MTMtMjFiYS00ZmEzLTk3ZWQtNTBkNmY1ZjE3ODEzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiV2RwVmlqdzNtNkZxUjNwXC9rdHVHVWJRbktEZG14WlZzN0dRRDdKcE5PZFJJaitZTmowOVdLTXZEbFwvaEJ6dDluIn0= dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fixed the klocwork issues. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Sep 2018 02:40:12 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunshan Tu --- .../Common/Features/UsbDeviceDxe/XdciDWC.c | 12 ++++++------ .../PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c | 1 + .../PlatformBootManagerLib/PlatformBootManager.c | 2 ++ .../PlatformSettings/PlatformDxe/PciDevice.c | 2 +- .../PlatformPreMemPei/BootMode.c | 7 ------- .../PlatformPreMemPei/FvCallback.c | 2 +- .../Common/PlatformSmm/Platform.c | 2 +- .../FspmWrapperPeim/FspmWrapperPeim.c | 3 ++- .../NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c | 4 ++-- .../Cpu/PowerManagement/Smm/PowerMgmtDts.c | 16 ++++++++-------- .../Cpu/SmmAccess/Dxe/SmmAccessDriver.c | 6 +++--- .../Cpu/SmmAccess/Pei/SmmAccessDriver.c | 4 ++-- .../BaseConfigBlockLib/BaseConfigBlockLib.c | 4 ++-- .../Library/DxeSmbiosMemoryLib/SmbiosType16.c | 4 ++-- .../Universal/Variable/RuntimeDxe/Variable.c | 4 ++-- .../Library/BaseScSpiCommonLib/SpiCommon.c | 2 +- .../SouthCluster/Library/DxeVtdLib/DxeVtdLib.c | 1 + .../Library/Private/DxeScHdaLib/ScHdaLib.c | 4 +++- .../ScPciExpressHelpersLibrary.c | 4 ++-- .../Library/ScPlatformLib/ScPlatformLibrary.c | 2 +- .../BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c | 8 ++++---- .../BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c | 2 +- 22 files changed, 48 insertions(+), 48 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciD= WC.c b/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c index 2c1e929ab7..2ade4434bd 100644 --- a/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c +++ b/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c @@ -22,7 +22,7 @@ UsbRegRead ( IN UINT32 Offset ) { - volatile UINT32 *addr =3D (volatile UINT32 *)(UINTN)(Base + Offset); + volatile UINT32 *addr =3D (volatile UINT32 *)((UINTN)(Base) + (UINTN)(Of= fset)); return *addr; } =20 @@ -33,7 +33,7 @@ UsbRegWrite ( IN UINT32 val ) { - volatile UINT32 *addr =3D (volatile UINT32 *)(UINTN)(Base + Offset); + volatile UINT32 *addr =3D (volatile UINT32 *)((UINTN)(Base) + (UINTN)(Of= fset)); *addr =3D val; } =20 @@ -1852,9 +1852,9 @@ DwcXdciCoreInit ( // // Prepare a Buffer for SETUP packet // - LocalCoreHandle->Trbs =3D (DWC_XDCI_TRB *)(UINTN)((UINT32)(UINTN) + LocalCoreHandle->Trbs =3D (DWC_XDCI_TRB *)((UINTN) LocalCoreHandle->UnalignedTrbs + - (DWC_XDCI_TRB_BYTE_ALIGNMENT - + (UINTN)(DWC_XDCI_TRB_BYTE_ALIGNMENT - ((UINT32)(UINTN)LocalCoreHandle->UnalignedTrbs= % DWC_XDCI_TRB_BYTE_ALIGNMENT))); =20 @@ -3954,9 +3954,9 @@ UsbXdciCoreReinit ( // // Prepare a Buffer for SETUP packet // - LocalCoreHandle->Trbs =3D (DWC_XDCI_TRB *)(UINTN)((UINT32)(UINTN) + LocalCoreHandle->Trbs =3D (DWC_XDCI_TRB *)((UINTN) LocalCoreHandle->UnalignedTrbs + - (DWC_XDCI_TRB_BYTE_ALIGNMENT - + (UINTN)(DWC_XDCI_TRB_BYTE_ALIGNMENT - ((UINT32)(UINTN)LocalCoreHandle->UnalignedTrbs= % DWC_XDCI_TRB_BYTE_ALIGNMENT))); =20 diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib= /PeiFspCpuPolicyInitLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiF= spPolicyInitLib/PeiFspCpuPolicyInitLib.c index c404116029..7bf54ca37d 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= CpuPolicyInitLib.c +++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= CpuPolicyInitLib.c @@ -89,6 +89,7 @@ PeiFspCpuPolicyInit ( =20 VariableSize =3D sizeof (SYSTEM_CONFIGURATION); SystemConfiguration =3D AllocateZeroPool (VariableSize); + ASSERT (SystemConfiguration !=3D NULL); =20 Status =3D VariableServices->GetVariable ( VariableServices, diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManager= Lib/PlatformBootManager.c b/Platform/BroxtonPlatformPkg/Common/Library/Plat= formBootManagerLib/PlatformBootManager.c index 5201ac080d..821ed95bc4 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/Pla= tformBootManager.c +++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/Pla= tformBootManager.c @@ -524,6 +524,8 @@ ProcessTcgPp ( EFI_TCG2_PHYSICAL_PRESENCE Tcg2PpData; EFI_PHYSICAL_PRESENCE TcgPpData; UINTN TcgPpDataSize; + =20 + Status =3D EFI_SUCCESS; =20 TcgPpData.PPRequest =3D TCG_PHYSICAL_PRESENCE_NO_ACTION; Tcg2PpData.PPRequest =3D TCG2_PHYSICAL_PRESENCE_NO_ACTION; diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDx= e/PciDevice.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Platfor= mDxe/PciDevice.c index 8c1c621e0b..296638d865 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDe= vice.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDe= vice.c @@ -443,7 +443,7 @@ PciBusEvent ( &Supports ); =20 - Supports &=3D EFI_PCI_DEVICE_ENABLE; + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; // // Work around start, PMC command register IO enable(BIT0) will alwa= ys read back as 0, though it supports IO // so the attributes for IO will not be set, here we set it diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPr= eMemPei/BootMode.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pl= atformPreMemPei/BootMode.c index c113097e55..a4182bbb1b 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /BootMode.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /BootMode.c @@ -424,13 +424,6 @@ SetPlatformBootMode ( CopyMem (&PlatformSetupId.SetupName, SAFE_SETUP_NAME, StrSize (SAFE_SE= TUP_NAME)); PlatformSetupId.PlatformBootMode =3D PLATFORM_SAFE_MODE; =20 - } else if (0) { - // - // Manufacturing mode - // - CopyMem (&PlatformSetupId.SetupName, MANUFACTURE_SETUP_NAME, StrSize (= MANUFACTURE_SETUP_NAME)); - PlatformSetupId.PlatformBootMode =3D PLATFORM_MANUFACTURING_MODE; - } else { // // Default to normal mode. diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPr= eMemPei/FvCallback.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/= PlatformPreMemPei/FvCallback.c index d5f514a6f4..02cda154b8 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /FvCallback.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /FvCallback.c @@ -158,7 +158,7 @@ CreateVariableHobs ( return EFI_INVALID_PARAMETER; } =20 - VariableStoreBase =3D (EFI_PHYSICAL_ADDRESS) ((UINTN) NvStorageFvHeade= r + (UINTN)NvStorageFvHeader->HeaderLength); + VariableStoreBase =3D (EFI_PHYSICAL_ADDRESS) ((UINTN) NvStorageFvHeade= r + (UINTN)(NvStorageFvHeader->HeaderLength)); VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) (UINTN) VariableStoreB= ase; =20 DEBUG ((EFI_D_INFO, " VariableStoreHeader at 0x%x. VariableStoreSize = =3D %d\n", VariableStoreHeader, (UINTN) VariableStoreHeader->Size)); diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c b/Pl= atform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c index 15014b020e..eccc2a67a5 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c @@ -556,7 +556,7 @@ CpuSmmSxWorkAround( // If C State enabled, disable it before going into S3 // The MSR will be restored back during S3 wake // - MsrValue &=3D ~B_EFI_MSR_PMG_CST_CONFIG_IO_MWAIT_REDIRECTION_ENABLE; + MsrValue &=3D ~((UINT64)B_EFI_MSR_PMG_CST_CONFIG_IO_MWAIT_REDIRECTION_= ENABLE); AsmWriteMsr64 (EFI_MSR_PMG_CST_CONFIG, MsrValue); } } diff --git a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2Wrapper= Pkg/FspmWrapperPeim/FspmWrapperPeim.c b/Platform/BroxtonPlatformPkg/Common/= SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c index f403d1e214..9162fde9d1 100644 --- a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/Fsp= mWrapperPeim/FspmWrapperPeim.c +++ b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/Fsp= mWrapperPeim/FspmWrapperPeim.c @@ -111,7 +111,7 @@ PeiFspMemoryInit ( DEBUG ((DEBUG_INFO, "PcdFspmBaseAddress =3D 0x%X\n", PcdGet32 (PcdFspmBa= seAddress))); DEBUG ((DEBUG_INFO, "FspmHeaderPtr =3D 0x%X\n", FspmHeaderPtr)); DEBUG ((DEBUG_INFO, "FspmHeaderPtr->CfgRegionSize =3D 0x%X\n", FspmHeade= rPtr->CfgRegionSize)); - + ASSERT (FspmHeaderPtr !=3D NULL); FspmUpdDataPtr =3D (FSPM_UPD *) AllocateZeroPool ((UINTN) FspmHeaderPtr-= >CfgRegionSize); ASSERT (FspmUpdDataPtr !=3D NULL); SourceData =3D (UINTN *) ((UINTN) FspmHeaderPtr->ImageBase + (UINTN) Fsp= mHeaderPtr->CfgRegionOffset); @@ -119,6 +119,7 @@ PeiFspMemoryInit ( =20 DEBUG ((DEBUG_INFO, "FspWrapperPlatformInitPreMem enter\n")); FspmUpdDataPtr =3D UpdateFspUpdConfigs (PeiServices, FspmUpdDataPtr); + ASSERT (FspmUpdDataPtr !=3D NULL); FspPolicyInitPreMem (FspmUpdDataPtr); =20 DEBUG ((DEBUG_INFO, " NvsBufferPtr - 0x%x\n", FspmUpdDataPtr->Fs= pmArchUpd.NvsBufferPtr)); diff --git a/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiP= xeBcDxe/PxeBcImpl.c b/Platform/BroxtonPlatformPkg/Common/SampleCode/Network= Pkg/UefiPxeBcDxe/PxeBcImpl.c index 8be6d2f8ab..f9f90630fa 100644 --- a/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe= /PxeBcImpl.c +++ b/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe= /PxeBcImpl.c @@ -95,8 +95,8 @@ EfiPxeBcStart ( // // Configure block size for TFTP as a default value to handle all link= layers. // - Private->BlockSize =3D (UINTN) (Private->Ip6MaxPacketSize - - PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE); + Private->BlockSize =3D (UINTN)(Private->Ip6MaxPacketSize) - + (UINTN)(PXEBC_DEFAULT_UDP_OVERHEAD_SIZE) - (UIN= TN)(PXEBC_DEFAULT_TFTP_OVERHEAD_SIZE); =20 // // PXE over IPv6 starts here, initialize the fields and list header. diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerM= gmtDts.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgm= tDts.c index 7a2bb7f76b..d46b29b108 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtDts.= c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtDts.= c @@ -554,9 +554,9 @@ PackageDigitalThermalSensorEnable ( // MsrData.Qword =3D AsmReadMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS); if (mDtsValue !=3D DTS_OUT_OF_SPEC_ONLY) { - MsrData.Qword &=3D ~THERM_STATUS_LOG_MASK; + MsrData.Qword &=3D ~((UINT64)THERM_STATUS_LOG_MASK); } else { - MsrData.Qword &=3D ~B_OUT_OF_SPEC_STATUS_LOG; + MsrData.Qword &=3D ~((UINT64)B_OUT_OF_SPEC_STATUS_LOG); } =20 AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS, MsrData.Qword); @@ -570,7 +570,7 @@ PackageDigitalThermalSensorEnable ( // Only lock interrupts if in CMP mode // if (gSmst->NumberOfCpus > 1) { - MsrData.Qword |=3D B_LOCK_THERMAL_INT; + MsrData.Qword |=3D ((UINT64)B_LOCK_THERMAL_INT); } =20 AsmWriteMsr64 (EFI_MSR_MISC_PWR_MGMT, MsrData.Qword); @@ -811,7 +811,7 @@ PackageDigitalThermalSensorSetOutOfSpecInterrupt ( // Enable Out Of Spec interrupt // MsrData.Qword =3D AsmReadMsr64 (EFI_MSR_IA32_PACKAGE_THERM_INTERRUPT); - MsrData.Qword |=3D OVERHEAT_INTERRUPT_ENABLE; + MsrData.Qword |=3D ((UINT64)OVERHEAT_INTERRUPT_ENABLE); AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_INTERRUPT, MsrData.Qword); =20 return EFI_SUCCESS; @@ -970,8 +970,8 @@ PackageDigitalThermalSensorSetThreshold ( // // Enable interrupts // - MsrData.Qword |=3D TH1_ENABLE; - MsrData.Qword |=3D TH2_ENABLE; + MsrData.Qword |=3D ((UINT64)TH1_ENABLE); + MsrData.Qword |=3D ((UINT64)TH2_ENABLE); =20 // // If the high temp is at TjMax (offset =3D=3D 0) @@ -979,7 +979,7 @@ PackageDigitalThermalSensorSetThreshold ( // causing many threshold crossings // if (MsrData.Bytes.SecondByte =3D=3D 0x80) { - MsrData.Qword &=3D ~TH1_ENABLE; + MsrData.Qword &=3D ~((UINT64)TH1_ENABLE); } =20 AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_INTERRUPT, MsrData.Qword); @@ -989,7 +989,7 @@ PackageDigitalThermalSensorSetThreshold ( // Clear the threshold log bits // MsrData.Qword =3D AsmReadMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS); - MsrData.Qword &=3D ~THERM_STATUS_THRESHOLD_LOG_MASK; + MsrData.Qword &=3D ~((UINT64)THERM_STATUS_THRESHOLD_LOG_MASK); AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS, MsrData.Qword); =20 return EFI_SUCCESS; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDri= ver.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c index 33b302731c..7edbf1e9a0 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c @@ -139,8 +139,8 @@ Open ( =20 Mmio64AndThenOr (MCH_BASE_ADDRESS, 0x6848, 0, 0xFF); =20 - SmmAccess->SmramDesc[Index].RegionState &=3D ~(EFI_SMRAM_CLOSED |EFI_A= LLOCATED); - SmmAccess->SmramDesc[Index].RegionState |=3D EFI_SMRAM_OPEN; + SmmAccess->SmramDesc[Index].RegionState &=3D ~((UINT64)(EFI_SMRAM_CLOS= ED |EFI_ALLOCATED)); + SmmAccess->SmramDesc[Index].RegionState |=3D (UINT64)(EFI_SMRAM_OPEN); } SmmAccess->SmmAccess.OpenState =3D TRUE; =20 @@ -181,7 +181,7 @@ Close ( continue; } =20 - SmmAccess->SmramDesc[Index].RegionState &=3D ~EFI_SMRAM_OPEN; + SmmAccess->SmramDesc[Index].RegionState &=3D ~((UINT64)(EFI_SMRAM_OPEN= )); SmmAccess->SmramDesc[Index].RegionState |=3D (UINTN)(EFI_SMRAM_CLOSED = |EFI_ALLOCATED); } SmmAccess->SmmAccess.OpenState =3D FALSE; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDri= ver.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c index 39a77f401e..0d83157261 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c @@ -147,7 +147,7 @@ Open ( // END CHIPSET SPECIFIC CODE // SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINTN) (~(EFI_SM= RAM_CLOSED | EFI_ALLOCATED)); - SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D EFI_SMRAM_OPEN; + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT64)(EFI_SMRA= M_OPEN); SmmAccess->SmmAccess.OpenState =3D TRUE; =20 return EFI_SUCCESS; @@ -190,7 +190,7 @@ Close ( return EFI_DEVICE_ERROR; } =20 - SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D ~EFI_SMRAM_OPEN; + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D ~((UINT64)EFI_SMR= AM_OPEN); SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINTN)(EFI_SMRAM= _CLOSED | EFI_ALLOCATED); =20 SmmAccess->SmmAccess.OpenState =3D FALSE; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/Bas= eConfigBlockLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlock= Lib/BaseConfigBlockLib.c index 3e089bf4c4..c4d7b3b619 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfig= BlockLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfig= BlockLib.c @@ -136,7 +136,7 @@ AddConfigBlock ( if (OffsetIndex =3D=3D 0) { LastUsedOffset =3D 0; } else { - LastUsedOffsetPtr =3D (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr + Config= BlkTblHdrSize + (UINTN) ((OffsetIndex - 1) * 4)); + LastUsedOffsetPtr =3D (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr + Config= BlkTblHdrSize + ((((UINTN)OffsetIndex) - 1) * 4)); LastUsedOffset =3D (UINT32) *LastUsedOffsetPtr; } *OffsetTblPtr =3D LastUsedOffset + ConfigBlkSize; @@ -144,7 +144,7 @@ AddConfigBlock ( ConfigBlkTblAddrPtr->AvailableBlocks--; ConfigBlkTblAddrPtr->AvailableSize =3D ConfigBlkTblAddrPtr->AvailableSiz= e - ConfigBlkSize; =20 - TempConfigBlk =3D (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN= ) ConfigBlkTblHdrSize + (UINTN) (NumOfBlocks * 4) + (UINTN) LastUsedOffset)= ; + TempConfigBlk =3D (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN= ) ConfigBlkTblHdrSize + (((UINTN)NumOfBlocks) * 4) + (UINTN) LastUsedOffset= ); TempConfigBlk->Header.Size =3D ConfigBlkSize; TempConfigBlk->Header.Revision =3D ConfigBlkAddrPtr->Header.Revision; TempConfigBlk->Header.Guid =3D ConfigBlkAddrPtr->Header.Guid; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbios= MemoryLib/SmbiosType16.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Lib= rary/DxeSmbiosMemoryLib/SmbiosType16.c index 194df4494a..14c9697d37 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryL= ib/SmbiosType16.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryL= ib/SmbiosType16.c @@ -88,14 +88,14 @@ InstallSmbiosType16 ( } MaxSockets =3D ChannelASlotNum + ChannelBSlotNum; if (mMemInfoHob->MemInfoData.ddrType =3D=3D 0) { - if ((MAX_RANK_CAPACITY_DDR4 * SA_MC_MAX_SIDES * MaxSockets) < SMBIOS_T= YPE16_USE_EXTENDED_MAX_CAPACITY) { + if ((MAX_RANK_CAPACITY_DDR4 * SA_MC_MAX_SIDES * (UINT64)(MaxSockets)) = < SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) { SmbiosTableType16Data.MaximumCapacity =3D MAX_RANK_CAPACITY_DDR4 * S= A_MC_MAX_SIDES * MaxSockets; } else { SmbiosTableType16Data.MaximumCapacity =3D SMBIOS_TYPE16_USE_EXTENDED= _MAX_CAPACITY; SmbiosTableType16Data.ExtendedMaximumCapacity =3D ((UINT64) MAX_RANK= _CAPACITY_DDR4) * SA_MC_MAX_SIDES * MaxSockets * 1024; // Convert from KB t= o Byte } } else { - if ((MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * MaxSockets) < SMBIOS_TYPE16= _USE_EXTENDED_MAX_CAPACITY) { + if ((MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * (UINT64)(MaxSockets)) < SMB= IOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) { SmbiosTableType16Data.MaximumCapacity =3D MAX_RANK_CAPACITY * SA_MC_= MAX_SIDES * MaxSockets; } else { SmbiosTableType16Data.MaximumCapacity =3D SMBIOS_TYPE16_USE_EXTENDED= _MAX_CAPACITY; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Univer= sal/Variable/RuntimeDxe/Variable.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Sample= Code/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c index 63834426a0..02265c14dc 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Var= iable/RuntimeDxe/Variable.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Var= iable/RuntimeDxe/Variable.c @@ -1323,7 +1323,7 @@ Reclaim ( // Install the new variable if it is not NULL. // if (NewVariable !=3D NULL) { - if ((UINTN) (CurrPtr - ValidBuffer) + NewVariableSize > VariableStoreH= eader->Size) { + if ((UINTN) ((UINTN)(CurrPtr) - (UINTN)(ValidBuffer)) + NewVariableSiz= e > VariableStoreHeader->Size) { // // No enough space to store the new variable. // @@ -1419,7 +1419,7 @@ Reclaim ( // If volatile variable store, just copy valid buffer. // SetMem ((UINT8 *) (UINTN) VariableBase, VariableStoreHeader->Size, 0xf= f); - CopyMem ((UINT8 *) (UINTN) VariableBase, ValidBuffer, (UINTN) (CurrPtr= - ValidBuffer)); + CopyMem ((UINT8 *) (UINTN) VariableBase, ValidBuffer, ((UINTN)CurrPtr = - (UINTN)ValidBuffer)); Status =3D EFI_SUCCESS; } else { // diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpi= CommonLib/SpiCommon.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Librar= y/BaseScSpiCommonLib/SpiCommon.c index c1fa73d05c..d50c179e25 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonL= ib/SpiCommon.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonL= ib/SpiCommon.c @@ -626,7 +626,7 @@ SendSpiCmd ( // sources after the flash cycle . // SmiEnSave =3D IoRead32 ((UINTN)(UINT16)(ABase + R_SMI_EN)); - IoWrite32 ((UINTN) (UINT16) (ABase + R_SMI_EN), SmiEnSave & (UINT32) (~B= _SMI_EN_GBL_SMI)); + IoWrite32 ((UINTN)(((UINT16)ABase) + ((UINT16)R_SMI_EN)), SmiEnSave & (U= INT32) (~B_SMI_EN_GBL_SMI)); BiosCtlSave =3D MmioRead8 (SpiBaseAddress + R_SPI_BCR) & B_SPI_BCR_SRC; =20 // diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib= /DxeVtdLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdL= ib/DxeVtdLib.c index abcfee2998..bc9db39c8f 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtd= Lib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtd= Lib.c @@ -547,6 +547,7 @@ UpdateDmarOnReadyToBoot ( SC_VTD_CONFIG *VtdConfig; =20 AcpiTableProtocol =3D NULL; + FwVol =3D NULL; DmarAcpiTable =3D NULL; Index =3D 0; =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/D= xeScHdaLib/ScHdaLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Librar= y/Private/DxeScHdaLib/ScHdaLib.c index d05395eb49..7578eb1f86 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHda= Lib/ScHdaLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHda= Lib/ScHdaLib.c @@ -226,7 +226,9 @@ NhltEndpointDump ( DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.CapabilitiesSize =3D %d B= \n", Endpoint->EndpointConfig.CapabilitiesSize)); DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.Capabilities:")); for (i =3D 0; i < (Endpoint->EndpointConfig.CapabilitiesSize ) ; i++) { - if (i % 16 =3D=3D 0) DEBUG ((DEBUG_INFO, "\n")); + if (i % 16 =3D=3D 0) { + DEBUG ((DEBUG_INFO, "\n")); + } DEBUG ((DEBUG_INFO, "0x%02x, ", Endpoint->EndpointConfig.Capabilities[= i])); } =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/P= eiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c b/Silicon/Broxt= onSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelper= sLib/ScPciExpressHelpersLibrary.c index 44b62db3ff..6691b4d866 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSm= mScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSm= mScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c @@ -1648,7 +1648,7 @@ PcieCheckPmConfig ( Operation =3D CalculateAspm; } else { Operation =3D ManualAspm; - *AspmVal &=3D RootPortConfig->Aspm; + *AspmVal &=3D (UINT16)(RootPortConfig->Aspm); } =20 // @@ -1837,7 +1837,7 @@ PcieSetPm ( Operation =3D CalculateAspm; } else { Operation =3D ManualAspm; - AspmVal &=3D RootPortConfig->Aspm; + AspmVal &=3D (UINT16)(RootPortConfig->Aspm); } =20 // diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatfor= mLib/ScPlatformLibrary.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Lib= rary/ScPlatformLib/ScPlatformLibrary.c index e2018e61c3..83b66fe0e0 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/Sc= PlatformLibrary.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/Sc= PlatformLibrary.c @@ -115,7 +115,7 @@ ScPmTimerStall ( // one I/O operation, and maybe generate SMI // while ((Counts !=3D 0) || (RemainingTick > CurrentTick)) { - CurrentTick =3D IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_TMR)) & B= _ACPI_PM1_TMR_VAL; + CurrentTick =3D IoRead32 ((UINTN)(AcpiBaseAddr) + (UINTN)(R_ACPI_PM1_T= MR)) & B_ACPI_PM1_TMR_VAL; // // Check if timer overflow // diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c b/Silic= on/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c index a7fc7a4168..4f9f221df7 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c @@ -242,7 +242,7 @@ SetHeci2Active ( =20 DEBUG ((EFI_D_INFO, "SetHeci2Active: Setting HECI2 to active...\n")); =20 - HostControlReg =3D (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHec= i_HeciBar + H_CSR); + HostControlReg =3D (volatile HECI_HOST_CONTROL_REGISTER *) (((UINTN)mHec= i_HeciBar) + ((UINTN)H_CSR)); =20 while ((Mmio32 (mHeci_HeciBar, R_HECI_DEVIDLEC) & B_HECI_DEVIDLEC_CIP) = =3D=3D B_HECI_DEVIDLEC_CIP); =20 @@ -307,9 +307,9 @@ BOOLEAN HeciSendHandle ( if (mHeci_LeftSize =3D=3D 0) { return TRUE; } - HostControlReg =3D (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN) (mHe= ci_HeciBar + H_CSR); - SecControlReg =3D (volatile HECI_SEC_CONTROL_REGISTER *) (UINTN) (mHeci= _HeciBar + SEC_CSR_HA); - WriteBuffer =3D (UINT32 *) (UINTN) (mHeci_HeciBar + H_CB_WW); + HostControlReg =3D (volatile HECI_HOST_CONTROL_REGISTER *) (((UINTN)mHe= ci_HeciBar) + ((UINTN)H_CSR)); + SecControlReg =3D (volatile HECI_SEC_CONTROL_REGISTER *) (((UINTN)mHeci= _HeciBar) + ((UINTN)SEC_CSR_HA)); + WriteBuffer =3D (UINT32 *) (((UINTN)mHeci_HeciBar) + ((UINTN)H_CB_WW)); MessageBody =3D (UINT32*) mHeci_Message; =20 MaxBuffer =3D HostControlReg->r.H_CBD - 0x10; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.= c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c index 2f3d0badca..04f479e238 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c @@ -1172,7 +1172,7 @@ HeciSetSeCEnableMsg ( EFI_HECI_PROTOCOL *Heci; HECI_FWS_REGISTER SeCFirmwareStatus; UINTN HeciPciAddressBase; - UINT16 TimeOut; + UINT32 TimeOut; =20 TimeOut =3D 0; =20 --=20 2.18.0.windows.1