From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web12.4967.1663917631867799042 for ; Fri, 23 Sep 2022 00:20:32 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxkOA+Xi1jc4sgAA--.56818S2; Fri, 23 Sep 2022 15:20:30 +0800 (CST) Date: Fri, 23 Sep 2022 15:20:30 +0800 From: "Chao Li" To: Michael D Kinney , Liming Gao , Zhiguang Liu Cc: "=?utf-8?Q?devel=40edk2.groups.io?=" Message-ID: In-Reply-To: <20220914094138.3697222-1-lichao@loongson.cn> References: <20220914094138.3697222-1-lichao@loongson.cn> Subject: Re: [PATCH v2 27/34] MdePkg/BaseCpuLib: LoongArch Base CPU library implementation. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxkOA+Xi1jc4sgAA--.56818S2 X-Coremail-Antispam: 1UD129KBjvPXoW5Wr4fJw1DJrWDJr1UGryDp5X_AryUXoWj9r 4vvr4DAr1rCryFvrsrAr10qrsrKr4Yyr1Ig3WjkFyftF1DKa1DAw1DGr43XF15JayrK3yx X34jvFWxKF1xn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3AaLa J3UjIYCTnIWjp_UUUYM7k0a2IF6w1UM7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IE x4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84 x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IY x2IY6xkF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4 A2jsIEc7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG67k08I80 eVWUJVW8JwAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl5I8CrVAKz4kIr2xC04v26r4j6ryUMc Ij6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_ Jr0_Gr1lF7xvr2IYc2Ij64vIr41l7480Y4vEI4kI2Ix0rVAqx4xJMxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r106r1r MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07j7hL8UUUUU= X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQASCGMsUF0TtQAesh Content-Type: multipart/alternative; boundary="632d5e3e_52684f37_dbe1" --632d5e3e_52684f37_dbe1 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Mike, Liming and Zhiguang, This patch has not been reviewed, would you please review it=3F Thanks, Chao -------- On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5=8D=88, Chao Li wrote: > RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053 > > Implement LoongArch CPU related functions in BaseCpuLib. > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > > Signed-off-by: Chao Li > --- > MdePkg/Library/BaseCpuLib/BaseCpuLib.inf =7C 7 ++++++- > MdePkg/Library/BaseCpuLib/BaseCpuLib.uni =7C 5 +++-- > MdePkg/Library/BaseCpuLib/LoongArch/Cpu=46lushTlb.S =7C 15 ++++++++++++= +++ > MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S =7C 15 +++++++++++++++ > 4 files changed, 39 insertions(+), 3 deletions(-) > create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/Cpu=46lushTlb.S > create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S > > diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/= BaseCpuLib/BaseCpuLib.inf > index c4cd29a783..6b230f6e6d 100644 > --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > =40=40 -8,6 +8,7 =40=40 > =23 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.=
> > =23 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved. > =23 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All = rights reserved.
> +=23 Portions Copyright (c) 2022, Loongson Technology Corporation Limit= ed. All rights reserved.
> =23 > =23 SPDX-License-Identifier: BSD-2-Clause-Patent > =23 > =40=40 -25,7 +26,7 =40=40 > > > > =23 > -=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 > +=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOONGAR= CH64 > =23 > > > =5BSources.IA32=5D > =40=40 -61,6 +62,10 =40=40 > =5BSources.RISCV64=5D > > RiscV/Cpu.S > > > +=5BSources.LOONGARCH64=5D > + LoongArch/Cpu=46lushTlb.S =7C GCC > + LoongArch/CpuSleep.S =7C GCC > + > =5BPackages=5D > MdePkg/MdePkg.dec > > > diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/= BaseCpuLib/BaseCpuLib.uni > index 80dc495786..7c5c8dfb37 100644 > --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni > +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni > =40=40 -1,13 +1,14 =40=40 > // /** =40file > > // Instance of CPU Library for various architecture. > // > -// CPU Library implemented using ASM functions for IA-32, X64 and RISC= V64, > +// CPU Library implemented using ASM functions for IA-32, X64, RISCV64= and LoongArch64, > // PAL CALLs for IP=46, and empty functions for EBC. > // > // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved. > // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<= BR> > // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved. > // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All r= ights reserved.
> +// Portions Copyright (c) 2022, Loongson Technology Corporation Limite= d. All rights reserved.
> // > // SPDX-License-Identifier: BSD-2-Clause-Patent > // > =40=40 -16,5 +17,5 =40=40 > > =23string STR=5FMODULE=5FABSTRACT =23language en-US =22Instance of CPU = Library for various architectures=22 > > > -=23string STR=5FMODULE=5FDESCRIPTION =23language en-US =22CPU Library = implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for= IP=46, and empty functions for EBC.=22 > +=23string STR=5FMODULE=5FDESCRIPTION =23language en-US =22CPU Library = implemented using ASM functions for IA-32, X64, RISCV64 and LoongArch64, = PAL CALLs for IP=46, and empty functions for EBC.=22 > > > diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/Cpu=46lushTlb.S b/MdeP= kg/Library/BaseCpuLib/LoongArch/Cpu=46lushTlb.S > new file mode 100644 > index 0000000000..8b792f0a37 > --- /dev/null > +++ b/MdePkg/Library/BaseCpuLib/LoongArch/Cpu=46lushTlb.S > =40=40 -0,0 +1,15 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 Cpu=46lushTlb() for LoongArch64 > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > +ASM=5FGLOBAL ASM=5FP=46X(Cpu=46lushTlb) > + > +ASM=5FP=46X(Cpu=46lushTlb): > + tlbflush > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S b/MdePkg/Li= brary/BaseCpuLib/LoongArch/CpuSleep.S > new file mode 100644 > index 0000000000..eb31b10714 > --- /dev/null > +++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S > =40=40 -0,0 +1,15 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 CpuSleep() for LoongArch64 > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > +ASM=5FGLOBAL ASM=5FP=46X(CpuSleep) > + > +ASM=5FP=46X(CpuSleep): > + idle 0 > + jirl =24zero, =24ra, 0 > + .end > -- > 2.27.0 > --632d5e3e_52684f37_dbe1 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Mike, Liming and Zhiguang,
This patch has not been reviewed, would you= please review it=3F


Thanks,<= br>Chao
--------

On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5=8D=88,= Chao Li <lichao=40loongson.cn> wrote:
R= E=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053

=
Implement LoongArch CPU related functions in BaseCpuLib.

Cc: Michael D Kinney <michael.d.kinney=40intel.com>
Cc= : Liming Gao <gaoliming=40byosoft.com.cn>
Cc: Zhiguang Li= u <zhiguang.liu=40intel.com>

Signed-off-by: Chao Li &= lt;lichao=40loongson.cn>
---
MdePkg/Library/BaseCp= uLib/BaseCpuLib.inf =7C 7 ++++++-
MdePkg/Library/BaseCpuLib/Bas= eCpuLib.uni =7C 5 +++--
MdePkg/Library/BaseCpuLib/LoongArch/Cpu= =46lushTlb.S =7C 15 +++++++++++++++
MdePkg/Library/BaseCpuLib/L= oongArch/CpuSleep.S =7C 15 +++++++++++++++
4 files changed, 39 = insertions(+), 3 deletions(-)
create mode 100644 MdePkg/Library= /BaseCpuLib/LoongArch/Cpu=46lushTlb.S
create mode 100644 MdePkg= /Library/BaseCpuLib/LoongArch/CpuSleep.S

diff --git a/MdePk= g/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLi= b.inf
index c4cd29a783..6b230f6e6d 100644
--- a/MdePk= g/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCp= uLib/BaseCpuLib.inf
=40=40 -8,6 +8,7 =40=40
=23 Porti= ons copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR><= /div>
=23 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights= reserved.<BR>

=23 Copyright (c) 2020, Hewlett Packar= d Enterprise Development LP. All rights reserved.<BR>

+=23 Portions Copyright (c) 2022, Loongson Technology Corporation Limite= d. All rights reserved.<BR>

=23

=23 SPD= X-License-Identifier: BSD-2-Clause-Patent

=23

=40=40 -25,7 +26,7 =40=40



=23

-=23= VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64

+=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARC= H64
=23



=5BSources.IA32=5D

<= div>=40=40 -61,6 +62,10 =40=40
=5BSources.RISCV64=5D

<= div>RiscV/Cpu.S


+=5BSources.LOONGARCH64=5D
+ LoongArch/Cpu=46lushTlb.S =7C GCC

+ LoongArch/CpuSl= eep.S =7C GCC

+

=5BPackages=5D

= MdePkg/MdePkg.dec



diff --git a/MdePkg/Library/BaseC= puLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
index 80dc495786..7c5c8dfb37 100644
--- a/MdePkg/Library/BaseC= puLib/BaseCpuLib.uni
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib= .uni
=40=40 -1,13 +1,14 =40=40
// /** =40file
// Instance of CPU Library for various architecture.

//
-// CPU Library implemented using ASM functions for IA-= 32, X64 and RISCV64,

+// CPU Library implemented using ASM = functions for IA-32, X64, RISCV64 and LoongArch64,

// PAL C= ALLs for IP=46, and empty functions for EBC.

//

// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.&= lt;BR>
// Portions copyright (c) 2008 - 2009, Apple Inc.= All rights reserved.<BR>

// Portions copyright (c) 2= 011 - 2013, ARM Ltd. All rights reserved.<BR>

// Copy= right (c) 2020, Hewlett Packard Enterprise Development LP. All rights res= erved.<BR>

+// Portions Copyright (c) 2022, Loongson = Technology Corporation Limited. All rights reserved.<BR>

<= div>//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//

=40=40 -16,5 +17,5 =40=40


=23= string STR=5FMODULE=5FABSTRACT =23language en-US =22Instance of CPU Libra= ry for various architectures=22



-=23string STR=5FMO= DULE=5FDESCRIPTION =23language en-US =22CPU Library implemented using ASM= functions for IA-32, X64 and RISCV64, PAL CALLs for IP=46, and empty fun= ctions for EBC.=22

+=23string STR=5FMODULE=5FDESCRIPTION =23= language en-US =22CPU Library implemented using ASM functions for IA-32, = X64, RISCV64 and LoongArch64, PAL CALLs for IP=46, and empty functions fo= r EBC.=22



diff --git a/MdePkg/Library/BaseCpuLib/Lo= ongArch/Cpu=46lushTlb.S b/MdePkg/Library/BaseCpuLib/LoongArch/Cpu=46lushT= lb.S
new file mode 100644
index 0000000000..8b792f0a3= 7
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Loong= Arch/Cpu=46lushTlb.S
=40=40 -0,0 +1,15 =40=40
+=23---= -------------------------------------------------------------------------= --

+=23

+=23 Cpu=46lushTlb() for LoongArch64<= /div>
+=23

+=23 Copyright (c) 2022, Loongson Techno= logy Corporation Limited. All rights reserved.<BR>

+=23=

+=23 SPDX-License-Identifier: BSD-2-Clause-Patent
+=23

+=23--------------------------------------------= ----------------------------------

+ASM=5FGLOBAL ASM=5FP=46= X(Cpu=46lushTlb)

+

+ASM=5FP=46X(Cpu=46lushTlb= ):

+ tlbflush

+ jirl =24zero, =24ra, 0
<= br>
+ .end

diff --git a/MdePkg/Library/BaseCpuLib/Loong= Arch/CpuSleep.S b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
new file mode 100644
index 0000000000..eb31b10714
-= -- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep= .S
=40=40 -0,0 +1,15 =40=40
+=23---------------------= ---------------------------------------------------------

+= =23

+=23 CpuSleep() for LoongArch64

+=23
+=23 Copyright (c) 2022, Loongson Technology Corporation Limite= d. All rights reserved.<BR>

+=23

+=23 S= PDX-License-Identifier: BSD-2-Clause-Patent

+=23

<= div>+=23-----------------------------------------------------------------= -------------

+ASM=5FGLOBAL ASM=5FP=46X(CpuSleep)

=
+

+ASM=5FP=46X(CpuSleep):

+ idle 0
=
+ jirl =24zero, =24ra, 0

+ .end

--
2.27.0
--632d5e3e_52684f37_dbe1--