From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B34272095B09C for ; Thu, 12 Oct 2017 23:10:35 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2017 23:14:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,369,1503385200"; d="scan'208";a="909528924" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2017 23:14:06 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 12 Oct 2017 23:14:06 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 12 Oct 2017 23:14:06 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Fri, 13 Oct 2017 14:14:03 +0800 From: "Wang, Jian J" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" , "Kinney, Michael D" , "Wolman, Ayellet" Thread-Topic: [PATCH 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: Disable page table protection Thread-Index: AQHTQj+qhI3UwIArdEyPoUuWJ0v9f6Lg/vjQgABRK/A= Date: Fri, 13 Oct 2017 06:14:03 +0000 Message-ID: References: <20171011031824.17060-1-jian.j.wang@intel.com> <20171011031824.17060-6-jian.j.wang@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: Disable page table protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Oct 2017 06:10:35 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable You're right. "BIT3 | BIT2" should be enclosed by parentheses. Thanks for c= atching this issue. > -----Original Message----- > From: Dong, Eric > Sent: Friday, October 13, 2017 9:24 AM > To: Wang, Jian J ; edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Kinney, Michael D > ; Wolman, Ayellet > Subject: RE: [PATCH 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: Disable page table > protection >=20 > Hi Jian, >=20 > > + if (!mCpuSmmStaticPageTable || (PcdGet8 (PcdHeapGuardPropertyMask) > > & > > + BIT3 | BIT2) !=3D 0) { >=20 > I think above code logic is not correct, the "&" will be handled before t= he "|" > which is not an expected order, right? >=20 > Thanks, > Eric >=20 > > -----Original Message----- > > From: Wang, Jian J > > Sent: Wednesday, October 11, 2017 11:18 AM > > To: edk2-devel@lists.01.org > > Cc: Dong, Eric ; Yao, Jiewen ; > > Kinney, Michael D ; Wolman, Ayellet > > > > Subject: [PATCH 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: Disable page table > > protection > > > > Heap guard feature will update page attributes frequently. The page tab= le > > should not set to be read-only if heap guard feature is enabled for SMM > > mode. Otherwise this feature cannot work. > > > > Cc: Eric Dong > > Cc: Jiewen Yao > > Cc: Michael Kinney > > Cc: Ayellet Wolman > > Suggested-by: Ayellet Wolman > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Jian J Wang > > --- > > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + > > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 +- > > 2 files changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > > index 099792e6ce..644709650c 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > > @@ -159,6 +159,7 @@ > > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable ## > > CONSUMES > > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## > > CONSUMES > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrM > > ask ## CONSUMES > > + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask > > ## CONSUMES > > > > [Depex] > > gEfiMpServiceProtocolGuid > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > index 3dde80f9ba..4debce3a0f 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > @@ -902,7 +902,7 @@ SetPageTableAttributes ( > > BOOLEAN IsSplitted; > > BOOLEAN PageTableSplitted; > > > > - if (!mCpuSmmStaticPageTable) { > > + if (!mCpuSmmStaticPageTable || (PcdGet8 (PcdHeapGuardPropertyMask) > > & > > + BIT3 | BIT2) !=3D 0) { > > return ; > > } > > > > -- > > 2.14.1.windows.1