From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 64A96220EE083 for ; Mon, 4 Dec 2017 01:22:01 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Dec 2017 01:26:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,358,1508828400"; d="scan'208";a="10219841" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga001.fm.intel.com with ESMTP; 04 Dec 2017 01:26:31 -0800 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 01:26:30 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 01:26:30 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.152]) with mapi id 14.03.0319.002; Mon, 4 Dec 2017 17:26:28 +0800 From: "Wang, Jian J" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" , "Ni, Ruiyu" , "Dong, Eric" Thread-Topic: [edk2] [PATCH v2 0/4] Enable page table write protection Thread-Index: AQHTbNr7XHanUAd61UeqzF6nBcDE0qMyX8mAgACJO7A= Date: Mon, 4 Dec 2017 09:26:28 +0000 Message-ID: References: <20171204083556.19416-1-jian.j.wang@intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B9BF42B@shsmsx102.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB0483103B9BF42B@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjhlMjIxYTYtYjFhYi00YmQ0LTllM2EtZmY5ODVjOGI4ZTQzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ4K29cL1BrUG5ZaFJOUmZkMmpZQWN2N3FtTDR5eGw0RnM3U0k3RVU5WFJ3UG8yYXZKZUhacGVYVjl3MzNkWkwzdSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 0/4] Enable page table write protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Dec 2017 09:22:02 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable That means we can't share page table pool between DxeIpl and CpuDxe. If thi= s is acceptable, I can remove them. > -----Original Message----- > From: Zeng, Star > Sent: Monday, December 04, 2017 5:11 PM > To: Wang, Jian J ; edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Ni, Ruiyu ; D= ong, > Eric ; Zeng, Star > Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection >=20 > Recommend to not introduce the new header file and PCDs as new interfaces= , > but handle the page table pool separately in DxeIpl and CpuDxe. >=20 > Thanks, > Star > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ji= an J > Wang > Sent: Monday, December 4, 2017 4:36 PM > To: edk2-devel@lists.01.org > Subject: [edk2] [PATCH v2 0/4] Enable page table write protection >=20 > > v2 changes: > > a. Enable protection on any newly added page table after DxeIpl. > > b. Introduce page table pool concept to make page table allocation > > and protection easier and error free. >=20 > Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/Cpu= Dxe. > But the memory pages used for page table are not set as read-only in the = driver > DxeIplPeim, after the paging is setup. This might jeopardize the page tab= le > integrity if there's buffer overflow occured in other part of system. >=20 > This patch series will change this situation by clearing R/W bit in page = attribute > of the pages used as page table. >=20 > Validation works include booting Windows (10/server 2016) and Linux > (Fedora/Ubuntu) on OVMF and Intel real platform. >=20 > Jian J Wang (4): > MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid > MdeModulePkg/PageTablePool.h: Page table pool GUID definition file > MdeModulePkg/DxeIpl: Mark page table as read-only > UefiCpuPkg/CpuDxe: Enable protection for newly added page table >=20 > MdeModulePkg/Core/DxeIplPeim/DxeIpl.h | 34 +++ > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 3 + > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 8 +- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315 > +++++++++++++++++++++- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 15 ++ > MdeModulePkg/Include/Guid/PageTablePool.h | 53 ++++ > MdeModulePkg/MdeModulePkg.dec | 28 ++ > UefiCpuPkg/CpuDxe/CpuDxe.c | 17 +- > UefiCpuPkg/CpuDxe/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + > UefiCpuPkg/CpuDxe/CpuPageTable.c | 329 > ++++++++++++++++++++++- > UefiCpuPkg/CpuDxe/CpuPageTable.h | 22 ++ > 12 files changed, 816 insertions(+), 13 deletions(-) create mode 100644 > MdeModulePkg/Include/Guid/PageTablePool.h >=20 > -- > 2.14.1.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel