From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Permerror (SPF Permanent Error: More than 10 MX records returned) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2F6D421B02834 for ; Thu, 7 Dec 2017 00:20:23 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Dec 2017 00:24:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,372,1508828400"; d="scan'208";a="10315528" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 07 Dec 2017 00:24:55 -0800 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Dec 2017 00:24:55 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Dec 2017 00:24:54 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Thu, 7 Dec 2017 16:24:52 +0800 From: "Wang, Jian J" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH v4 00/11] Implement stack guard feature Thread-Index: AQHTbm9F9W+TxVghMU+55W5A/70sC6M3BJeAgACG3OA= Date: Thu, 7 Dec 2017 08:24:52 +0000 Message-ID: References: <20171206085005.14552-1-jian.j.wang@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503AA3CFF0@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503AA3CFF0@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODMwNTNmNzctOWRkZC00YTFiLTg3NWQtMjNkOTQ4Yjk4NDBmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ2WnhwZ1F0b2tjTUZQRUtVckxWeHJYVTlyWFQyZzh1V2k4SmxrdUhqdDFyWjdmdkNCS0I3aHpnYUFhdVMwcE9rIn0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v4 00/11] Implement stack guard feature X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Dec 2017 08:20:23 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I missed that part. I'll add it. Thanks. Regards, Jian > -----Original Message----- > From: Yao, Jiewen > Sent: Thursday, December 07, 2017 4:17 PM > To: Wang, Jian J ; edk2-devel@lists.01.org > Subject: RE: [edk2] [PATCH v4 00/11] Implement stack guard feature >=20 > Thanks. I still think we should add version field, just in case we need a= dd more in > this CPU_EXCEPTION_INIT_DATA. >=20 > With version field added, reviewed-by: Jiewen.yao@intel.com >=20 > I suggest CpuModulePkg can double check the patch. >=20 > Thank you > Yao Jiewen >=20 > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of = Jian > J > > Wang > > Sent: Wednesday, December 6, 2017 4:50 PM > > To: edk2-devel@lists.01.org > > Subject: [edk2] [PATCH v4 00/11] Implement stack guard feature > > > > > v4: > > > a. Change name of new data structure from > CPU_EXCEPTION_INIT_DATA_EX > > > to CPU_EXCEPTION_INIT_DATA > > > b. Add "size" field for all "buffer" fields in CPU_EXCEPTION_INIT_DA= TA > > > c. Add separate fields for IA32 and X64 in CPU_EXCEPTION_INIT_DATA > > > d. Change related code per changes in CPU_EXCEPTION_INIT_DATA > > > > > v3: > > > a. Change new API InitializeCpuExceptionStackSwitchHandlers() to > > > InitializeCpuExceptionHandlersEx(). Related code are updated > > accordingly. > > > b. Move EXCEPTION_STACK_SWITCH_DATA to CpuExceptionHandlerLib.h > > > and change the name to CPU_EXCEPTION_INIT_DATA_EX for the sake > > > of the API name change. > > > c. Add more general macros in BaseLib.h. > > > d. Add dummy implementation of InitializeCpuExceptionHandlersEx for > > > SEC, PEI and SMM but implement a full version for DXE. > > > e. Add dummy InitializeCpuExceptionHandlersEx for ARM's > > CpuExceptionHandlerLib > > > and NULL version of CpuExceptionHandlerLib > > > f. Call InitializeCpuExceptionHandlersEx() in DxeMain instead of > > > InitializeCpuExceptionHandlers(). > > > > > > > v2: > > > a. Introduce and implement new API > > InitializeCpuExceptionStackSwitchHandlers(). > > > b. Add stack switch related general definitions of IA32 in BaseLib.h= . > > > c. Add two new PCDs to configure exception vector list and stack siz= e. > > > d. Add code to save/restore GDTR, IDTR and TR for AP. > > > e. Refactor exception handler code for stack switch. > > > f. Add code to setup stack switch for AP besides BSP. > > > > Stack guard feature makes use of paging mechanism to monitor if there's= a > > stack overflow occurred during boot. A new PCD PcdCpuStackGuard is adde= d > to > > enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and > > PcdCpuKnownGoodStackSize are introduced to configure the required > > exceptions > > and stack size. > > > > If this feature is enabled, DxeIpl will setup page tables and set page = where > > the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Pag= e > > Fault exception will be triggered. > > > > In order to make sure exception handler works normally even when the st= ack > > is corrupted, stack switching is implemented in exception library. > > > > Due to the mechanism behind Stack Guard, this feature is only avaiable = for > > UEFI drivers (memory avaiable). That also means it doesn't support NT32 > > emulated platform (paging not supported). > > > > Jian J Wang (11): > > MdeModulePkg/metafile: Add PCD PcdCpuStackGuard > > UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch > > MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API > > InitializeCpuExceptionHandlersEx > > MdePkg/BaseLib: Add stack switch related definitions for IA32 > > UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support > > MdeModulePkg/CpuExceptionHandlerLibNull: Add new API implementation > > ArmPkg/ArmExceptionLib: Add implementation of new API > > UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data > > UefiCpuPkg/CpuDxe: Initialize stack switch for MP > > MdeModulePkg/Core/Dxe: Call new API InitializeCpuExceptionHandlersEx > > instead > > MdeModulePkg/DxeIpl: Enable paging for Stack Guard > > > > ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c | 33 ++ > > MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 2 +- > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +- > > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 + > > MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 + > > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++- > > .../Include/Library/CpuExceptionHandlerLib.h | 91 +++++ > > .../CpuExceptionHandlerLibNull.c | 34 ++ > > MdeModulePkg/MdeModulePkg.dec | 7 + > > MdeModulePkg/MdeModulePkg.uni | 7 + > > MdePkg/Include/Library/BaseLib.h | 117 ++++++ > > MdePkg/Library/BaseLib/BaseLib.inf | 3 + > > MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++ > > MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++ > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + > > UefiCpuPkg/CpuDxe/CpuMp.c | 188 > > ++++++++++ > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 39 ++ > > .../DxeCpuExceptionHandlerLib.inf | 6 + > > .../Library/CpuExceptionHandlerLib/DxeException.c | 83 +++++ > > .../Ia32/ArchExceptionHandler.c | 187 ++++++++++ > > .../Ia32/ArchInterruptDefs.h | 8 + > > .../Ia32/ExceptionTssEntryAsm.nasm | 398 > > +++++++++++++++++++++ > > .../CpuExceptionHandlerLib/PeiCpuException.c | 34 +- > > .../PeiCpuExceptionHandlerLib.inf | 1 + > > .../CpuExceptionHandlerLib/SecPeiCpuException.c | 34 +- > > .../SecPeiCpuExceptionHandlerLib.inf | 1 + > > .../SmmCpuExceptionHandlerLib.inf | 1 + > > .../Library/CpuExceptionHandlerLib/SmmException.c | 34 +- > > .../X64/ArchExceptionHandler.c | 155 ++++++++ > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 + > > UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 + > > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 + > > UefiCpuPkg/UefiCpuPkg.dec | 12 + > > 33 files changed, 1616 insertions(+), 19 deletions(-) > > create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm > > create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm > > create mode 100644 > > > UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm > > > > -- > > 2.15.1.windows.2 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel