From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.126; helo=mga18.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DA670220C2A7F for ; Thu, 15 Mar 2018 20:09:58 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Mar 2018 20:16:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,313,1517904000"; d="scan'208";a="42476715" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga002.jf.intel.com with ESMTP; 15 Mar 2018 20:16:23 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 15 Mar 2018 20:16:22 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 15 Mar 2018 20:16:22 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.235]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.108]) with mapi id 14.03.0319.002; Fri, 16 Mar 2018 11:16:20 +0800 From: "Wang, Jian J" To: "Gao, Liming" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Kinney, Michael D" Thread-Topic: [Patch] UefiCpuPkg CpuExceptionHandlerLib: use FixedPcdGetSize() as the macro value Thread-Index: AQHTvMi8dn5b8pt6rECKc32Vjr+SzaPSMJ6g Date: Fri, 16 Mar 2018 03:16:19 +0000 Message-ID: References: <20180316014706.15952-1-liming.gao@intel.com> In-Reply-To: <20180316014706.15952-1-liming.gao@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNmVjNjk4NjUtZWU4OC00MDEwLWEzMjYtZjMxNmI3NmNlNDM1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJucWROV1dwNVVKU09VSkNwREtwSVl2bjI5cmVHXC85RU1uYWh4SEhibTc2QVZ1dHBsTVJsU0JtNU5DeTVcLytxeVcifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg CpuExceptionHandlerLib: use FixedPcdGetSize() as the macro value X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Mar 2018 03:09:59 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jian J Wang > -----Original Message----- > From: Gao, Liming > Sent: Friday, March 16, 2018 9:47 AM > To: edk2-devel@lists.01.org > Cc: Wang, Jian J ; Ni, Ruiyu ; > Kinney, Michael D > Subject: [Patch] UefiCpuPkg CpuExceptionHandlerLib: use FixedPcdGetSize()= as > the macro value >=20 > FixedPcdGetSize() is used as the macro value, PcdGetSize() is used as glo= bal > variable or function. Here usage is to access macro value. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Liming Gao > Cc: Wang Jian J > Cc: Ruiyu Ni > Cc: Michael Kinney > --- > UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h | 6 += ++- > -- > 1 file changed, 3 insertions(+), 3 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h > index d9ded5977f..ac3650a2a3 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h > @@ -1,7 +1,7 @@ > /** @file > Ia32 arch definition for CPU Exception Handler Library. >=20 > - Copyright (c) 2013, Intel Corporation. All rights reserved.
> + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be found > at > @@ -43,10 +43,10 @@ typedef struct { >=20 > #define CPU_TSS_DESC_SIZE \ > (sizeof (IA32_TSS_DESCRIPTOR) * \ > - (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1)) > + (FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + 1)) >=20 > #define CPU_TSS_SIZE \ > (sizeof (IA32_TASK_STATE_SEGMENT) * \ > - (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1)) > + (FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + 1)) >=20 > #endif > -- > 2.11.0.windows.1