From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel-bounces@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6B1BF210F6225; Mon, 20 Aug 2018 01:28:20 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2018 01:28:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,264,1531810800"; d="scan'208";a="226065128" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga004.jf.intel.com with ESMTP; 20 Aug 2018 01:28:17 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 20 Aug 2018 01:28:17 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 20 Aug 2018 01:28:17 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.240]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.150]) with mapi id 14.03.0319.002; Mon, 20 Aug 2018 16:28:15 +0800 From: "Wang, Jian J" To: edk2-devel , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH 0/4] Support non-stop mode in heap guard and null detection Thread-Index: AQHUOFEJtgTLgLNZokGqvRXbwFiqqKTITd9A Date: Mon, 20 Aug 2018 08:28:15 +0000 Message-ID: References: <20180820064201.16592-1-jian.j.wang@intel.com> In-Reply-To: <20180820064201.16592-1-jian.j.wang@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTcyN2Q1MDUtMzg5Zi00ZTcwLWFjYjgtNjEzMGQ2NmE1ZTcxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMmVieVJ2ZmhoQzFqdW5HV1pDZ3dBd3lGMDI3SXpta3NCOXg2Szd1c1Q4YlwvODRlTkdHNGtYMExmOE1BM2YzaloifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 0/4] Support non-stop mode in heap guard and null detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 08:28:20 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Forgot to mention the OS boot validation: Platform: OVMF OS (x64): Fedora 26, Ubuntu 18.04, Windows 10, Windows 7 Regards, Jian > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] > Sent: Monday, August 20, 2018 2:42 PM > To: edk2-devel@lists.01.org > Subject: [edk2] [PATCH 0/4] Support non-stop mode in heap guard and null > detection >=20 > Background: > Heap Guard and NULL Pointer Detection are very useful features to detect > code flaw in EDK II. If an issue is detected, #PF exception will be > triggered and the BIOS will enter into dead loop, which is the default > behavior of exception handling. From QA perspective, this default behavio= r > will block them to collect all tests result in reasonable time. >=20 > Solution: > This patch series update CpuDxe, PiSmmCpuDxeSmm and > CpuExceptionHandlerLib > to allow the code to continue execution after #PF. The mechanism behind i= t > is the same as SMM Profile feature, in which a special #PF handler is > registered to set the page causing #PF to be 'present' and setup single > steop trap, then return the control back to the instruction accessing tha= t > page. Once the instruction is re-executed, a #DB is triggered and a speci= al > handler for it will be called to reset the page back to 'not-present'. >=20 > Usage: > The non-stop mode is enabled/disabled by BIT6 of following PCDs >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask > gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask >=20 > The default setting is 'disable'. >=20 > BZ Tracker: > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1095 >=20 > Jian J Wang (4): > MdeModulePkg/MdeModulePkg.dec: add new settings for PCDs > UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler > UefiCpuPkg/CpuDxe: implement non-stop mode for uefi > UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM >=20 > MdeModulePkg/MdeModulePkg.dec | 4 +- > UefiCpuPkg/CpuDxe/CpuDxe.h | 39 +++ > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + > UefiCpuPkg/CpuDxe/CpuMp.c | 34 ++- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 271 +++++++++++++++= ++++++ > .../Ia32/ExceptionHandlerAsm.nasm | 7 + > .../Ia32/ExceptionTssEntryAsm.nasm | 4 +- > .../X64/ExceptionHandlerAsm.nasm | 4 + > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 43 ++-- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 3 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 60 ++++- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 ++ > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 6 + > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 43 ++-- > 14 files changed, 495 insertions(+), 41 deletions(-) >=20 > -- > 2.16.2.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel