From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Permerror (SPF Permanent Error: Two or more type TXT spf records found.) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3270A210FCF5C for ; Sun, 2 Sep 2018 19:19:54 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Sep 2018 19:19:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,323,1531810800"; d="scan'208";a="82438801" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga002.fm.intel.com with ESMTP; 02 Sep 2018 19:15:37 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 2 Sep 2018 19:15:37 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 2 Sep 2018 19:15:36 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.240]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.205]) with mapi id 14.03.0319.002; Mon, 3 Sep 2018 10:15:34 +0800 From: "Wang, Jian J" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH 2/2] UefiCpuPkg/CpuExceptionHandlerLib: Avoid calling PEI services from AP Thread-Index: AQHUQQWZkCSSepGTgkKJwrFvgYKHLKTd1UcQ Date: Mon, 3 Sep 2018 02:15:34 +0000 Message-ID: References: <20180831083620.303688-1-ruiyu.ni@intel.com> <20180831083620.303688-3-ruiyu.ni@intel.com> In-Reply-To: <20180831083620.303688-3-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMmQ0MDdjMDctYmY3OS00ZjE5LTgyMmYtOTE1MThlNTc0YjQ1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiV1dcL0NHMXp3STkwWjh1eDkwQmRDQ3lJZnlCTEFtSktmK1lDQ2RITitwZ1RlT3FDb2pRd3BISUJLYlF5dEJaS1MifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] UefiCpuPkg/CpuExceptionHandlerLib: Avoid calling PEI services from AP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 03 Sep 2018 02:19:54 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Validated-by: Jian J Wang Reviewed-by: Jian J Wang > -----Original Message----- > From: Ni, Ruiyu > Sent: Friday, August 31, 2018 4:36 PM > To: edk2-devel@lists.01.org > Cc: Wang, Jian J ; Fan Jeff > Subject: [PATCH 2/2] UefiCpuPkg/CpuExceptionHandlerLib: Avoid calling PEI > services from AP >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1128 >=20 > When an exception happens in AP, system hangs at > GetPeiServicesTablePointer(), complaining the PeiServices retrieved > from memory before IDT is NULL. >=20 > Due to the following commit: > c563077a380437c114aba4c95be65eb963ebc1f3 > * UefiCpuPkg/MpInitLib: Avoid calling PEI services from AP > the IDT used by AP no longer preserve PeiServices pointer in the > very beginning. > But the implementation of PeiExceptionHandlerLib still assumes > the PeiServices pointer is there, so the assertion happens. >=20 > The patch fixes the exception handler library to not call > PEI services from AP. >=20 > The patch duplicates the #0 exception stub header in an allocated > pool but with extra 4-byte/8-byte to store the exception handler > data which was originally stored in HOB. > When AP exception happens, the code gets the exception handler data > from the exception handler for #0. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ruiyu Ni > Cc: Jian J Wang > Cc: Fan Jeff > --- > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 7 +- > .../CpuExceptionHandlerLib/PeiCpuException.c | 77 +++++++++++++++-= ------ > 2 files changed, 55 insertions(+), 29 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > index e10d9379d5..459f06ac84 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > @@ -1,7 +1,7 @@ > /** @file > Common header file for CPU Exception Handler Library. >=20 > - Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be found > at > @@ -43,11 +43,6 @@ >=20 > #include "ArchInterruptDefs.h" >=20 > -#define CPU_EXCEPTION_HANDLER_LIB_HOB_GUID \ > - { \ > - 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x= 2c, > 0x83 } \ > - } > - > #define CPU_STACK_SWITCH_EXCEPTION_NUMBER \ > FixedPcdGetSize (PcdCpuStackSwitchExceptionList) >=20 > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c > index 6f271983f2..5dd8423d2f 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c > @@ -1,7 +1,7 @@ > /** @file > CPU exception handler library implementation for PEIM module. >=20 > -Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made availa= ble > under > the terms and conditions of the BSD License that accompanies this distri= bution. > The full text of the license may be found at > @@ -20,10 +20,17 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, EITHER EXPRESS OR IMPLIED. >=20 > CONST UINTN mDoFarReturnFlag =3D 0; >=20 > -EFI_GUID mCpuExceptrionHandlerLibHobGuid =3D > CPU_EXCEPTION_HANDLER_LIB_HOB_GUID; > +typedef struct { > + UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE]; > + EXCEPTION_HANDLER_DATA *ExceptionHandlerData; > +} EXCEPTION0_STUB_HEADER; >=20 > /** > - Get exception handler data pointer from GUIDed HOb. > + Get exception handler data pointer from IDT[0]. > + > + The exception #0 stub header is duplicated in an allocated pool with e= xtra 4- > byte/8-byte to store the > + exception handler data. The new allocated memory layout follows struct= ure > EXCEPTION0_STUB_HEADER. > + The code assumes that all processors uses the same exception handler f= or #0 > exception. >=20 > @return pointer to exception handler data. > **/ > @@ -32,18 +39,50 @@ GetExceptionHandlerData ( > VOID > ) > { > - EFI_HOB_GUID_TYPE *GuidHob; > - VOID *DataInHob; > - EXCEPTION_HANDLER_DATA *ExceptionHandlerData; > + IA32_DESCRIPTOR IdtDescriptor; > + IA32_IDT_GATE_DESCRIPTOR *IdtTable; > + EXCEPTION0_STUB_HEADER *Exception0StubHeader; > + > + AsmReadIdtr (&IdtDescriptor); > + IdtTable =3D (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; > + > + Exception0StubHeader =3D (EXCEPTION0_STUB_HEADER *)ArchGetIdtHandler > (&IdtTable[0]); > + return Exception0StubHeader->ExceptionHandlerData; > +} >=20 > - ExceptionHandlerData =3D NULL; > - GuidHob =3D GetFirstGuidHob (&mCpuExceptrionHandlerLibHobGuid); > - if (GuidHob !=3D NULL) { > - DataInHob =3D GET_GUID_HOB_DATA (GuidHob); > - ExceptionHandlerData =3D (EXCEPTION_HANDLER_DATA *)(*(UINTN > *)DataInHob); > - } > - ASSERT (ExceptionHandlerData !=3D NULL); > - return ExceptionHandlerData; > +/** > + Set exception handler data pointer to IDT[0]. > + > + The exception #0 stub header is duplicated in an allocated pool with e= xtra 4- > byte/8-byte to store the > + exception handler data. The new allocated memory layout follows struct= ure > EXCEPTION0_STUB_HEADER. > + The code assumes that all processors uses the same exception handler f= or #0 > exception. > + > + @param pointer to exception handler data. > +**/ > +VOID > +SetExceptionHandlerData ( > + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData > + ) > +{ > + EXCEPTION0_STUB_HEADER *Exception0StubHeader; > + IA32_DESCRIPTOR IdtDescriptor; > + IA32_IDT_GATE_DESCRIPTOR *IdtTable; > + // > + // Duplicate the exception #0 stub header in pool and cache the > ExceptionHandlerData just after the stub header. > + // So AP can get the ExceptionHandlerData by reading the IDT[0]. > + // > + AsmReadIdtr (&IdtDescriptor); > + IdtTable =3D (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; > + > + Exception0StubHeader =3D AllocatePool (sizeof (*Exception0StubHeader))= ; > + ASSERT (Exception0StubHeader !=3D NULL); > + CopyMem ( > + Exception0StubHeader->ExceptionStubHeader, > + (VOID *)ArchGetIdtHandler (&IdtTable[0]), > + sizeof (Exception0StubHeader->ExceptionStubHeader) > + ); > + Exception0StubHeader->ExceptionHandlerData =3D ExceptionHandlerData; > + ArchUpdateIdtEntry (&IdtTable[0], (UINTN)Exception0StubHeader- > >ExceptionStubHeader); > } >=20 > /** > @@ -109,15 +148,7 @@ InitializeCpuExceptionHandlers ( > return Status; > } >=20 > - // > - // Build location of CPU MP DATA buffer in HOB > - // > - BuildGuidDataHob ( > - &mCpuExceptrionHandlerLibHobGuid, > - (VOID *)&ExceptionHandlerData, > - sizeof(UINT64) > - ); > - > + SetExceptionHandlerData (ExceptionHandlerData); > return EFI_SUCCESS; > } >=20 > -- > 2.16.1.windows.1