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DIR:OUT; SFP:1101; SCL:1; SRVR:DB4PR04MB300; H:DB4PR04MB299.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Oct 2017 16:53:50.7016 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR04MB300 Subject: Re: Clarification about InitializeCpuExceptionHandlers() and TGE bit in hcr_el2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Oct 2017 16:50:32 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Andrew Fish, I understand. In PEI Phase, No handlers are installed and there might be pending excepti= on. ExceptionHandlers() can be installed during PEI phase like after initia= lizing the MMU to catch unhandled exception. Please suggest? Dear Arm Folks, I request you to comment on hcr_el2 usage mentioned in below email I understand that Enabling TGE bit will route the EL1 exception to EL2.Is t= here any EL1 code during UEFI execution?=20 Regards, Vabhav -----Original Message----- From: afish@apple.com [mailto:afish@apple.com]=20 Sent: Thursday, September 28, 2017 7:31 PM To: Vabhav Sharma Cc: edk2-devel@lists.01.org; edk2-devel Subject: Re: [edk2] Clarification about InitializeCpuExceptionHandlers() an= d TGE bit in hcr_el2 > On Sep 28, 2017, at 4:23 AM, Vabhav Sharma wrote: >=20 > Hi All, >=20 > I see that InitializeCpuExceptionHandlers() is called from DxeMain to tak= e over exception handlers and later from ArmCpuDxe. > Is there any specific purpose to call it from two places during dxe phase= ? >=20 Vabhav, DxeMain is the DXE Core and that is like (micro) kernel and it is platform = agnostic code. InitializeCpuExceptionHandlers() exists in that location to = catch unhandled exceptions, especially in the case when no debugger stub is= linked in. The CPU Dxe driver abstracts CPU specifics from the DXE Core an= d it adds supports for interrupts, cachability, etc. and the DXE Core uses = services from this driver to abstract CPU implementation. To make things even more complex on some platforms PEI and DXE run in entir= ely different modes. For example on x86 is is common for PEI to be 32-bit a= nd and DXE to be 64-bit. This is mostly due to how complex it is to turn on= memory, and the fact that there is no good place to put the page tables pr= ior to memory init.=20 I'll let the ARM folks comment on hcr_el2 usage.=20 Thanks, Andrew Fish=20 > Additionally we are setting TGE bit three times in hcr_el2 during PrePei = phase(ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c) > and Twice in Dxe phase: dxemain(),ArmCpuDxe >=20 > Please help to clarify or required to be fixed? >=20 > Regards, > Vabhav > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel