* [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support
@ 2017-12-22 12:16 Meenakshi Aggarwal
2017-12-22 12:16 ` [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller Meenakshi Aggarwal
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: Meenakshi Aggarwal @ 2017-12-22 12:16 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Following patches add support for pci emulation layer
and SATA on NXP boards.
Null Library for USB is also present to give completeness
to Pci Emulation layer.
Meenakshi Aggarwal (3):
USB: Added Support of DWC3 USB controller.
PciEmulation : Add support for Pci Emulation layer.
SATA : Added SATA controller initialization driver.
Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 +++++++++++++++++++++
Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++
Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++
.../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++
Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++
Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++
Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++
.../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 +
.../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 +
Platform/NXP/NxpQoriqLs.dec | 14 +-
Platform/NXP/NxpQoriqLs.dsc | 15 +
11 files changed, 1547 insertions(+), 2 deletions(-)
create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c
create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h
create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf
create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c
create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c
create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h
create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c
create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf
--
1.9.1
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller. 2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal @ 2017-12-22 12:16 ` Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 2/3] PciEmulation : Add support for Pci Emulation layer Meenakshi Aggarwal ` (3 subsequent siblings) 4 siblings, 0 replies; 21+ messages in thread From: Meenakshi Aggarwal @ 2017-12-22 12:16 UTC (permalink / raw) To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel Added library for DWC3 USB controller and enabled USB support in pci emulation layer. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> --- .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 +++++++++++++++++++ .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 ++++++++++++++++++++++ Platform/NXP/NxpQoriqLs.dsc | 9 +++++++ 3 files changed, 62 insertions(+) create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf diff --git a/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c b/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c new file mode 100644 index 0000000..51a9b16 --- /dev/null +++ b/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c @@ -0,0 +1,25 @@ +/** @file + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi.h> + +EFI_STATUS +EFIAPI +InitializeUsbController ( + IN UINTN UsbReg + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf b/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf new file mode 100644 index 0000000..76a414e --- /dev/null +++ b/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf @@ -0,0 +1,28 @@ +# UsbHcdNull.inf +# NULL Library fr DWC3 +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +*/ + +[Defines] + INF_VERSION = 0x0001000A + BASE_NAME = UsbHcdNull + FILE_GUID = 0946b308-9ac9-4e01-b4ec-e6e4d72991ec + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = UsbHcdLib + +[Sources.common] + UsbHcdLibNull.c + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 54f0c2c..9b450fa 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -392,6 +392,15 @@ FatPkg/EnhancedFatDxe/Fat.inf # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # # Bds # MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH edk2-platforms 2/3] PciEmulation : Add support for Pci Emulation layer. 2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller Meenakshi Aggarwal @ 2017-12-22 12:16 ` Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 3/3] SATA : Added SATA controller initialization driver Meenakshi Aggarwal ` (2 subsequent siblings) 4 siblings, 0 replies; 21+ messages in thread From: Meenakshi Aggarwal @ 2017-12-22 12:16 UTC (permalink / raw) To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset="y", Size: 47146 bytes --] SATA and USB will use this pci emulation layer Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> --- Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 +++++++++++++++++++++ Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ Platform/NXP/NxpQoriqLs.dec | 9 +- 5 files changed, 1277 insertions(+), 2 deletions(-) create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.c b/Platform/NXP/Drivers/PciEmulation/PciEmulation.c new file mode 100644 index 0000000..6635eb4 --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.c @@ -0,0 +1,624 @@ +/** PciEmulation.c + Provides all functions of PCI Host Bridge Resource Allocation Protocol + + Reference taken from PCI Emulation implementation in + Omap35xxPkg/PciEmulation/ + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciEmulation.h" + +EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate = +{ + { + { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } }, + EISA_PNP_ID(0x0A03), // HID + 0 // UID + }, + { + { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } }, + 0, + 0 + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} } +}; + +EFI_STATUS +PciIoPollMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMemRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + return PciRootBridgeIoMemRead (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Private->ConfigSpace->Device.Bar[0] + Offset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoMemWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Private->ConfigSpace->Device.Bar[0] + Offset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoIoWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Enable a PCI driver to read PCI controller registers in PCI configuration space. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] Offset The offset within the PCI configuration space for + the PCI controller. + @param[in] Count The number of PCI configuration operations to + perform. Bytes moved is Width size * Count, + starting at Offset. + + @param[in out] Buffer The destination buffer to store the results. + + @retval EFI_SUCCESS The data was read from the PCI controller. + @retval EFI_INVALID_PARAMETER "Width" is invalid. + @retval EFI_INVALID_PARAMETER "Buffer" is NULL. + +**/ +EFI_STATUS +PciIoPciRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + EFI_STATUS Status; + UINT64 Address; + + Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Address = (UINT64)((UINT8 *)Private->ConfigSpace + Offset); + Status = PciRootBridgeIoMemRW (FALSE, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, + Address, + Count, + Buffer + ); + + return Status; +} + +/** + Enable a PCI driver to write PCI controller registers in PCI configuration space. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] Offset The offset within the PCI configuration space for + the PCI controller. + @param[in] Count The number of PCI configuration operations to + perform. Bytes moved is Width size * Count, + starting at Offset. + + @param[in out] Buffer The source buffer to write data from. + + @retval EFI_SUCCESS The data was read from the PCI controller. + @retval EFI_INVALID_PARAMETER "Width" is invalid. + @retval EFI_INVALID_PARAMETER "Buffer" is NULL. + +**/ +EFI_STATUS +PciIoPciWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoMemRW (TRUE, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + (UINT64)(Private->ConfigSpace + Offset), + Count, + Buffer + ); +} + +EFI_STATUS +PciIoCopyMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 DestBarIndex, + IN UINT64 DestOffset, + IN UINT8 SrcBarIndex, + IN UINT64 SrcOffset, + IN UINTN Count + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + DMA_MAP_OPERATION DmaOperation; + + if (Operation == EfiPciIoOperationBusMasterRead) { + DmaOperation = MapOperationBusMasterRead; + } else if (Operation == EfiPciIoOperationBusMasterWrite) { + DmaOperation = MapOperationBusMasterWrite; + } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) { + DmaOperation = MapOperationBusMasterCommonBuffer; + } else { + return EFI_INVALID_PARAMETER; + } + + return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping); +} + +EFI_STATUS +PciIoUnmap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN VOID *Mapping + ) +{ + return DmaUnmap (Mapping); +} + +/** + Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer + mapping. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] Type This parameter is not used and must be ignored. + @param[in] MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param[in] Pages The number of pages to allocate. + @param[out] HostAddress A pointer to store the base system memory address of + the allocated range. + @param[in] Attributes The requested bit mask of attributes for the allocated + range. Only the attributes, + EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and + EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this + function. If any other bits are set, then EFI_UNSUPPORTED + is returned. This function ignores this bit mask. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_UNSUPPORTED Attributes is unsupported. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +PciIoAllocateBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + if (Attributes & + (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | + EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) { + return EFI_UNSUPPORTED; + } + + return DmaAllocateBuffer (MemoryType, Pages, HostAddress); +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages + was not allocated with AllocateBuffer(). + +**/ + +EFI_STATUS +PciIoFreeBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + return DmaFreeBuffer (Pages, HostAddress); +} + +EFI_STATUS +PciIoFlush ( + IN EFI_PCI_IO_PROTOCOL *This + ) +{ + // + // not supported yet + // + return EFI_SUCCESS; +} + +/** + Retrieves this PCI controller's current PCI bus number, device number, and function number. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[out] SegmentNumber The PCI controller's current PCI segment number. + @param[out] BusNumber The PCI controller's current PCI bus number. + @param[out] DeviceNumber The PCI controller's current PCI device number. + @param[out] FunctionNumber The PCI controller’s current PCI function number. + + @retval EFI_SUCCESS The PCI controller location was returned. + @retval EFI_INVALID_PARAMETER At least one out of the four output parameters is + a NULL pointer. +**/ +EFI_STATUS +PciIoGetLocation ( + IN EFI_PCI_IO_PROTOCOL *This, + OUT UINTN *SegmentNumber, + OUT UINTN *BusNumber, + OUT UINTN *DeviceNumber, + OUT UINTN *FunctionNumber + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + if ((SegmentNumber == NULL) || (BusNumber == NULL) || + (DeviceNumber == NULL) || (FunctionNumber == NULL) ) { + return EFI_INVALID_PARAMETER; + } + + Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + *SegmentNumber = Private->Segment; + *BusNumber = 0xff; + *DeviceNumber = 0; + *FunctionNumber = 0; + + return EFI_SUCCESS; +} + +/** + Performs an operation on the attributes that this PCI controller supports. + + The operations include getting the set of supported attributes, retrieving + the current attributes, setting the current attributes, enabling attributes, + and disabling attributes. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] Operation The operation to perform on the attributes for this + PCI controller. + @param[in] Attributes The mask of attributes that are used for Set, + Enable and Disable operations. + @param[out] Result A pointer to the result mask of attributes that are + returned for the Get and Supported operations. This + is an optional parameter that may be NULL for the + Set, Enable, and Disable operations. + + @retval EFI_SUCCESS The operation on the PCI controller's + attributes was completed. If the operation + was Get or Supported, then the attribute mask + is returned in Result. + @retval EFI_INVALID_PARAMETER Operation is greater than or equal to + EfiPciIoAttributeOperationMaximum. + @retval EFI_INVALID_PARAMETER Operation is Get and Result is NULL. + @retval EFI_INVALID_PARAMETER Operation is Supported and Result is NULL. + +**/ +EFI_STATUS +PciIoAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, + IN UINT64 Attributes, + OUT UINT64 *Result OPTIONAL + ) +{ + switch (Operation) { + case EfiPciIoAttributeOperationGet: + case EfiPciIoAttributeOperationSupported: + if (Result == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // We are not a real PCI device so just say things we kind of do + // + *Result = EFI_PCI_DEVICE_ENABLE; + break; + + case EfiPciIoAttributeOperationSet: + case EfiPciIoAttributeOperationEnable: + case EfiPciIoAttributeOperationDisable: + if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) { + return EFI_UNSUPPORTED; + } + // + // Since we are not a real PCI device no enable/set or disable operations exist. + // + break; + + default: + return EFI_INVALID_PARAMETER; + }; + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoGetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT8 BarIndex, + OUT UINT64 *Supports, OPTIONAL + OUT VOID **Resources OPTIONAL + ) +{ + if (Supports == NULL && Resources == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoSetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN UINT8 BarIndex, + IN OUT UINT64 *Offset, + IN OUT UINT64 *Length + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_PCI_IO_PROTOCOL PciIoTemplate = +{ + PciIoPollMem, + 0, + { PciIoMemRead, PciIoMemWrite }, + { 0, PciIoIoWrite }, + { PciIoPciRead, PciIoPciWrite }, + PciIoCopyMem, + PciIoMap, + PciIoUnmap, + PciIoAllocateBuffer, + PciIoFreeBuffer, + PciIoFlush, + PciIoGetLocation, + PciIoAttributes, + PciIoGetBarAttributes, + PciIoSetBarAttributes, + 0, + 0 +}; + +EFI_STATUS +PciInstallDevice ( + IN UINTN DeviceId, + IN PHYSICAL_ADDRESS MemoryStart, + IN UINT64 MemorySize, + IN UINTN ClassCode1, + IN UINTN ClassCode2, + IN UINTN ClassCode3 + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + EFI_PCI_IO_PRIVATE_DATA *Private; + + // + // Create a private structure + // + Private = AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA)); + if (Private == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "Failed to allocate memory for EFI_PCI_IO_PRIVATE_DATA\n")); + return Status; + } + + Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature + Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too + Private->RootBridge.MemoryStart = MemoryStart; // Get the controller register base + Private->Segment = 0; // Default to segment zero + + // + // Calculate the total size of the controller. + // + Private->RootBridge.MemorySize = MemorySize; + + // + // HBA reset + // + if (PCI_CLASS_MASS_STORAGE_SATADPA == ClassCode2) { + MmioWrite32 ((Private->RootBridge.MemoryStart + HBA_GHC), HBA_RESET); + } + + // + // Create fake PCI config space + // + Private->ConfigSpace = AllocateZeroPool (sizeof (PCI_TYPE00)); + if (Private->ConfigSpace == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "Failed to allocate memory for PCI_TYPE00\n")); + FreePool (Private); + return Status; + } + + // + // Configure PCI config space + // + Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device. + Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid. + Private->ConfigSpace->Hdr.ClassCode[0] = ClassCode1; + Private->ConfigSpace->Hdr.ClassCode[1] = ClassCode2; + Private->ConfigSpace->Hdr.ClassCode[2] = ClassCode3; + Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart; + + Handle = NULL; + + // Unique device path. + CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDevicePathTemplate)); + Private->DevicePath.AcpiDevicePath.UID = 0; + Private->DevicePath.PciDevicePath.Device = DeviceId; + + // Copy protocol structure + CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate)); + + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEfiPciIoProtocolGuid, + &Private->PciIoProtocol, + &gEfiDevicePathProtocolGuid, + &Private->DevicePath, + NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PciInstallDevice InstallMultipleProtocolInterfaces () failed.\n")); + FreePool (Private->ConfigSpace); + FreePool (Private); + } + + return Status; +} + +EFI_STATUS +PciEmulationEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + BOOLEAN SuccessFlag; + UINT8 DeviceId; + UINTN ControllerAddr; + + DeviceId = 0; + + while (DeviceId < PcdGet32 (PcdNumUsbController)) { + ControllerAddr = PcdGet32 (PcdUsbBaseAddr) + (DeviceId * PcdGet32 (PcdUsbSize)); + Status = InitializeUsbController (ControllerAddr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USB HC initialization Failed for %d (0x%x)\n", + ControllerAddr, Status)); + continue; + } + + Status = PciInstallDevice (DeviceId, ControllerAddr, PcdGet32 (PcdUsbSize), + PCI_IF_XHCI, PCI_CLASS_SERIAL_USB, + PCI_CLASS_SERIAL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PciEmulation: failed to install USB %d device\n", DeviceId)); + } else { + SuccessFlag = TRUE; + } + DeviceId++; + } + + while (DeviceId < (PcdGet32 (PcdNumUsbController) + PcdGet32 (PcdNumSataController))) { + ControllerAddr = PcdGet32 (PcdSataBaseAddr) + + ((DeviceId - PcdGet32 (PcdNumUsbController)) * PcdGet32 (PcdSataSize)); + + Status = PciInstallDevice (DeviceId, ControllerAddr, PcdGet32 (PcdSataSize), + PCI_IF_MASS_STORAGE_SATA, PCI_CLASS_MASS_STORAGE_SATADPA, + PCI_CLASS_MASS_STORAGE); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PciEmulation: failed to install SATA %d device\n", + DeviceId - PcdGet32 (PcdNumUsbController))); + } else { + SuccessFlag = TRUE; + } + DeviceId++; + } + + if (SuccessFlag) { + return EFI_SUCCESS; + } else { + return Status; + } +} diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.h b/Platform/NXP/Drivers/PciEmulation/PciEmulation.h new file mode 100755 index 0000000..870d870 --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.h @@ -0,0 +1,306 @@ +/** PciEmulation.h + Provides all declararyion of PCI Root Bridge IO Protocol + + Reference taken from PCI Emulation implementation in + Omap35xxPkg/PciEmulation/ + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCI_EMULATION_H_ +#define _PCI_EMULATION_H_ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/Pci.h> +#include <IndustryStandard/Pci22.h> +#include <IndustryStandard/Pci30.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/DmaLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PciLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <PiDxe.h> +#include <Protocol/DevicePath.h> +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> +#include <Protocol/PciIo.h> +#include <Protocol/PciRootBridgeIo.h> + + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', '3') +#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'L') +#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE) +#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE) + + +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL +#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL + +#define HBA_GHC 0x04 +#define HBA_RESET 0x80000001 + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + + +#define ACPI_CONFIG_IO 0 +#define ACPI_CONFIG_MMIO 1 +#define ACPI_CONFIG_BUS 2 + +typedef struct { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3]; + EFI_ACPI_END_TAG_DESCRIPTOR EndDesc; +} ACPI_CONFIG_INFO; + + + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; + UINT8 StartBus; + UINT8 EndBus; + UINT16 Type; + UINT32 MemoryStart; + UINT32 MemorySize; + UINTN IoOffset; + UINT32 IoStart; + UINT32 IoSize; + UINT64 PciAttributes; + ACPI_CONFIG_INFO *Config; +} PCI_ROOT_BRIDGE; + + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + PCI_DEVICE_PATH PciDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_IO_DEVICE_PATH; + +typedef struct { + UINT32 Signature; + EFI_PCI_IO_DEVICE_PATH DevicePath; + EFI_PCI_IO_PROTOCOL PciIoProtocol; + PCI_TYPE00 *ConfigSpace; + PCI_ROOT_BRIDGE RootBridge; + UINTN Segment; +} EFI_PCI_IO_PRIVATE_DATA; + +// +// Driver Instance Data Prototypes +// + +typedef struct { + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; + UINTN NumberOfBytes; + UINTN NumberOfPages; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS MappedHostAddress; +} MAP_INFO; + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ); + +// +// Private Function Prototypes +// +// +EFI_STATUS +PciRootBridgeIoMemRW ( + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +BOOLEAN +PciIoMemAddressValid ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Address + ); + +EFI_STATUS +EFIAPI +InitializeUsbController ( + IN UINTN UsbReg + ); + +#endif diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf b/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf new file mode 100644 index 0000000..10fcb4b --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf @@ -0,0 +1,54 @@ +/* PciEmulation.inf +# Component description file for PCI Host Bridge driver +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +*/ + +[Defines] + INF_VERSION = 0x0001000A + BASE_NAME = PciEmulation + FILE_GUID = 196e7c2a-37b2-4b85-8683-7185c055fd5b + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciEmulationEntryPoint + +[Sources.common] + PciRootBridgeIo.c + PciEmulation.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DmaLib + UefiDriverEntryPoint + UsbHcdLibrary + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdSataSize + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController + +[Protocols] + gEfiPciRootBridgeIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + gEfiPciIoProtocolGuid + +[Depex] + TRUE diff --git a/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c b/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c new file mode 100644 index 0000000..4020cbe --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c @@ -0,0 +1,286 @@ +/** PciRootBridgeIo.c + PCI Root Bridge Io Protocol implementation + + Reference taken from PCI Emulation implementation in + Omap35xxPkg/PciEmulation/ + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciEmulation.h" + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mInStride[] = { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 0, // EfiPciWidthFifoUint8 + 0, // EfiPciWidthFifoUint16 + 0, // EfiPciWidthFifoUint32 + 0, // EfiPciWidthFifoUint64 + 1, // EfiPciWidthFillUint8 + 2, // EfiPciWidthFillUint16 + 4, // EfiPciWidthFillUint32 + 8 // EfiPciWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] = { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 1, // EfiPciWidthFifoUint8 + 2, // EfiPciWidthFifoUint16 + 4, // EfiPciWidthFifoUint32 + 8, // EfiPciWidthFifoUint64 + 0, // EfiPciWidthFillUint8 + 0, // EfiPciWidthFillUint16 + 0, // EfiPciWidthFillUint32 + 0 // EfiPciWidthFillUint64 +}; + + +BOOLEAN +PciRootBridgeMemAddressValid ( + IN PCI_ROOT_BRIDGE *Private, + IN UINT64 Address + ) +{ + if ((Address >= Private->MemoryStart) && + (Address < (Private->MemoryStart + Private->MemorySize))) { + return TRUE; + } + + return FALSE; +} + +EFI_STATUS +PciRootBridgeIoMemRW ( + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + break; + case EfiPciWidthUint16: + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + break; + case EfiPciWidthUint64: + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer = MmioRead8 ((UINTN)Address); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address); + break; + case EfiPciWidthUint64: + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + + if ( Buffer == NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + DEBUG ((DEBUG_ERROR, "READ ADDRESS is not valid: %llx\n", Address)); + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoMemRW (FALSE, Width, Address, Count, Buffer); + +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + + if ( Buffer == NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + DEBUG ((DEBUG_ERROR, "WRITE ADDRESS is not valid: %llx\n", Address)); + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoMemRW (TRUE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index fd07eee..f43ccf0 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -51,8 +51,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110 - gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32|0x00000111 - gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32|0x00000112 + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111 + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT64|0x00000113 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x00000114 gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64|0x00000115 @@ -246,3 +246,8 @@ # gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330 gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x0000331 + + # + # SATA Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000340 -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH edk2-platforms 3/3] SATA : Added SATA controller initialization driver. 2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 2/3] PciEmulation : Add support for Pci Emulation layer Meenakshi Aggarwal @ 2017-12-22 12:16 ` Meenakshi Aggarwal 2017-12-22 15:31 ` [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Ard Biesheuvel 2018-01-08 15:55 ` [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support Meenakshi Aggarwal 4 siblings, 0 replies; 21+ messages in thread From: Meenakshi Aggarwal @ 2017-12-22 12:16 UTC (permalink / raw) To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel Add driver to initialize SATA controller and apply any platform specific errata. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> --- Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 +++++++++++++++++++++++ Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++++++ Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++++++++ Platform/NXP/NxpQoriqLs.dec | 5 + Platform/NXP/NxpQoriqLs.dsc | 6 ++ 5 files changed, 208 insertions(+) create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c b/Platform/NXP/Drivers/SataInitDxe/SataInit.c new file mode 100644 index 0000000..4bda242 --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c @@ -0,0 +1,122 @@ +/** @file + This driver module performs initialization of SATA controller + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include <Library/BeIoLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/PciIo.h> + +#include "SataInit.h" + +/** + Write AHCI Operation register. + + @param PciIo The PCI IO protocol instance. + @param Offset The operation register offset. + @param Data The data used to write down. + +**/ +VOID +EFIAPI +AhciWriteReg ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Offset, + IN UINT32 Data + ) +{ + ASSERT (PciIo != NULL); + + PciIo->Mem.Write ( + PciIo, + EfiPciIoWidthUint32, + AHCI_BAR_INDEX, + (UINT64) Offset, + 1, + &Data + ); + + return; +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +InitializeSataController ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + + // + // Impact : The SATA controller does not detect some hard drives reliably with + // the default SerDes register setting. + // Workaround : write value 0x80104e20 to 0x1eb1300 (serdes 2) + // + if (PcdGetBool (PcdSataErratumA010554)) { + BeMmioWrite32 ((UINTN)SERDES2_SATA_ERRATA, 0x80104e20); + } + + // + // Impact : Device may see false CRC errors causing unreliable SATA operation. + // Workaround : write 0x80000000 to the address 0x20140520 (dcsr). + // + if (PcdGetBool (PcdSataErratumA010635)) { + BeMmioWrite32 ((UINTN)DCSR_SATA_ERRATA, 0x80000000); + } + + // + // Locate PCI I/O Protocol + // + Status = gBS->LocateProtocol (&gEfiPciIoProtocolGuid, NULL, (VOID **)&PciIo); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Sata controller is not able to find PCI Emulation 0x%x\n", + Status)); + return Status; + } + + // + // configuring Physical Control Layer parameters for Port 0 + // + AhciWriteReg (PciIo, SATA_PPCFG, PORT_PHYSICAL); + + // + // This register controls the configuration of the + // Transport Layer for Port 0 + // Errata Description : The default Rx watermark value may be insufficient for some + // hard drives and result in a false CRC or internal errors. + // Workaround: Change PTC[RXWM] field at offset 0xC8 to 0x29. Do not change + // the other reserved fields of the register. + // + + if (PcdGetBool (PcdSataErratumA009185)) { + AhciWriteReg (PciIo, SATA_PTC, PORT_RXWM); + } else { + AhciWriteReg (PciIo, SATA_PTC, PORT_TRANSPORT); + } + + return Status; +} diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.h b/Platform/NXP/Drivers/SataInitDxe/SataInit.h new file mode 100644 index 0000000..401173d --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.h @@ -0,0 +1,32 @@ +/** @file + Header file for Sata Controller initialization driver. + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#ifndef _SATA_INIT_H_ +#define _SATA_INIT_H_ + + +#define AHCI_BAR_INDEX 0x05 + +#define SATA_PPCFG 0xA8 +#define SATA_PTC 0xC8 + +#define PORT_PHYSICAL 0xA003FFFE +#define PORT_TRANSPORT 0x08000025 +#define PORT_RXWM 0x08000029 + +#define DCSR_SATA_ERRATA 0x20140520 +#define SERDES2_SATA_ERRATA 0x01eb1300 + +#endif diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf new file mode 100644 index 0000000..d06480f --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for the Sata Controller initialization driver +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x0001000A + BASE_NAME = SataInit + FILE_GUID = 021722D8-522B-4079-852A-FE44C2C13F49 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSataController + +[Sources] + SataInit.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BeIoLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635 + +[Protocols] + gEfiPciIoProtocolGuid diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index f43ccf0..bf4a086 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -82,6 +82,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000012D gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x00000130 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x00000131 # # DSPI Pcds @@ -155,6 +157,9 @@ gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x00000275 gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x00000276 gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000277 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|FALSE|BOOLEAN|0x00000278 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|FALSE|BOOLEAN|0x00000279 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA008402|FALSE|BOOLEAN|0x0000027A # # Test PCDs diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 9b450fa..6efa2a4 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -334,6 +334,12 @@ } # + # ATA Driver + # + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # # Architectural Protocols # ArmPkg/Drivers/CpuDxe/CpuDxe.inf -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal ` (2 preceding siblings ...) 2017-12-22 12:16 ` [PATCH edk2-platforms 3/3] SATA : Added SATA controller initialization driver Meenakshi Aggarwal @ 2017-12-22 15:31 ` Ard Biesheuvel 2018-01-04 11:27 ` Meenakshi Aggarwal 2018-01-08 15:55 ` [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support Meenakshi Aggarwal 4 siblings, 1 reply; 21+ messages in thread From: Ard Biesheuvel @ 2017-12-22 15:31 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 22 December 2017 at 12:16, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > Following patches add support for pci emulation layer > and SATA on NXP boards. > > Null Library for USB is also present to give completeness > to Pci Emulation layer. > > Meenakshi Aggarwal (3): > USB: Added Support of DWC3 USB controller. > PciEmulation : Add support for Pci Emulation layer. > SATA : Added SATA controller initialization driver. > Please don't add PCI emulation drivers. Instead, we have NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, UHCI, UFS, NVME and SDHCI platform devices. > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 +++++++++++++++++++++ > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + > Platform/NXP/NxpQoriqLs.dec | 14 +- > Platform/NXP/NxpQoriqLs.dsc | 15 + > 11 files changed, 1547 insertions(+), 2 deletions(-) > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c > create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c > create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf > > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2017-12-22 15:31 ` [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Ard Biesheuvel @ 2018-01-04 11:27 ` Meenakshi Aggarwal 2018-01-04 11:33 ` Ard Biesheuvel 0 siblings, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-04 11:27 UTC (permalink / raw) To: Ard Biesheuvel, star.zeng@intel.com, eric.dong@intel.com Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi Hi Ard, I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but on using this my SATA drive is not been detected by UEFI. Below is the reason of error: From EnumerateAttachedDevice() function AhciModeInitialization() function gets called. In AhciModeInitialization() under else loop i am receiving EFI_TIMEOUT from AhciIdentify() } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) { Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); if (EFI_ERROR (Status)) { REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); continue; } DeviceType = EfiIdeHarddisk; Then i check In AhciIdentify() function. Here, AhciPioTransfer() calls AhciCheckMemSet() to read PioFisReceived and D2hFisReceived. And AhciCheckMemSet() returns EFI_NOT_READY for both cases. So timeout occurs. I tried to compare PciEmulation layer and NonDiscoverablePciDeviceDxe but not able to find much difference. Please suggest what can possibly i am missing. > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Friday, December 22, 2017 9:02 PM > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA > support > > On 22 December 2017 at 12:16, Meenakshi Aggarwal > <meenakshi.aggarwal@nxp.com> wrote: > > Following patches add support for pci emulation layer > > and SATA on NXP boards. > > > > Null Library for USB is also present to give completeness > > to Pci Emulation layer. > > > > Meenakshi Aggarwal (3): > > USB: Added Support of DWC3 USB controller. > > PciEmulation : Add support for Pci Emulation layer. > > SATA : Added SATA controller initialization driver. > > > > Please don't add PCI emulation drivers. Instead, we have > NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, > UHCI, UFS, NVME and SDHCI platform devices. > > > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 > +++++++++++++++++++++ > > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ > > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ > > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ > > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ > > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ > > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ > > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + > > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + > > Platform/NXP/NxpQoriqLs.dec | 14 +- > > Platform/NXP/NxpQoriqLs.dsc | 15 + > > 11 files changed, 1547 insertions(+), 2 deletions(-) > > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c > > create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h > > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf > > create mode 100644 > Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c > > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > create mode 100644 > Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c > > create mode 100644 > Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf > > > > -- > > 1.9.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2018-01-04 11:27 ` Meenakshi Aggarwal @ 2018-01-04 11:33 ` Ard Biesheuvel 2018-01-04 12:56 ` Meenakshi Aggarwal 0 siblings, 1 reply; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-04 11:33 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: star.zeng@intel.com, eric.dong@intel.com, Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 4 January 2018 at 11:27, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > Hi Ard, > > > I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but on using this my SATA drive is not been detected by UEFI. > > Below is the reason of error: > > From EnumerateAttachedDevice() function AhciModeInitialization() function gets called. > > In AhciModeInitialization() under else loop i am receiving EFI_TIMEOUT from AhciIdentify() > > } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) { > Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); > > if (EFI_ERROR (Status)) { > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); > continue; > } > > DeviceType = EfiIdeHarddisk; > > Then i check In AhciIdentify() function. > Here, AhciPioTransfer() calls AhciCheckMemSet() to read PioFisReceived and D2hFisReceived. > And AhciCheckMemSet() returns EFI_NOT_READY for both cases. > So timeout occurs. > > I tried to compare PciEmulation layer and NonDiscoverablePciDeviceDxe but not able to find much difference. > > Please suggest what can possibly i am missing. > Does it work for XHCI? >> -----Original Message----- >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> Sent: Friday, December 22, 2017 9:02 PM >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA >> support >> >> On 22 December 2017 at 12:16, Meenakshi Aggarwal >> <meenakshi.aggarwal@nxp.com> wrote: >> > Following patches add support for pci emulation layer >> > and SATA on NXP boards. >> > >> > Null Library for USB is also present to give completeness >> > to Pci Emulation layer. >> > >> > Meenakshi Aggarwal (3): >> > USB: Added Support of DWC3 USB controller. >> > PciEmulation : Add support for Pci Emulation layer. >> > SATA : Added SATA controller initialization driver. >> > >> >> Please don't add PCI emulation drivers. Instead, we have >> NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, >> UHCI, UFS, NVME and SDHCI platform devices. >> >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 >> +++++++++++++++++++++ >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ >> > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + >> > Platform/NXP/NxpQoriqLs.dec | 14 +- >> > Platform/NXP/NxpQoriqLs.dsc | 15 + >> > 11 files changed, 1547 insertions(+), 2 deletions(-) >> > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c >> > create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h >> > create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf >> > create mode 100644 >> Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> > create mode 100644 >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c >> > create mode 100644 >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf >> > >> > -- >> > 1.9.1 >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2018-01-04 11:33 ` Ard Biesheuvel @ 2018-01-04 12:56 ` Meenakshi Aggarwal 2018-01-05 6:47 ` Meenakshi Aggarwal 0 siblings, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-04 12:56 UTC (permalink / raw) To: Ard Biesheuvel Cc: star.zeng@intel.com, eric.dong@intel.com, Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Thursday, January 04, 2018 5:03 PM > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm > <leif.lindholm@linaro.org>; Kinney, Michael D > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA > support > > On 4 January 2018 at 11:27, Meenakshi Aggarwal > <meenakshi.aggarwal@nxp.com> wrote: > > Hi Ard, > > > > > > I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but on > using this my SATA drive is not been detected by UEFI. > > > > Below is the reason of error: > > > > From EnumerateAttachedDevice() function AhciModeInitialization() > function gets called. > > > > In AhciModeInitialization() under else loop i am receiving EFI_TIMEOUT > from AhciIdentify() > > > > } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == > EFI_AHCI_ATA_DEVICE_SIG) { > > Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); > > > > if (EFI_ERROR (Status)) { > > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); > > continue; > > } > > > > DeviceType = EfiIdeHarddisk; > > > > Then i check In AhciIdentify() function. > > Here, AhciPioTransfer() calls AhciCheckMemSet() to read PioFisReceived > and D2hFisReceived. > > And AhciCheckMemSet() returns EFI_NOT_READY for both cases. > > So timeout occurs. > > > > I tried to compare PciEmulation layer and NonDiscoverablePciDeviceDxe > but not able to find much difference. > > > > Please suggest what can possibly i am missing. > > > > Does it work for XHCI? > I have not tried XHCI yet. > > >> -----Original Message----- > >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > >> Sent: Friday, December 22, 2017 9:02 PM > >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D > >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and > SATA > >> support > >> > >> On 22 December 2017 at 12:16, Meenakshi Aggarwal > >> <meenakshi.aggarwal@nxp.com> wrote: > >> > Following patches add support for pci emulation layer > >> > and SATA on NXP boards. > >> > > >> > Null Library for USB is also present to give completeness > >> > to Pci Emulation layer. > >> > > >> > Meenakshi Aggarwal (3): > >> > USB: Added Support of DWC3 USB controller. > >> > PciEmulation : Add support for Pci Emulation layer. > >> > SATA : Added SATA controller initialization driver. > >> > > >> > >> Please don't add PCI emulation drivers. Instead, we have > >> NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, > >> UHCI, UFS, NVME and SDHCI platform devices. > >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 > >> +++++++++++++++++++++ > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ > >> > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ > >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + > >> > Platform/NXP/NxpQoriqLs.dec | 14 +- > >> > Platform/NXP/NxpQoriqLs.dsc | 15 + > >> > 11 files changed, 1547 insertions(+), 2 deletions(-) > >> > create mode 100644 > Platform/NXP/Drivers/PciEmulation/PciEmulation.c > >> > create mode 100755 > Platform/NXP/Drivers/PciEmulation/PciEmulation.h > >> > create mode 100644 > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf > >> > create mode 100644 > >> Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > >> > create mode 100644 > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c > >> > create mode 100644 > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf > >> > > >> > -- > >> > 1.9.1 > >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2018-01-04 12:56 ` Meenakshi Aggarwal @ 2018-01-05 6:47 ` Meenakshi Aggarwal 2018-01-05 7:40 ` Ard Biesheuvel 0 siblings, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-05 6:47 UTC (permalink / raw) To: Ard Biesheuvel Cc: star.zeng@intel.com, eric.dong@intel.com, Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi Hi Ard, I tried NonDiscoverablePciDeviceDxe with Xhci today and unfortunately it also didnt work. I didnt debug it much but XhciInitializeDevice() and UsbEnumerateNewDev() is failing. XhcSetBiosOwnership: called to set BIOS ownership XhcResetHC! XhcInitSched:DCBAA=0xFE949000 XhcInitSched: Created CMD ring [FE949400~FE94A400) EVENT ring [FE94A400~FE94C400) InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC FE959038 XhcDriverBindingStart: XHCI started for controller @ FE9EBD98 InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D FE9D5020 XhcGetCapability: 2 ports, 64 bit 1 UsbRootHubInit: root hub FE9DB918 - max speed 3, 2 ports XhcClearRootHubPortFeature: status Success UsbEnumeratePort: port 0 state - 01, change - 01 on FE9DB918 UsbEnumeratePort: Device Connect/Disconnect Normally UsbEnumeratePort: new device connected at port 0 XhcUsbPortReset! XhcSetRootHubPortFeature: status Success XhcClearRootHubPortFeature: status Success XhcClearRootHubPortFeature: status Success Wait here for considerable amount of time, then it timeout. XhcInitializeDeviceSlot64: Enable Slot Failed, Status = Time out UsbEnumerateNewDev: hub port 0 is reset UsbEnumerateNewDev: device is of 2 speed UsbEnumerateNewDev: device uses translator (0, 0) XhcControlTransfer: error - Device Error, transfer - 100 UsbEnumerateNewDev: failed to set device address - Device Error Is there some fixed sequence which needs to be followed? Thanks, Meenakshi > -----Original Message----- > From: Meenakshi Aggarwal > Sent: Thursday, January 04, 2018 6:26 PM > To: 'Ard Biesheuvel' <ard.biesheuvel@linaro.org> > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm > <leif.lindholm@linaro.org>; Kinney, Michael D > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > Subject: RE: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA > support > > > > > -----Original Message----- > > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > > Sent: Thursday, January 04, 2018 5:03 PM > > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm > > <leif.lindholm@linaro.org>; Kinney, Michael D > > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and > SATA > > support > > > > On 4 January 2018 at 11:27, Meenakshi Aggarwal > > <meenakshi.aggarwal@nxp.com> wrote: > > > Hi Ard, > > > > > > > > > I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but on > > using this my SATA drive is not been detected by UEFI. > > > > > > Below is the reason of error: > > > > > > From EnumerateAttachedDevice() function AhciModeInitialization() > > function gets called. > > > > > > In AhciModeInitialization() under else loop i am receiving EFI_TIMEOUT > > from AhciIdentify() > > > > > > } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == > > EFI_AHCI_ATA_DEVICE_SIG) { > > > Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); > > > > > > if (EFI_ERROR (Status)) { > > > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > > (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); > > > continue; > > > } > > > > > > DeviceType = EfiIdeHarddisk; > > > > > > Then i check In AhciIdentify() function. > > > Here, AhciPioTransfer() calls AhciCheckMemSet() to read PioFisReceived > > and D2hFisReceived. > > > And AhciCheckMemSet() returns EFI_NOT_READY for both cases. > > > So timeout occurs. > > > > > > I tried to compare PciEmulation layer and NonDiscoverablePciDeviceDxe > > but not able to find much difference. > > > > > > Please suggest what can possibly i am missing. > > > > > > > Does it work for XHCI? > > > I have not tried XHCI yet. > > > > >> -----Original Message----- > > >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > > >> Sent: Friday, December 22, 2017 9:02 PM > > >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > > >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D > > >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > > >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > > >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and > > SATA > > >> support > > >> > > >> On 22 December 2017 at 12:16, Meenakshi Aggarwal > > >> <meenakshi.aggarwal@nxp.com> wrote: > > >> > Following patches add support for pci emulation layer > > >> > and SATA on NXP boards. > > >> > > > >> > Null Library for USB is also present to give completeness > > >> > to Pci Emulation layer. > > >> > > > >> > Meenakshi Aggarwal (3): > > >> > USB: Added Support of DWC3 USB controller. > > >> > PciEmulation : Add support for Pci Emulation layer. > > >> > SATA : Added SATA controller initialization driver. > > >> > > > >> > > >> Please don't add PCI emulation drivers. Instead, we have > > >> NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, > > >> UHCI, UFS, NVME and SDHCI platform devices. > > >> > > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 > > >> +++++++++++++++++++++ > > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 > ++++++++++ > > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ > > >> > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ > > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ > > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ > > >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ > > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + > > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + > > >> > Platform/NXP/NxpQoriqLs.dec | 14 +- > > >> > Platform/NXP/NxpQoriqLs.dsc | 15 + > > >> > 11 files changed, 1547 insertions(+), 2 deletions(-) > > >> > create mode 100644 > > Platform/NXP/Drivers/PciEmulation/PciEmulation.c > > >> > create mode 100755 > > Platform/NXP/Drivers/PciEmulation/PciEmulation.h > > >> > create mode 100644 > > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf > > >> > create mode 100644 > > >> Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c > > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > > >> > create mode 100644 > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > >> > create mode 100644 > > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c > > >> > create mode 100644 > > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf > > >> > > > >> > -- > > >> > 1.9.1 > > >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2018-01-05 6:47 ` Meenakshi Aggarwal @ 2018-01-05 7:40 ` Ard Biesheuvel 2018-01-05 8:53 ` Meenakshi Aggarwal 0 siblings, 1 reply; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-05 7:40 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: star.zeng@intel.com, eric.dong@intel.com, Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 5 January 2018 at 06:47, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > Hi Ard, > > I tried NonDiscoverablePciDeviceDxe with Xhci today and unfortunately it also didnt work. > > I didnt debug it much but XhciInitializeDevice() and UsbEnumerateNewDev() is failing. > Are you using the correct DMA type for your device? (coherent vs non-coherent) > > XhcSetBiosOwnership: called to set BIOS ownership > XhcResetHC! > XhcInitSched:DCBAA=0xFE949000 > XhcInitSched: Created CMD ring [FE949400~FE94A400) EVENT ring [FE94A400~FE94C400) > InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC FE959038 > XhcDriverBindingStart: XHCI started for controller @ FE9EBD98 > InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D FE9D5020 > XhcGetCapability: 2 ports, 64 bit 1 > UsbRootHubInit: root hub FE9DB918 - max speed 3, 2 ports > XhcClearRootHubPortFeature: status Success > UsbEnumeratePort: port 0 state - 01, change - 01 on FE9DB918 > UsbEnumeratePort: Device Connect/Disconnect Normally > UsbEnumeratePort: new device connected at port 0 > XhcUsbPortReset! > XhcSetRootHubPortFeature: status Success > XhcClearRootHubPortFeature: status Success > XhcClearRootHubPortFeature: status Success > > Wait here for considerable amount of time, then it timeout. > > XhcInitializeDeviceSlot64: Enable Slot Failed, Status = Time out > UsbEnumerateNewDev: hub port 0 is reset > UsbEnumerateNewDev: device is of 2 speed > UsbEnumerateNewDev: device uses translator (0, 0) > XhcControlTransfer: error - Device Error, transfer - 100 > UsbEnumerateNewDev: failed to set device address - Device Error > > > Is there some fixed sequence which needs to be followed? > > Thanks, > Meenakshi > >> -----Original Message----- >> From: Meenakshi Aggarwal >> Sent: Thursday, January 04, 2018 6:26 PM >> To: 'Ard Biesheuvel' <ard.biesheuvel@linaro.org> >> Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm >> <leif.lindholm@linaro.org>; Kinney, Michael D >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> Subject: RE: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA >> support >> >> >> >> > -----Original Message----- >> > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> > Sent: Thursday, January 04, 2018 5:03 PM >> > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm >> > <leif.lindholm@linaro.org>; Kinney, Michael D >> > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and >> SATA >> > support >> > >> > On 4 January 2018 at 11:27, Meenakshi Aggarwal >> > <meenakshi.aggarwal@nxp.com> wrote: >> > > Hi Ard, >> > > >> > > >> > > I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but on >> > using this my SATA drive is not been detected by UEFI. >> > > >> > > Below is the reason of error: >> > > >> > > From EnumerateAttachedDevice() function AhciModeInitialization() >> > function gets called. >> > > >> > > In AhciModeInitialization() under else loop i am receiving EFI_TIMEOUT >> > from AhciIdentify() >> > > >> > > } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == >> > EFI_AHCI_ATA_DEVICE_SIG) { >> > > Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); >> > > >> > > if (EFI_ERROR (Status)) { >> > > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, >> > (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); >> > > continue; >> > > } >> > > >> > > DeviceType = EfiIdeHarddisk; >> > > >> > > Then i check In AhciIdentify() function. >> > > Here, AhciPioTransfer() calls AhciCheckMemSet() to read PioFisReceived >> > and D2hFisReceived. >> > > And AhciCheckMemSet() returns EFI_NOT_READY for both cases. >> > > So timeout occurs. >> > > >> > > I tried to compare PciEmulation layer and NonDiscoverablePciDeviceDxe >> > but not able to find much difference. >> > > >> > > Please suggest what can possibly i am missing. >> > > >> > >> > Does it work for XHCI? >> > >> I have not tried XHCI yet. >> > >> > >> -----Original Message----- >> > >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> > >> Sent: Friday, December 22, 2017 9:02 PM >> > >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> > >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D >> > >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> > >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> > >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and >> > SATA >> > >> support >> > >> >> > >> On 22 December 2017 at 12:16, Meenakshi Aggarwal >> > >> <meenakshi.aggarwal@nxp.com> wrote: >> > >> > Following patches add support for pci emulation layer >> > >> > and SATA on NXP boards. >> > >> > >> > >> > Null Library for USB is also present to give completeness >> > >> > to Pci Emulation layer. >> > >> > >> > >> > Meenakshi Aggarwal (3): >> > >> > USB: Added Support of DWC3 USB controller. >> > >> > PciEmulation : Add support for Pci Emulation layer. >> > >> > SATA : Added SATA controller initialization driver. >> > >> > >> > >> >> > >> Please don't add PCI emulation drivers. Instead, we have >> > >> NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, >> > >> UHCI, UFS, NVME and SDHCI platform devices. >> > >> >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 >> > >> +++++++++++++++++++++ >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 >> ++++++++++ >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ >> > >> > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ >> > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + >> > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + >> > >> > Platform/NXP/NxpQoriqLs.dec | 14 +- >> > >> > Platform/NXP/NxpQoriqLs.dsc | 15 + >> > >> > 11 files changed, 1547 insertions(+), 2 deletions(-) >> > >> > create mode 100644 >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c >> > >> > create mode 100755 >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h >> > >> > create mode 100644 >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf >> > >> > create mode 100644 >> > >> Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c >> > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c >> > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h >> > >> > create mode 100644 >> Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> > >> > create mode 100644 >> > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c >> > >> > create mode 100644 >> > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf >> > >> > >> > >> > -- >> > >> > 1.9.1 >> > >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2018-01-05 7:40 ` Ard Biesheuvel @ 2018-01-05 8:53 ` Meenakshi Aggarwal 2018-01-05 9:16 ` Ard Biesheuvel 0 siblings, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-05 8:53 UTC (permalink / raw) To: Ard Biesheuvel Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Friday, January 05, 2018 1:11 PM > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm > <leif.lindholm@linaro.org>; Kinney, Michael D > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA > support > > On 5 January 2018 at 06:47, Meenakshi Aggarwal > <meenakshi.aggarwal@nxp.com> wrote: > > Hi Ard, > > > > I tried NonDiscoverablePciDeviceDxe with Xhci today and unfortunately it > also didnt work. > > > > I didnt debug it much but XhciInitializeDevice() and > UsbEnumerateNewDev() is failing. > > > > Are you using the correct DMA type for your device? (coherent vs non- > coherent) > I assumed i was but i was not :(. Correcting DMA type resolved the problem. Thanks a lot Ard. > > > > XhcSetBiosOwnership: called to set BIOS ownership > > XhcResetHC! > > XhcInitSched:DCBAA=0xFE949000 > > XhcInitSched: Created CMD ring [FE949400~FE94A400) EVENT ring > [FE94A400~FE94C400) > > InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC > FE959038 > > XhcDriverBindingStart: XHCI started for controller @ FE9EBD98 > > InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D > FE9D5020 > > XhcGetCapability: 2 ports, 64 bit 1 > > UsbRootHubInit: root hub FE9DB918 - max speed 3, 2 ports > > XhcClearRootHubPortFeature: status Success > > UsbEnumeratePort: port 0 state - 01, change - 01 on FE9DB918 > > UsbEnumeratePort: Device Connect/Disconnect Normally > > UsbEnumeratePort: new device connected at port 0 > > XhcUsbPortReset! > > XhcSetRootHubPortFeature: status Success > > XhcClearRootHubPortFeature: status Success > > XhcClearRootHubPortFeature: status Success > > > > Wait here for considerable amount of time, then it timeout. > > > > XhcInitializeDeviceSlot64: Enable Slot Failed, Status = Time out > > UsbEnumerateNewDev: hub port 0 is reset > > UsbEnumerateNewDev: device is of 2 speed > > UsbEnumerateNewDev: device uses translator (0, 0) > > XhcControlTransfer: error - Device Error, transfer - 100 > > UsbEnumerateNewDev: failed to set device address - Device Error > > > > > > Is there some fixed sequence which needs to be followed? > > > > Thanks, > > Meenakshi > > > >> -----Original Message----- > >> From: Meenakshi Aggarwal > >> Sent: Thursday, January 04, 2018 6:26 PM > >> To: 'Ard Biesheuvel' <ard.biesheuvel@linaro.org> > >> Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm > >> <leif.lindholm@linaro.org>; Kinney, Michael D > >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > >> Subject: RE: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and > SATA > >> support > >> > >> > >> > >> > -----Original Message----- > >> > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > >> > Sent: Thursday, January 04, 2018 5:03 PM > >> > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > >> > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm > >> > <leif.lindholm@linaro.org>; Kinney, Michael D > >> > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > >> > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and > >> SATA > >> > support > >> > > >> > On 4 January 2018 at 11:27, Meenakshi Aggarwal > >> > <meenakshi.aggarwal@nxp.com> wrote: > >> > > Hi Ard, > >> > > > >> > > > >> > > I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but > on > >> > using this my SATA drive is not been detected by UEFI. > >> > > > >> > > Below is the reason of error: > >> > > > >> > > From EnumerateAttachedDevice() function AhciModeInitialization() > >> > function gets called. > >> > > > >> > > In AhciModeInitialization() under else loop i am receiving > EFI_TIMEOUT > >> > from AhciIdentify() > >> > > > >> > > } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == > >> > EFI_AHCI_ATA_DEVICE_SIG) { > >> > > Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); > >> > > > >> > > if (EFI_ERROR (Status)) { > >> > > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > >> > (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); > >> > > continue; > >> > > } > >> > > > >> > > DeviceType = EfiIdeHarddisk; > >> > > > >> > > Then i check In AhciIdentify() function. > >> > > Here, AhciPioTransfer() calls AhciCheckMemSet() to read > PioFisReceived > >> > and D2hFisReceived. > >> > > And AhciCheckMemSet() returns EFI_NOT_READY for both cases. > >> > > So timeout occurs. > >> > > > >> > > I tried to compare PciEmulation layer and > NonDiscoverablePciDeviceDxe > >> > but not able to find much difference. > >> > > > >> > > Please suggest what can possibly i am missing. > >> > > > >> > > >> > Does it work for XHCI? > >> > > >> I have not tried XHCI yet. > >> > > >> > >> -----Original Message----- > >> > >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > >> > >> Sent: Friday, December 22, 2017 9:02 PM > >> > >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > >> > >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D > >> > >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > >> > >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > >> > >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation > and > >> > SATA > >> > >> support > >> > >> > >> > >> On 22 December 2017 at 12:16, Meenakshi Aggarwal > >> > >> <meenakshi.aggarwal@nxp.com> wrote: > >> > >> > Following patches add support for pci emulation layer > >> > >> > and SATA on NXP boards. > >> > >> > > >> > >> > Null Library for USB is also present to give completeness > >> > >> > to Pci Emulation layer. > >> > >> > > >> > >> > Meenakshi Aggarwal (3): > >> > >> > USB: Added Support of DWC3 USB controller. > >> > >> > PciEmulation : Add support for Pci Emulation layer. > >> > >> > SATA : Added SATA controller initialization driver. > >> > >> > > >> > >> > >> > >> Please don't add PCI emulation drivers. Instead, we have > >> > >> NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, > >> > >> UHCI, UFS, NVME and SDHCI platform devices. > >> > >> > >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 > >> > >> +++++++++++++++++++++ > >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 > >> ++++++++++ > >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ > >> > >> > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 > ++++++++++ > >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ > >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ > >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ > >> > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + > >> > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + > >> > >> > Platform/NXP/NxpQoriqLs.dec | 14 +- > >> > >> > Platform/NXP/NxpQoriqLs.dsc | 15 + > >> > >> > 11 files changed, 1547 insertions(+), 2 deletions(-) > >> > >> > create mode 100644 > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c > >> > >> > create mode 100755 > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h > >> > >> > create mode 100644 > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf > >> > >> > create mode 100644 > >> > >> Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c > >> > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > >> > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > >> > >> > create mode 100644 > >> Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > >> > >> > create mode 100644 > >> > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c > >> > >> > create mode 100644 > >> > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf > >> > >> > > >> > >> > -- > >> > >> > 1.9.1 > >> > >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support 2018-01-05 8:53 ` Meenakshi Aggarwal @ 2018-01-05 9:16 ` Ard Biesheuvel 0 siblings, 0 replies; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-05 9:16 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 5 January 2018 at 08:53, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > > >> -----Original Message----- >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> Sent: Friday, January 05, 2018 1:11 PM >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm >> <leif.lindholm@linaro.org>; Kinney, Michael D >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA >> support >> >> On 5 January 2018 at 06:47, Meenakshi Aggarwal >> <meenakshi.aggarwal@nxp.com> wrote: >> > Hi Ard, >> > >> > I tried NonDiscoverablePciDeviceDxe with Xhci today and unfortunately it >> also didnt work. >> > >> > I didnt debug it much but XhciInitializeDevice() and >> UsbEnumerateNewDev() is failing. >> > >> >> Are you using the correct DMA type for your device? (coherent vs non- >> coherent) >> > I assumed i was but i was not :(. > Correcting DMA type resolved the problem. Glad to hear that! >> > >> > XhcSetBiosOwnership: called to set BIOS ownership >> > XhcResetHC! >> > XhcInitSched:DCBAA=0xFE949000 >> > XhcInitSched: Created CMD ring [FE949400~FE94A400) EVENT ring >> [FE94A400~FE94C400) >> > InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC >> FE959038 >> > XhcDriverBindingStart: XHCI started for controller @ FE9EBD98 >> > InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D >> FE9D5020 >> > XhcGetCapability: 2 ports, 64 bit 1 >> > UsbRootHubInit: root hub FE9DB918 - max speed 3, 2 ports >> > XhcClearRootHubPortFeature: status Success >> > UsbEnumeratePort: port 0 state - 01, change - 01 on FE9DB918 >> > UsbEnumeratePort: Device Connect/Disconnect Normally >> > UsbEnumeratePort: new device connected at port 0 >> > XhcUsbPortReset! >> > XhcSetRootHubPortFeature: status Success >> > XhcClearRootHubPortFeature: status Success >> > XhcClearRootHubPortFeature: status Success >> > >> > Wait here for considerable amount of time, then it timeout. >> > >> > XhcInitializeDeviceSlot64: Enable Slot Failed, Status = Time out >> > UsbEnumerateNewDev: hub port 0 is reset >> > UsbEnumerateNewDev: device is of 2 speed >> > UsbEnumerateNewDev: device uses translator (0, 0) >> > XhcControlTransfer: error - Device Error, transfer - 100 >> > UsbEnumerateNewDev: failed to set device address - Device Error >> > >> > >> > Is there some fixed sequence which needs to be followed? >> > >> > Thanks, >> > Meenakshi >> > >> >> -----Original Message----- >> >> From: Meenakshi Aggarwal >> >> Sent: Thursday, January 04, 2018 6:26 PM >> >> To: 'Ard Biesheuvel' <ard.biesheuvel@linaro.org> >> >> Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm >> >> <leif.lindholm@linaro.org>; Kinney, Michael D >> >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> >> Subject: RE: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and >> SATA >> >> support >> >> >> >> >> >> >> >> > -----Original Message----- >> >> > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> >> > Sent: Thursday, January 04, 2018 5:03 PM >> >> > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> >> > Cc: star.zeng@intel.com; eric.dong@intel.com; Leif Lindholm >> >> > <leif.lindholm@linaro.org>; Kinney, Michael D >> >> > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> >> > Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and >> >> SATA >> >> > support >> >> > >> >> > On 4 January 2018 at 11:27, Meenakshi Aggarwal >> >> > <meenakshi.aggarwal@nxp.com> wrote: >> >> > > Hi Ard, >> >> > > >> >> > > >> >> > > I tried using NonDiscoverablePciDeviceDxe driver for SATA (AHCI), but >> on >> >> > using this my SATA drive is not been detected by UEFI. >> >> > > >> >> > > Below is the reason of error: >> >> > > >> >> > > From EnumerateAttachedDevice() function AhciModeInitialization() >> >> > function gets called. >> >> > > >> >> > > In AhciModeInitialization() under else loop i am receiving >> EFI_TIMEOUT >> >> > from AhciIdentify() >> >> > > >> >> > > } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == >> >> > EFI_AHCI_ATA_DEVICE_SIG) { >> >> > > Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer); >> >> > > >> >> > > if (EFI_ERROR (Status)) { >> >> > > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, >> >> > (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED)); >> >> > > continue; >> >> > > } >> >> > > >> >> > > DeviceType = EfiIdeHarddisk; >> >> > > >> >> > > Then i check In AhciIdentify() function. >> >> > > Here, AhciPioTransfer() calls AhciCheckMemSet() to read >> PioFisReceived >> >> > and D2hFisReceived. >> >> > > And AhciCheckMemSet() returns EFI_NOT_READY for both cases. >> >> > > So timeout occurs. >> >> > > >> >> > > I tried to compare PciEmulation layer and >> NonDiscoverablePciDeviceDxe >> >> > but not able to find much difference. >> >> > > >> >> > > Please suggest what can possibly i am missing. >> >> > > >> >> > >> >> > Does it work for XHCI? >> >> > >> >> I have not tried XHCI yet. >> >> > >> >> > >> -----Original Message----- >> >> > >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> >> > >> Sent: Friday, December 22, 2017 9:02 PM >> >> > >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> >> > >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D >> >> > >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> >> > >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> >> > >> Subject: Re: [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation >> and >> >> > SATA >> >> > >> support >> >> > >> >> >> > >> On 22 December 2017 at 12:16, Meenakshi Aggarwal >> >> > >> <meenakshi.aggarwal@nxp.com> wrote: >> >> > >> > Following patches add support for pci emulation layer >> >> > >> > and SATA on NXP boards. >> >> > >> > >> >> > >> > Null Library for USB is also present to give completeness >> >> > >> > to Pci Emulation layer. >> >> > >> > >> >> > >> > Meenakshi Aggarwal (3): >> >> > >> > USB: Added Support of DWC3 USB controller. >> >> > >> > PciEmulation : Add support for Pci Emulation layer. >> >> > >> > SATA : Added SATA controller initialization driver. >> >> > >> > >> >> > >> >> >> > >> Please don't add PCI emulation drivers. Instead, we have >> >> > >> NonDiscoverablePciDeviceDxe that supports AHCI, XHCI, EHCI, OHCI, >> >> > >> UHCI, UFS, NVME and SDHCI platform devices. >> >> > >> >> >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 >> >> > >> +++++++++++++++++++++ >> >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 >> >> ++++++++++ >> >> > >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ >> >> > >> > .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 >> ++++++++++ >> >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ >> >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ >> >> > >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ >> >> > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + >> >> > >> > .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + >> >> > >> > Platform/NXP/NxpQoriqLs.dec | 14 +- >> >> > >> > Platform/NXP/NxpQoriqLs.dsc | 15 + >> >> > >> > 11 files changed, 1547 insertions(+), 2 deletions(-) >> >> > >> > create mode 100644 >> >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.c >> >> > >> > create mode 100755 >> >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.h >> >> > >> > create mode 100644 >> >> > Platform/NXP/Drivers/PciEmulation/PciEmulation.inf >> >> > >> > create mode 100644 >> >> > >> Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c >> >> > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c >> >> > >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h >> >> > >> > create mode 100644 >> >> Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> >> > >> > create mode 100644 >> >> > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c >> >> > >> > create mode 100644 >> >> > >> Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf >> >> > >> > >> >> > >> > -- >> >> > >> > 1.9.1 >> >> > >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support 2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal ` (3 preceding siblings ...) 2017-12-22 15:31 ` [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Ard Biesheuvel @ 2018-01-08 15:55 ` Meenakshi Aggarwal 2018-01-08 15:55 ` [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver Meenakshi Aggarwal 2018-01-08 15:55 ` [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller Meenakshi Aggarwal 4 siblings, 2 replies; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-08 15:55 UTC (permalink / raw) To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel V2: 1. Pci Emulation layer removed. 2. Made SATA driver as NonDiscoverablePciDevice. 3. Add support of SATA on LS1046RDB board. Meenakshi Aggarwal (2): SATA : Added SATA controller driver. LS1046 : Enable support of SATA controller Platform/NXP/Drivers/SataInitDxe/SataInit.c | 285 +++++++++++++++++++++ Platform/NXP/Drivers/SataInitDxe/SataInit.h | 36 +++ Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 52 ++++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 8 + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12 + .../Library/PlatformLib/ArmPlatformLib.inf | 2 + .../Library/PlatformLib/NxpQoriqLsMem.c | 8 + Platform/NXP/NxpQoriqLs.dec | 14 +- Platform/NXP/NxpQoriqLs.dsc | 13 + Silicon/NXP/LS1046A/LS1046A.dsc | 5 + 10 files changed, 433 insertions(+), 2 deletions(-) create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf V1 : Following patches add support for pci emulation layer and SATA on NXP boards. Null Library for USB is also present to give completeness to Pci Emulation layer. Meenakshi Aggarwal (3): USB: Added Support of DWC3 USB controller. PciEmulation : Add support for Pci Emulation layer. SATA : Added SATA controller initialization driver. Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 +++++++++++++++++++++ Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 ++++ Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++ Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++ .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 + .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 + Platform/NXP/NxpQoriqLs.dec | 14 +- Platform/NXP/NxpQoriqLs.dsc | 15 + 11 files changed, 1547 insertions(+), 2 deletions(-) create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary -- 1.9.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver. 2018-01-08 15:55 ` [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support Meenakshi Aggarwal @ 2018-01-08 15:55 ` Meenakshi Aggarwal 2018-01-08 15:05 ` Ard Biesheuvel 2018-01-08 15:55 ` [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller Meenakshi Aggarwal 1 sibling, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-08 15:55 UTC (permalink / raw) To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel This patch adds support of SATA controller, which Initialize SATA controller, apply platform specific errata and Register itself as NonDiscoverableMmioDevice Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> --- Platform/NXP/Drivers/SataInitDxe/SataInit.c | 285 +++++++++++++++++++++++ Platform/NXP/Drivers/SataInitDxe/SataInit.h | 36 +++ Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 52 +++++ Platform/NXP/NxpQoriqLs.dec | 14 +- Platform/NXP/NxpQoriqLs.dsc | 13 ++ 5 files changed, 398 insertions(+), 2 deletions(-) create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c b/Platform/NXP/Drivers/SataInitDxe/SataInit.c new file mode 100644 index 0000000..bac390b --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c @@ -0,0 +1,285 @@ +/** @file + This driver module adds SATA controller support. + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include <IndustryStandard/Pci.h> +#include <Library/BeIoLib.h> +#include <Library/DebugLib.h> +#include <Library/NonDiscoverableDeviceRegistrationLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Protocol/PciIo.h> + +#include "SataInit.h" + +STATIC VOID *mDriverEventRegistration; + +/** + Read AHCI Operation register. + + @param PciIo The PCI IO protocol instance. + @param Offset The operation register offset. + + @return The register content read. +**/ + +UINT32 +EFIAPI +AhciReadReg ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Offset + ) +{ + UINT32 Data; + + ASSERT (PciIo != NULL); + + Data = 0; + + PciIo->Mem.Read ( + PciIo, + EfiPciIoWidthUint32, + AHCI_BAR_INDEX, + (UINT64) Offset, + 1, + &Data + ); + + return Data; +} + +/** + Write AHCI Operation register. + + @param PciIo The PCI IO protocol instance. + @param Offset The operation register offset. + @param Data The data used to write down. + +**/ +VOID +EFIAPI +AhciWriteReg ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Offset, + IN UINT32 Data + ) +{ + ASSERT (PciIo != NULL); + + PciIo->Mem.Write ( + PciIo, + EfiPciIoWidthUint32, + AHCI_BAR_INDEX, + (UINT64) Offset, + 1, + &Data + ); + + return; +} + +STATIC +VOID +PciIoRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINTN HandleCount; + UINTN Address; + UINT32 Count; + UINT32 Data; + UINT8 PciClass; + UINT8 PciSubClass; + EFI_PCI_IO_PROTOCOL *PciIo; + EFI_HANDLE *HandleBuf; + + PciIo = NULL; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuf); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Sata controller is not able to locate gEfiPciIoProtocolGuid 0x%x\n", + Status)); + return; + } + + for (Count = 0; Count < HandleCount; Count++) { + Status = gBS->OpenProtocol ( + HandleBuf[Count], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo, + NULL, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + continue; + } + + // + // Now further check the PCI header: Base class (offset 0x0B) and + // Sub Class (offset 0x0A). This controller should be an Ide controller + // + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + PCI_CLASSCODE_OFFSET + 2, + 1, + &PciClass + ); + if (EFI_ERROR (Status)) { + continue; + } + + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + PCI_CLASSCODE_OFFSET + 1, + 1, + &PciSubClass + ); + if (EFI_ERROR (Status)) { + continue; + } + + // + // Examine Ide PCI Configuration table fields + // + if ((PciClass != PCI_CLASS_MASS_STORAGE) || + (PciSubClass != PCI_CLASS_MASS_STORAGE_SATADPA)) { + continue; + } + + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + PCI_AHCI_BASE_ADDRESS, + 1, + &Address + ); + if (EFI_ERROR (Status)) { + continue; + } else if (Address == (UINTN)Context) { + gBS->CloseEvent (Event); + + // + // configuring Physical Control Layer parameters for Port 0 + // + AhciWriteReg (PciIo, SATA_PPCFG, PORT_PHYSICAL); + + // + // This register controls the configuration of the + // Transport Layer for Port 0 + // Errata Description : The default Rx watermark value may be insufficient for some + // hard drives and result in a false CRC or internal errors. + // Workaround: Change PTC[RXWM] field at offset 0xC8 to 0x29. Do not change + // the other reserved fields of the register. + // + + Data = AhciReadReg (PciIo, SATA_PTC); + if (PcdGetBool (PcdSataErratumA009185)) { + Data |= PORT_RXWM; + } else { + Data |= PORT_TRANSPORT; + } + AhciWriteReg (PciIo, SATA_PTC, Data); + + break; + } + } + + gBS->FreePool (HandleBuf); + + return; +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +InitializeSataController ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 NumSataController; + UINTN ControllerAddr; + + Status = EFI_SUCCESS; + NumSataController = PcdGet32 (PcdNumSataController); + + // + // Impact : The SATA controller does not detect some hard drives reliably with + // the default SerDes register setting. + // Workaround : write value 0x80104e20 to 0x1eb1300 (serdes 2) + // + if (PcdGetBool (PcdSataErratumA010554)) { + BeMmioWrite32 ((UINTN)SERDES2_SATA_ERRATA, 0x80104e20); + } + + // + // Impact : Device may see false CRC errors causing unreliable SATA operation. + // Workaround : write 0x80000000 to the address 0x20140520 (dcsr). + // + if (PcdGetBool (PcdSataErratumA010635)) { + BeMmioWrite32 ((UINTN)DCSR_SATA_ERRATA, 0x80000000); + } + + while (NumSataController) { + NumSataController--; + ControllerAddr = PcdGet32 (PcdSataBaseAddr) + + (NumSataController * PcdGet32 (PcdSataSize)); + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeAhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + ControllerAddr, PcdGet32 (PcdSataSize) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register SATA device (0x%x) with error 0x%x \n", + ControllerAddr, Status)); + } else { + // + // Register a protocol registration notification callback on the driver + // binding protocol so we can attempt to connect to it as soon as it appears. + // + EfiCreateProtocolNotifyEvent ( + &gEfiPciIoProtocolGuid, + TPL_CALLBACK, + PciIoRegistrationEvent, + (VOID *)ControllerAddr, + &mDriverEventRegistration); + } + } + + return Status; +} diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.h b/Platform/NXP/Drivers/SataInitDxe/SataInit.h new file mode 100644 index 0000000..7fe6273 --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.h @@ -0,0 +1,36 @@ +/** @file + Header file for Sata Controller initialization driver. + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#ifndef _SATA_INIT_H_ +#define _SATA_INIT_H_ + + +#define AHCI_BAR_INDEX 0x05 +// +// Offset for AHCI base address in PCI Header +// +#define PCI_AHCI_BASE_ADDRESS 0x24 + +#define SATA_PPCFG 0xA8 +#define SATA_PTC 0xC8 + +#define PORT_PHYSICAL 0xA003FFFE +#define PORT_TRANSPORT 0x08000025 +#define PORT_RXWM 0x08000029 + +#define DCSR_SATA_ERRATA 0x20140520 +#define SERDES2_SATA_ERRATA 0x01eb1300 + +#endif diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf new file mode 100644 index 0000000..82535f4 --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf @@ -0,0 +1,52 @@ +## @file +# Component description file for the Sata Controller initialization driver +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x0001000A + BASE_NAME = SataInit + FILE_GUID = 021722D8-522B-4079-852A-FE44C2C13F49 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSataController + +[Sources] + SataInit.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BeIoLib + DebugLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdSataSize + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635 + +[Protocols] + gEfiPciIoProtocolGuid + +[Depex] + TRUE diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index bd4273f..65d659e 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -52,8 +52,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110 - gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32|0x00000111 - gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32|0x00000112 + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111 + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT64|0x00000113 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x00000114 gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64|0x00000115 @@ -83,6 +83,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000012D gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x00000130 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x00000131 # # DSPI Pcds @@ -156,6 +158,9 @@ gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x00000275 gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x00000276 gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000277 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|FALSE|BOOLEAN|0x00000278 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|FALSE|BOOLEAN|0x00000279 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA008402|FALSE|BOOLEAN|0x0000027A # # Test PCDs @@ -249,3 +254,8 @@ # gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330 gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x0000331 + + # + # SATA Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000340 diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 10eff06..c3c0eb1 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -99,6 +99,8 @@ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf @@ -144,6 +146,7 @@ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [LibraryClasses.common.UEFI_APPLICATION] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -334,6 +337,16 @@ } # + # AHCI Support + # + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # # Architectural Protocols # ArmPkg/Drivers/CpuDxe/CpuDxe.inf -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver. 2018-01-08 15:55 ` [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver Meenakshi Aggarwal @ 2018-01-08 15:05 ` Ard Biesheuvel 2018-01-09 4:50 ` Meenakshi Aggarwal 0 siblings, 1 reply; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-08 15:05 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi Hi Meenakshi, This is looking much better - thanks for rewriting it. I do have some comments below On 8 January 2018 at 15:55, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > This patch adds support of SATA controller, which > Initialize SATA controller, > apply platform specific errata and > Register itself as NonDiscoverableMmioDevice > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > --- > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 285 +++++++++++++++++++++++ > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 36 +++ > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 52 +++++ > Platform/NXP/NxpQoriqLs.dec | 14 +- > Platform/NXP/NxpQoriqLs.dsc | 13 ++ > 5 files changed, 398 insertions(+), 2 deletions(-) > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c b/Platform/NXP/Drivers/SataInitDxe/SataInit.c > new file mode 100644 > index 0000000..bac390b > --- /dev/null > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c > @@ -0,0 +1,285 @@ > +/** @file > + This driver module adds SATA controller support. > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > + **/ > + > +#include <IndustryStandard/Pci.h> > +#include <Library/BeIoLib.h> > +#include <Library/DebugLib.h> > +#include <Library/NonDiscoverableDeviceRegistrationLib.h> > +#include <Library/UefiBootServicesTableLib.h> > +#include <Library/UefiLib.h> > +#include <Protocol/PciIo.h> > + > +#include "SataInit.h" > + > +STATIC VOID *mDriverEventRegistration; > + > +/** > + Read AHCI Operation register. > + > + @param PciIo The PCI IO protocol instance. > + @param Offset The operation register offset. > + > + @return The register content read. > +**/ > + > +UINT32 > +EFIAPI > +AhciReadReg ( > + IN EFI_PCI_IO_PROTOCOL *PciIo, > + IN UINT32 Offset > + ) > +{ > + UINT32 Data; > + > + ASSERT (PciIo != NULL); > + > + Data = 0; > + > + PciIo->Mem.Read ( > + PciIo, > + EfiPciIoWidthUint32, > + AHCI_BAR_INDEX, > + (UINT64) Offset, > + 1, > + &Data > + ); > + > + return Data; > +} > + > +/** > + Write AHCI Operation register. > + > + @param PciIo The PCI IO protocol instance. > + @param Offset The operation register offset. > + @param Data The data used to write down. > + > +**/ > +VOID > +EFIAPI > +AhciWriteReg ( > + IN EFI_PCI_IO_PROTOCOL *PciIo, > + IN UINT32 Offset, > + IN UINT32 Data > + ) > +{ > + ASSERT (PciIo != NULL); > + > + PciIo->Mem.Write ( > + PciIo, > + EfiPciIoWidthUint32, > + AHCI_BAR_INDEX, > + (UINT64) Offset, > + 1, > + &Data > + ); > + > + return; > +} > + > +STATIC > +VOID > +PciIoRegistrationEvent ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ) > +{ > + EFI_STATUS Status; > + UINTN HandleCount; > + UINTN Address; > + UINT32 Count; > + UINT32 Data; > + UINT8 PciClass; > + UINT8 PciSubClass; > + EFI_PCI_IO_PROTOCOL *PciIo; > + EFI_HANDLE *HandleBuf; > + > + PciIo = NULL; > + > + Status = gBS->LocateHandleBuffer ( > + ByProtocol, > + &gEfiPciIoProtocolGuid, > + NULL, > + &HandleCount, > + &HandleBuf); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Sata controller is not able to locate gEfiPciIoProtocolGuid 0x%x\n", > + Status)); > + return; > + } > + > + for (Count = 0; Count < HandleCount; Count++) { > + Status = gBS->OpenProtocol ( > + HandleBuf[Count], > + &gEfiPciIoProtocolGuid, > + (VOID **) &PciIo, > + NULL, > + NULL, > + EFI_OPEN_PROTOCOL_GET_PROTOCOL); > + if (EFI_ERROR (Status)) { > + continue; > + } > + > + // > + // Now further check the PCI header: Base class (offset 0x0B) and > + // Sub Class (offset 0x0A). This controller should be an Ide controller > + // > + Status = PciIo->Pci.Read ( > + PciIo, > + EfiPciIoWidthUint8, > + PCI_CLASSCODE_OFFSET + 2, > + 1, > + &PciClass > + ); > + if (EFI_ERROR (Status)) { > + continue; > + } > + > + Status = PciIo->Pci.Read ( > + PciIo, > + EfiPciIoWidthUint8, > + PCI_CLASSCODE_OFFSET + 1, > + 1, > + &PciSubClass > + ); > + if (EFI_ERROR (Status)) { > + continue; > + } > + > + // > + // Examine Ide PCI Configuration table fields > + // > + if ((PciClass != PCI_CLASS_MASS_STORAGE) || > + (PciSubClass != PCI_CLASS_MASS_STORAGE_SATADPA)) { > + continue; > + } > + > + Status = PciIo->Pci.Read ( > + PciIo, > + EfiPciIoWidthUint32, > + PCI_AHCI_BASE_ADDRESS, > + 1, > + &Address > + ); > + if (EFI_ERROR (Status)) { > + continue; > + } else if (Address == (UINTN)Context) { > + gBS->CloseEvent (Event); > + > + // > + // configuring Physical Control Layer parameters for Port 0 > + // > + AhciWriteReg (PciIo, SATA_PPCFG, PORT_PHYSICAL); > + > + // > + // This register controls the configuration of the > + // Transport Layer for Port 0 > + // Errata Description : The default Rx watermark value may be insufficient for some > + // hard drives and result in a false CRC or internal errors. > + // Workaround: Change PTC[RXWM] field at offset 0xC8 to 0x29. Do not change > + // the other reserved fields of the register. > + // > + > + Data = AhciReadReg (PciIo, SATA_PTC); > + if (PcdGetBool (PcdSataErratumA009185)) { > + Data |= PORT_RXWM; > + } else { > + Data |= PORT_TRANSPORT; > + } > + AhciWriteReg (PciIo, SATA_PTC, Data); > + > + break; > + } > + } > + > + gBS->FreePool (HandleBuf); > + > + return; > +} > + > +/** > + The Entry Point of module. It follows the standard UEFI driver model. > + > + @param[in] ImageHandle The firmware allocated handle for the EFI image. > + @param[in] SystemTable A pointer to the EFI System Table. > + > + @retval EFI_SUCCESS The entry point is executed successfully. > + @retval other Some error occurs when executing this entry point. > + > +**/ > +EFI_STATUS > +EFIAPI > +InitializeSataController ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + EFI_STATUS Status; > + UINT32 NumSataController; > + UINTN ControllerAddr; > + > + Status = EFI_SUCCESS; > + NumSataController = PcdGet32 (PcdNumSataController); > + > + // > + // Impact : The SATA controller does not detect some hard drives reliably with > + // the default SerDes register setting. > + // Workaround : write value 0x80104e20 to 0x1eb1300 (serdes 2) > + // > + if (PcdGetBool (PcdSataErratumA010554)) { > + BeMmioWrite32 ((UINTN)SERDES2_SATA_ERRATA, 0x80104e20); > + } > + > + // > + // Impact : Device may see false CRC errors causing unreliable SATA operation. > + // Workaround : write 0x80000000 to the address 0x20140520 (dcsr). > + // > + if (PcdGetBool (PcdSataErratumA010635)) { > + BeMmioWrite32 ((UINTN)DCSR_SATA_ERRATA, 0x80000000); > + } > + > + while (NumSataController) { > + NumSataController--; > + ControllerAddr = PcdGet32 (PcdSataBaseAddr) + > + (NumSataController * PcdGet32 (PcdSataSize)); > + > + Status = RegisterNonDiscoverableMmioDevice ( > + NonDiscoverableDeviceTypeAhci, > + NonDiscoverableDeviceDmaTypeNonCoherent, > + NULL, > + NULL, > + 1, > + ControllerAddr, PcdGet32 (PcdSataSize) > + ); > + > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed to register SATA device (0x%x) with error 0x%x \n", > + ControllerAddr, Status)); Please don't use if/else for the expected path: instead, return here or goto the error/unwind code at the end of the function > + } else { > + // > + // Register a protocol registration notification callback on the driver > + // binding protocol so we can attempt to connect to it as soon as it appears. > + // > + EfiCreateProtocolNotifyEvent ( > + &gEfiPciIoProtocolGuid, > + TPL_CALLBACK, > + PciIoRegistrationEvent, > + (VOID *)ControllerAddr, > + &mDriverEventRegistration); What is the point of this? AhciReadReg()/AhciWriteReg() can access ControllerAddr directly, so there is no reason to go through the PCI I/O protocol. > + } > + } > + > + return Status; > +} > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.h b/Platform/NXP/Drivers/SataInitDxe/SataInit.h > new file mode 100644 > index 0000000..7fe6273 > --- /dev/null > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.h > @@ -0,0 +1,36 @@ > +/** @file > + Header file for Sata Controller initialization driver. > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > + **/ > + > +#ifndef _SATA_INIT_H_ > +#define _SATA_INIT_H_ > + > + > +#define AHCI_BAR_INDEX 0x05 > +// > +// Offset for AHCI base address in PCI Header > +// > +#define PCI_AHCI_BASE_ADDRESS 0x24 > + > +#define SATA_PPCFG 0xA8 > +#define SATA_PTC 0xC8 > + > +#define PORT_PHYSICAL 0xA003FFFE > +#define PORT_TRANSPORT 0x08000025 > +#define PORT_RXWM 0x08000029 > + > +#define DCSR_SATA_ERRATA 0x20140520 > +#define SERDES2_SATA_ERRATA 0x01eb1300 > + > +#endif > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > new file mode 100644 > index 0000000..82535f4 > --- /dev/null > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > @@ -0,0 +1,52 @@ > +## @file > +# Component description file for the Sata Controller initialization driver > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001000A > + BASE_NAME = SataInit > + FILE_GUID = 021722D8-522B-4079-852A-FE44C2C13F49 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + ENTRY_POINT = InitializeSataController > + > +[Sources] > + SataInit.c > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + Platform/NXP/NxpQoriqLs.dec > + > +[LibraryClasses] > + BeIoLib > + DebugLib > + NonDiscoverableDeviceRegistrationLib > + UefiBootServicesTableLib > + UefiDriverEntryPoint > + UefiLib > + > +[FixedPcd] > + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController > + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554 > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635 > + > +[Protocols] > + gEfiPciIoProtocolGuid > + > +[Depex] > + TRUE > diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec > index bd4273f..65d659e 100644 > --- a/Platform/NXP/NxpQoriqLs.dec > +++ b/Platform/NXP/NxpQoriqLs.dec > @@ -52,8 +52,8 @@ > gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E > gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F > gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110 > - gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32|0x00000111 > - gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32|0x00000112 > + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111 > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112 > gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT64|0x00000113 > gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x00000114 > gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64|0x00000115 > @@ -83,6 +83,8 @@ > gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000012D > gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E > gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x00000130 > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x00000131 > > # > # DSPI Pcds > @@ -156,6 +158,9 @@ > gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x00000275 > gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x00000276 > gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000277 > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|FALSE|BOOLEAN|0x00000278 > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|FALSE|BOOLEAN|0x00000279 > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA008402|FALSE|BOOLEAN|0x0000027A > > # > # Test PCDs > @@ -249,3 +254,8 @@ > # > gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330 > gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x0000331 > + > + # > + # SATA Pcds > + # > + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000340 > diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc > index 10eff06..c3c0eb1 100644 > --- a/Platform/NXP/NxpQoriqLs.dsc > +++ b/Platform/NXP/NxpQoriqLs.dsc > @@ -99,6 +99,8 @@ > VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf > NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf > CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf > + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf > + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf > > [LibraryClasses.common.SEC] > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > @@ -144,6 +146,7 @@ > SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf > PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf > MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf > + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf > Why do you need to add this twice? > [LibraryClasses.common.UEFI_APPLICATION] > PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > @@ -334,6 +337,16 @@ > } > > # > + # AHCI Support > + # > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf > + > + # > # Architectural Protocols > # > ArmPkg/Drivers/CpuDxe/CpuDxe.inf > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver. 2018-01-08 15:05 ` Ard Biesheuvel @ 2018-01-09 4:50 ` Meenakshi Aggarwal 2018-01-09 8:26 ` Ard Biesheuvel 0 siblings, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-09 4:50 UTC (permalink / raw) To: Ard Biesheuvel Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Monday, January 08, 2018 8:35 PM > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller > driver. > > Hi Meenakshi, > > This is looking much better - thanks for rewriting it. I do have some > comments below > > On 8 January 2018 at 15:55, Meenakshi Aggarwal > <meenakshi.aggarwal@nxp.com> wrote: > > This patch adds support of SATA controller, which > > Initialize SATA controller, > > apply platform specific errata and > > Register itself as NonDiscoverableMmioDevice > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > > --- > > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 285 > +++++++++++++++++++++++ > > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 36 +++ > > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 52 +++++ > > Platform/NXP/NxpQoriqLs.dec | 14 +- > > Platform/NXP/NxpQoriqLs.dsc | 13 ++ > > 5 files changed, 398 insertions(+), 2 deletions(-) > > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c > > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h > > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > > > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c > b/Platform/NXP/Drivers/SataInitDxe/SataInit.c > > new file mode 100644 > > index 0000000..bac390b > > --- /dev/null > > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c > > @@ -0,0 +1,285 @@ > > +/** @file > > + This driver module adds SATA controller support. > > + > > + Copyright 2017 NXP > > + > > + This program and the accompanying materials > > + are licensed and made available under the terms and conditions of the > BSD License > > + which accompanies this distribution. The full text of the license may be > found > > + > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope > nsource.org%2Flicenses%2Fbsd- > license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1bf888 > dbc6b34f8646fe08d556a93d5a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 > %7C0%7C636510207254570536&sdata=hU2o5igZuy5SDt5emEUmAqhSn1gW9 > H40OgvmH8gMn9k%3D&reserved=0 > > + > > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > > + > > + **/ > > + > > +#include <IndustryStandard/Pci.h> > > +#include <Library/BeIoLib.h> > > +#include <Library/DebugLib.h> > > +#include <Library/NonDiscoverableDeviceRegistrationLib.h> > > +#include <Library/UefiBootServicesTableLib.h> > > +#include <Library/UefiLib.h> > > +#include <Protocol/PciIo.h> > > + > > +#include "SataInit.h" > > + > > +STATIC VOID *mDriverEventRegistration; > > + > > +/** > > + Read AHCI Operation register. > > + > > + @param PciIo The PCI IO protocol instance. > > + @param Offset The operation register offset. > > + > > + @return The register content read. > > +**/ > > + > > +UINT32 > > +EFIAPI > > +AhciReadReg ( > > + IN EFI_PCI_IO_PROTOCOL *PciIo, > > + IN UINT32 Offset > > + ) > > +{ > > + UINT32 Data; > > + > > + ASSERT (PciIo != NULL); > > + > > + Data = 0; > > + > > + PciIo->Mem.Read ( > > + PciIo, > > + EfiPciIoWidthUint32, > > + AHCI_BAR_INDEX, > > + (UINT64) Offset, > > + 1, > > + &Data > > + ); > > + > > + return Data; > > +} > > + > > +/** > > + Write AHCI Operation register. > > + > > + @param PciIo The PCI IO protocol instance. > > + @param Offset The operation register offset. > > + @param Data The data used to write down. > > + > > +**/ > > +VOID > > +EFIAPI > > +AhciWriteReg ( > > + IN EFI_PCI_IO_PROTOCOL *PciIo, > > + IN UINT32 Offset, > > + IN UINT32 Data > > + ) > > +{ > > + ASSERT (PciIo != NULL); > > + > > + PciIo->Mem.Write ( > > + PciIo, > > + EfiPciIoWidthUint32, > > + AHCI_BAR_INDEX, > > + (UINT64) Offset, > > + 1, > > + &Data > > + ); > > + > > + return; > > +} > > + > > +STATIC > > +VOID > > +PciIoRegistrationEvent ( > > + IN EFI_EVENT Event, > > + IN VOID *Context > > + ) > > +{ > > + EFI_STATUS Status; > > + UINTN HandleCount; > > + UINTN Address; > > + UINT32 Count; > > + UINT32 Data; > > + UINT8 PciClass; > > + UINT8 PciSubClass; > > + EFI_PCI_IO_PROTOCOL *PciIo; > > + EFI_HANDLE *HandleBuf; > > + > > + PciIo = NULL; > > + > > + Status = gBS->LocateHandleBuffer ( > > + ByProtocol, > > + &gEfiPciIoProtocolGuid, > > + NULL, > > + &HandleCount, > > + &HandleBuf); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Sata controller is not able to locate > gEfiPciIoProtocolGuid 0x%x\n", > > + Status)); > > + return; > > + } > > + > > + for (Count = 0; Count < HandleCount; Count++) { > > + Status = gBS->OpenProtocol ( > > + HandleBuf[Count], > > + &gEfiPciIoProtocolGuid, > > + (VOID **) &PciIo, > > + NULL, > > + NULL, > > + EFI_OPEN_PROTOCOL_GET_PROTOCOL); > > + if (EFI_ERROR (Status)) { > > + continue; > > + } > > + > > + // > > + // Now further check the PCI header: Base class (offset 0x0B) and > > + // Sub Class (offset 0x0A). This controller should be an Ide controller > > + // > > + Status = PciIo->Pci.Read ( > > + PciIo, > > + EfiPciIoWidthUint8, > > + PCI_CLASSCODE_OFFSET + 2, > > + 1, > > + &PciClass > > + ); > > + if (EFI_ERROR (Status)) { > > + continue; > > + } > > + > > + Status = PciIo->Pci.Read ( > > + PciIo, > > + EfiPciIoWidthUint8, > > + PCI_CLASSCODE_OFFSET + 1, > > + 1, > > + &PciSubClass > > + ); > > + if (EFI_ERROR (Status)) { > > + continue; > > + } > > + > > + // > > + // Examine Ide PCI Configuration table fields > > + // > > + if ((PciClass != PCI_CLASS_MASS_STORAGE) || > > + (PciSubClass != PCI_CLASS_MASS_STORAGE_SATADPA)) { > > + continue; > > + } > > + > > + Status = PciIo->Pci.Read ( > > + PciIo, > > + EfiPciIoWidthUint32, > > + PCI_AHCI_BASE_ADDRESS, > > + 1, > > + &Address > > + ); > > + if (EFI_ERROR (Status)) { > > + continue; > > + } else if (Address == (UINTN)Context) { > > + gBS->CloseEvent (Event); > > + > > + // > > + // configuring Physical Control Layer parameters for Port 0 > > + // > > + AhciWriteReg (PciIo, SATA_PPCFG, PORT_PHYSICAL); > > + > > + // > > + // This register controls the configuration of the > > + // Transport Layer for Port 0 > > + // Errata Description : The default Rx watermark value may be > insufficient for some > > + // hard drives and result in a false CRC or internal errors. > > + // Workaround: Change PTC[RXWM] field at offset 0xC8 to 0x29. Do > not change > > + // the other reserved fields of the register. > > + // > > + > > + Data = AhciReadReg (PciIo, SATA_PTC); > > + if (PcdGetBool (PcdSataErratumA009185)) { > > + Data |= PORT_RXWM; > > + } else { > > + Data |= PORT_TRANSPORT; > > + } > > + AhciWriteReg (PciIo, SATA_PTC, Data); > > + > > + break; > > + } > > + } > > + > > + gBS->FreePool (HandleBuf); > > + > > + return; > > +} > > + > > +/** > > + The Entry Point of module. It follows the standard UEFI driver model. > > + > > + @param[in] ImageHandle The firmware allocated handle for the EFI > image. > > + @param[in] SystemTable A pointer to the EFI System Table. > > + > > + @retval EFI_SUCCESS The entry point is executed successfully. > > + @retval other Some error occurs when executing this entry point. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +InitializeSataController ( > > + IN EFI_HANDLE ImageHandle, > > + IN EFI_SYSTEM_TABLE *SystemTable > > + ) > > +{ > > + EFI_STATUS Status; > > + UINT32 NumSataController; > > + UINTN ControllerAddr; > > + > > + Status = EFI_SUCCESS; > > + NumSataController = PcdGet32 (PcdNumSataController); > > + > > + // > > + // Impact : The SATA controller does not detect some hard drives reliably > with > > + // the default SerDes register setting. > > + // Workaround : write value 0x80104e20 to 0x1eb1300 (serdes 2) > > + // > > + if (PcdGetBool (PcdSataErratumA010554)) { > > + BeMmioWrite32 ((UINTN)SERDES2_SATA_ERRATA, 0x80104e20); > > + } > > + > > + // > > + // Impact : Device may see false CRC errors causing unreliable SATA > operation. > > + // Workaround : write 0x80000000 to the address 0x20140520 (dcsr). > > + // > > + if (PcdGetBool (PcdSataErratumA010635)) { > > + BeMmioWrite32 ((UINTN)DCSR_SATA_ERRATA, 0x80000000); > > + } > > + > > + while (NumSataController) { > > + NumSataController--; > > + ControllerAddr = PcdGet32 (PcdSataBaseAddr) + > > + (NumSataController * PcdGet32 (PcdSataSize)); > > + > > + Status = RegisterNonDiscoverableMmioDevice ( > > + NonDiscoverableDeviceTypeAhci, > > + NonDiscoverableDeviceDmaTypeNonCoherent, > > + NULL, > > + NULL, > > + 1, > > + ControllerAddr, PcdGet32 (PcdSataSize) > > + ); > > + > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Failed to register SATA device (0x%x) with > error 0x%x \n", > > + ControllerAddr, Status)); > > Please don't use if/else for the expected path: instead, return here > or goto the error/unwind code at the end of the function > In case of more than one controller, we cannot return/goto from here because there are chances that other controller might get register successfully. So used if-else, please suggest the correct way. > > + } else { > > + // > > + // Register a protocol registration notification callback on the driver > > + // binding protocol so we can attempt to connect to it as soon as it > appears. > > + // > > + EfiCreateProtocolNotifyEvent ( > > + &gEfiPciIoProtocolGuid, > > + TPL_CALLBACK, > > + PciIoRegistrationEvent, > > + (VOID *)ControllerAddr, > > + &mDriverEventRegistration); > > What is the point of this? AhciReadReg()/AhciWriteReg() can access > ControllerAddr directly, so there is no reason to go through the PCI > I/O protocol. > OK, i will check this. > > + } > > + } > > + > > + return Status; > > +} > > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.h > b/Platform/NXP/Drivers/SataInitDxe/SataInit.h > > new file mode 100644 > > index 0000000..7fe6273 > > --- /dev/null > > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.h > > @@ -0,0 +1,36 @@ > > +/** @file > > + Header file for Sata Controller initialization driver. > > + > > + Copyright 2017 NXP > > + > > + This program and the accompanying materials > > + are licensed and made available under the terms and conditions of the > BSD License > > + which accompanies this distribution. The full text of the license may be > found > > + > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope > nsource.org%2Flicenses%2Fbsd- > license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1bf888 > dbc6b34f8646fe08d556a93d5a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 > %7C0%7C636510207254570536&sdata=hU2o5igZuy5SDt5emEUmAqhSn1gW9 > H40OgvmH8gMn9k%3D&reserved=0 > > + > > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > > + > > + **/ > > + > > +#ifndef _SATA_INIT_H_ > > +#define _SATA_INIT_H_ > > + > > + > > +#define AHCI_BAR_INDEX 0x05 > > +// > > +// Offset for AHCI base address in PCI Header > > +// > > +#define PCI_AHCI_BASE_ADDRESS 0x24 > > + > > +#define SATA_PPCFG 0xA8 > > +#define SATA_PTC 0xC8 > > + > > +#define PORT_PHYSICAL 0xA003FFFE > > +#define PORT_TRANSPORT 0x08000025 > > +#define PORT_RXWM 0x08000029 > > + > > +#define DCSR_SATA_ERRATA 0x20140520 > > +#define SERDES2_SATA_ERRATA 0x01eb1300 > > + > > +#endif > > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > new file mode 100644 > > index 0000000..82535f4 > > --- /dev/null > > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > @@ -0,0 +1,52 @@ > > +## @file > > +# Component description file for the Sata Controller initialization driver > > +# > > +# Copyright 2017 NXP > > +# > > +# This program and the accompanying materials > > +# are licensed and made available under the terms and conditions of the > BSD License > > +# which accompanies this distribution. The full text of the license may be > found > > +# > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope > nsource.org%2Flicenses%2Fbsd- > license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1bf888 > dbc6b34f8646fe08d556a93d5a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 > %7C0%7C636510207254570536&sdata=hU2o5igZuy5SDt5emEUmAqhSn1gW9 > H40OgvmH8gMn9k%3D&reserved=0 > > +# > > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > > +# > > +## > > + > > +[Defines] > > + INF_VERSION = 0x0001000A > > + BASE_NAME = SataInit > > + FILE_GUID = 021722D8-522B-4079-852A-FE44C2C13F49 > > + MODULE_TYPE = DXE_DRIVER > > + VERSION_STRING = 1.0 > > + ENTRY_POINT = InitializeSataController > > + > > +[Sources] > > + SataInit.c > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + Platform/NXP/NxpQoriqLs.dec > > + > > +[LibraryClasses] > > + BeIoLib > > + DebugLib > > + NonDiscoverableDeviceRegistrationLib > > + UefiBootServicesTableLib > > + UefiDriverEntryPoint > > + UefiLib > > + > > +[FixedPcd] > > + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController > > + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr > > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize > > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 > > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554 > > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635 > > + > > +[Protocols] > > + gEfiPciIoProtocolGuid > > + > > +[Depex] > > + TRUE > > diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec > > index bd4273f..65d659e 100644 > > --- a/Platform/NXP/NxpQoriqLs.dec > > +++ b/Platform/NXP/NxpQoriqLs.dec > > @@ -52,8 +52,8 @@ > > gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E > > gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F > > gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110 > > - > gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32| > 0x00000111 > > - > gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32| > 0x00000112 > > + > gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111 > > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112 > > > gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT6 > 4|0x00000113 > > > gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x0 > 0000114 > > > gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64 > |0x00000115 > > @@ -83,6 +83,8 @@ > > > gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000 > 012D > > > gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E > > > gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F > > + > gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x00000130 > > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x00000131 > > > > # > > # DSPI Pcds > > @@ -156,6 +158,9 @@ > > > gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x0000 > 0275 > > > gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x0000 > 0276 > > > gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x > 00000277 > > + > gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|FALSE|BOOLEAN|0x > 00000278 > > + > gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|FALSE|BOOLEAN|0x > 00000279 > > + > gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA008402|FALSE|BOOLEAN|0x > 0000027A > > > > # > > # Test PCDs > > @@ -249,3 +254,8 @@ > > # > > gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330 > > > gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x00003 > 31 > > + > > + # > > + # SATA Pcds > > + # > > + > gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x000003 > 40 > > diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc > > index 10eff06..c3c0eb1 100644 > > --- a/Platform/NXP/NxpQoriqLs.dsc > > +++ b/Platform/NXP/NxpQoriqLs.dsc > > @@ -99,6 +99,8 @@ > > VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf > > NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf > > > CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.i > nf > > + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf > > + > NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscove > rableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf > > > > [LibraryClasses.common.SEC] > > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > > @@ -144,6 +146,7 @@ > > > SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementL > ib/DxeSecurityManagementLib.inf > > > PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerforma > nceLib.inf > > MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf > > + > NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscove > rableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf > > > > Why do you need to add this twice? My fault, will update. > > > [LibraryClasses.common.UEFI_APPLICATION] > > PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > > @@ -334,6 +337,16 @@ > > } > > > > # > > + # AHCI Support > > + # > > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > > + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > > + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > > + > MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePci > DeviceDxe.inf > > + > > + # > > # Architectural Protocols > > # > > ArmPkg/Drivers/CpuDxe/CpuDxe.inf > > -- > > 1.9.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver. 2018-01-09 4:50 ` Meenakshi Aggarwal @ 2018-01-09 8:26 ` Ard Biesheuvel 0 siblings, 0 replies; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-09 8:26 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 9 January 2018 at 04:50, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > > >> -----Original Message----- >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> Sent: Monday, January 08, 2018 8:35 PM >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> Subject: Re: [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller >> driver. >> >> Hi Meenakshi, >> >> This is looking much better - thanks for rewriting it. I do have some >> comments below >> >> On 8 January 2018 at 15:55, Meenakshi Aggarwal >> <meenakshi.aggarwal@nxp.com> wrote: >> > This patch adds support of SATA controller, which >> > Initialize SATA controller, >> > apply platform specific errata and >> > Register itself as NonDiscoverableMmioDevice >> > >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> > --- >> > Platform/NXP/Drivers/SataInitDxe/SataInit.c | 285 >> +++++++++++++++++++++++ >> > Platform/NXP/Drivers/SataInitDxe/SataInit.h | 36 +++ >> > Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 52 +++++ >> > Platform/NXP/NxpQoriqLs.dec | 14 +- >> > Platform/NXP/NxpQoriqLs.dsc | 13 ++ >> > 5 files changed, 398 insertions(+), 2 deletions(-) >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h >> > create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> > .... >> > +/** >> > + The Entry Point of module. It follows the standard UEFI driver model. >> > + >> > + @param[in] ImageHandle The firmware allocated handle for the EFI >> image. >> > + @param[in] SystemTable A pointer to the EFI System Table. >> > + >> > + @retval EFI_SUCCESS The entry point is executed successfully. >> > + @retval other Some error occurs when executing this entry point. >> > + >> > +**/ >> > +EFI_STATUS >> > +EFIAPI >> > +InitializeSataController ( >> > + IN EFI_HANDLE ImageHandle, >> > + IN EFI_SYSTEM_TABLE *SystemTable >> > + ) >> > +{ >> > + EFI_STATUS Status; >> > + UINT32 NumSataController; >> > + UINTN ControllerAddr; >> > + >> > + Status = EFI_SUCCESS; >> > + NumSataController = PcdGet32 (PcdNumSataController); >> > + >> > + // >> > + // Impact : The SATA controller does not detect some hard drives reliably >> with >> > + // the default SerDes register setting. >> > + // Workaround : write value 0x80104e20 to 0x1eb1300 (serdes 2) >> > + // >> > + if (PcdGetBool (PcdSataErratumA010554)) { >> > + BeMmioWrite32 ((UINTN)SERDES2_SATA_ERRATA, 0x80104e20); >> > + } >> > + >> > + // >> > + // Impact : Device may see false CRC errors causing unreliable SATA >> operation. >> > + // Workaround : write 0x80000000 to the address 0x20140520 (dcsr). >> > + // >> > + if (PcdGetBool (PcdSataErratumA010635)) { >> > + BeMmioWrite32 ((UINTN)DCSR_SATA_ERRATA, 0x80000000); >> > + } >> > + >> > + while (NumSataController) { >> > + NumSataController--; >> > + ControllerAddr = PcdGet32 (PcdSataBaseAddr) + >> > + (NumSataController * PcdGet32 (PcdSataSize)); >> > + >> > + Status = RegisterNonDiscoverableMmioDevice ( >> > + NonDiscoverableDeviceTypeAhci, >> > + NonDiscoverableDeviceDmaTypeNonCoherent, >> > + NULL, >> > + NULL, >> > + 1, >> > + ControllerAddr, PcdGet32 (PcdSataSize) >> > + ); >> > + >> > + if (EFI_ERROR (Status)) { >> > + DEBUG ((DEBUG_ERROR, "Failed to register SATA device (0x%x) with >> error 0x%x \n", >> > + ControllerAddr, Status)); >> >> Please don't use if/else for the expected path: instead, return here >> or goto the error/unwind code at the end of the function >> > In case of more than one controller, we cannot return/goto from here because there are chances that other controller might get register successfully. > So used if-else, please suggest the correct way. > Then use 'continue' In any case, all RegisterNonDiscoverableMmioDevice() does is install a protocol on a new handle, so it is unlikely to fail. You can just replace the error handling with ASSERT_EFI_ERROR(). >> > + } else { >> > + // >> > + // Register a protocol registration notification callback on the driver >> > + // binding protocol so we can attempt to connect to it as soon as it >> appears. >> > + // >> > + EfiCreateProtocolNotifyEvent ( >> > + &gEfiPciIoProtocolGuid, >> > + TPL_CALLBACK, >> > + PciIoRegistrationEvent, >> > + (VOID *)ControllerAddr, >> > + &mDriverEventRegistration); >> >> What is the point of this? AhciReadReg()/AhciWriteReg() can access >> ControllerAddr directly, so there is no reason to go through the PCI >> I/O protocol. >> > OK, i will check this. >> > + } >> > + } >> > + >> > + return Status; >> > +} >> > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.h >> b/Platform/NXP/Drivers/SataInitDxe/SataInit.h >> > new file mode 100644 >> > index 0000000..7fe6273 >> > --- /dev/null >> > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.h >> > @@ -0,0 +1,36 @@ >> > +/** @file >> > + Header file for Sata Controller initialization driver. >> > + >> > + Copyright 2017 NXP >> > + >> > + This program and the accompanying materials >> > + are licensed and made available under the terms and conditions of the >> BSD License >> > + which accompanies this distribution. The full text of the license may be >> found >> > + >> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope >> nsource.org%2Flicenses%2Fbsd- >> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1bf888 >> dbc6b34f8646fe08d556a93d5a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 >> %7C0%7C636510207254570536&sdata=hU2o5igZuy5SDt5emEUmAqhSn1gW9 >> H40OgvmH8gMn9k%3D&reserved=0 >> > + >> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" >> BASIS, >> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER >> EXPRESS OR IMPLIED. >> > + >> > + **/ >> > + >> > +#ifndef _SATA_INIT_H_ >> > +#define _SATA_INIT_H_ >> > + >> > + >> > +#define AHCI_BAR_INDEX 0x05 >> > +// >> > +// Offset for AHCI base address in PCI Header >> > +// >> > +#define PCI_AHCI_BASE_ADDRESS 0x24 >> > + >> > +#define SATA_PPCFG 0xA8 >> > +#define SATA_PTC 0xC8 >> > + >> > +#define PORT_PHYSICAL 0xA003FFFE >> > +#define PORT_TRANSPORT 0x08000025 >> > +#define PORT_RXWM 0x08000029 >> > + >> > +#define DCSR_SATA_ERRATA 0x20140520 >> > +#define SERDES2_SATA_ERRATA 0x01eb1300 >> > + >> > +#endif >> > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> > new file mode 100644 >> > index 0000000..82535f4 >> > --- /dev/null >> > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> > @@ -0,0 +1,52 @@ >> > +## @file >> > +# Component description file for the Sata Controller initialization driver >> > +# >> > +# Copyright 2017 NXP >> > +# >> > +# This program and the accompanying materials >> > +# are licensed and made available under the terms and conditions of the >> BSD License >> > +# which accompanies this distribution. The full text of the license may be >> found >> > +# >> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope >> nsource.org%2Flicenses%2Fbsd- >> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1bf888 >> dbc6b34f8646fe08d556a93d5a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 >> %7C0%7C636510207254570536&sdata=hU2o5igZuy5SDt5emEUmAqhSn1gW9 >> H40OgvmH8gMn9k%3D&reserved=0 >> > +# >> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" >> BASIS, >> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER >> EXPRESS OR IMPLIED. >> > +# >> > +## >> > + >> > +[Defines] >> > + INF_VERSION = 0x0001000A >> > + BASE_NAME = SataInit >> > + FILE_GUID = 021722D8-522B-4079-852A-FE44C2C13F49 >> > + MODULE_TYPE = DXE_DRIVER >> > + VERSION_STRING = 1.0 >> > + ENTRY_POINT = InitializeSataController >> > + >> > +[Sources] >> > + SataInit.c >> > + >> > +[Packages] >> > + MdePkg/MdePkg.dec >> > + MdeModulePkg/MdeModulePkg.dec >> > + Platform/NXP/NxpQoriqLs.dec >> > + >> > +[LibraryClasses] >> > + BeIoLib >> > + DebugLib >> > + NonDiscoverableDeviceRegistrationLib >> > + UefiBootServicesTableLib >> > + UefiDriverEntryPoint >> > + UefiLib >> > + >> > +[FixedPcd] >> > + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554 >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635 >> > + >> > +[Protocols] >> > + gEfiPciIoProtocolGuid >> > + >> > +[Depex] >> > + TRUE >> > diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec >> > index bd4273f..65d659e 100644 >> > --- a/Platform/NXP/NxpQoriqLs.dec >> > +++ b/Platform/NXP/NxpQoriqLs.dec >> > @@ -52,8 +52,8 @@ >> > gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E >> > gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F >> > gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110 >> > - >> gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32| >> 0x00000111 >> > - >> gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32| >> 0x00000112 >> > + >> gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111 >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112 >> > >> gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT6 >> 4|0x00000113 >> > >> gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x0 >> 0000114 >> > >> gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64 >> |0x00000115 >> > @@ -83,6 +83,8 @@ >> > >> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000 >> 012D >> > >> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E >> > >> gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F >> > + >> gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x00000130 >> > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x00000131 >> > >> > # >> > # DSPI Pcds >> > @@ -156,6 +158,9 @@ >> > >> gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x0000 >> 0275 >> > >> gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x0000 >> 0276 >> > >> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x >> 00000277 >> > + >> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|FALSE|BOOLEAN|0x >> 00000278 >> > + >> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|FALSE|BOOLEAN|0x >> 00000279 >> > + >> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA008402|FALSE|BOOLEAN|0x >> 0000027A >> > >> > # >> > # Test PCDs >> > @@ -249,3 +254,8 @@ >> > # >> > gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330 >> > >> gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x00003 >> 31 >> > + >> > + # >> > + # SATA Pcds >> > + # >> > + >> gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x000003 >> 40 >> > diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc >> > index 10eff06..c3c0eb1 100644 >> > --- a/Platform/NXP/NxpQoriqLs.dsc >> > +++ b/Platform/NXP/NxpQoriqLs.dsc >> > @@ -99,6 +99,8 @@ >> > VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf >> > NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf >> > >> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.i >> nf >> > + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf >> > + >> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscove >> rableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf >> > >> > [LibraryClasses.common.SEC] >> > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >> > @@ -144,6 +146,7 @@ >> > >> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementL >> ib/DxeSecurityManagementLib.inf >> > >> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerforma >> nceLib.inf >> > MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf >> > + >> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscove >> rableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf >> > >> >> Why do you need to add this twice? > My fault, will update. >> >> > [LibraryClasses.common.UEFI_APPLICATION] >> > PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf >> > @@ -334,6 +337,16 @@ >> > } >> > >> > # >> > + # AHCI Support >> > + # >> > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf >> > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf >> > + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf >> > + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf >> > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf >> > + >> MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePci >> DeviceDxe.inf >> > + >> > + # >> > # Architectural Protocols >> > # >> > ArmPkg/Drivers/CpuDxe/CpuDxe.inf >> > -- >> > 1.9.1 >> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller 2018-01-08 15:55 ` [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support Meenakshi Aggarwal 2018-01-08 15:55 ` [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver Meenakshi Aggarwal @ 2018-01-08 15:55 ` Meenakshi Aggarwal 2018-01-08 15:11 ` Ard Biesheuvel 1 sibling, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-08 15:55 UTC (permalink / raw) To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel Enable support of SATA drives on ls1046 board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> --- Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 8 ++++++++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12 ++++++++++++ .../NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 8 ++++++++ Silicon/NXP/LS1046A/LS1046A.dsc | 5 +++++ 5 files changed, 35 insertions(+) diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc index 9d2482b..93fc848 100644 --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc @@ -63,6 +63,13 @@ # gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + # + # Errata Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|TRUE + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform @@ -71,3 +78,4 @@ [Components.common] edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf + edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf index 169cef0..23b46ad 100644 --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf @@ -142,6 +142,18 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + # + # AHCI Support + # + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + INF edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf + # FAT filesystem + GPT/MBR partitioning # INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index 13a0ffb..002294e 100644 --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -68,3 +68,5 @@ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index 7022528..4b04ff5 100644 --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -49,6 +49,8 @@ #define DRAM3_SIZE FixedPcdGet64 (PcdDram3Size) #define QSPI_REGION_BASE_ADDR FixedPcdGet64 (PcdQspiRegionBaseAddr) #define QSPI_REGION_SIZE FixedPcdGet64 (PcdQspiRegionSize) +#define DCSR_BASE_ADDR FixedPcdGet64 (PcdDcsrBaseAddr) +#define DCSR_SIZE FixedPcdGet64 (PcdDcsrSize) /** @@ -169,6 +171,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = QSPI_REGION_SIZE; VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + // DCSR Space + VirtualMemoryTable[++Index].PhysicalBase = DCSR_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = DCSR_BASE_ADDR; + VirtualMemoryTable[Index].Length = DCSR_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // End of Table VirtualMemoryTable[++Index].PhysicalBase = 0; VirtualMemoryTable[Index].VirtualBase = 0; diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc index 4e7230a..33c57ad 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc @@ -74,5 +74,10 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A0000 gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B0000 gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x04000000 + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x3200000 + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x1 ## -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller 2018-01-08 15:55 ` [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller Meenakshi Aggarwal @ 2018-01-08 15:11 ` Ard Biesheuvel 2018-01-09 4:37 ` Meenakshi Aggarwal 0 siblings, 1 reply; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-08 15:11 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 8 January 2018 at 15:55, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > Enable support of SATA drives on ls1046 board. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > --- > Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 8 ++++++++ > Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12 ++++++++++++ > .../NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ > .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 8 ++++++++ > Silicon/NXP/LS1046A/LS1046A.dsc | 5 +++++ > 5 files changed, 35 insertions(+) > > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > index 9d2482b..93fc848 100644 > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > @@ -63,6 +63,13 @@ > # > gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 > > + # > + # Errata Pcds > + # > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|TRUE > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|TRUE > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|TRUE > + > ################################################################################ > # > # Components Section - list of all EDK II Modules needed by this Platform > @@ -71,3 +78,4 @@ > [Components.common] > edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf > edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf > + edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf This looks wrong to me. Your .dsc/.fdf files should not contain these edk2-platforms prefixes. Instead, you should set your PACKAGES_PATH correctly to include your edk2-platforms directory. > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > index 169cef0..23b46ad 100644 > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > @@ -142,6 +142,18 @@ READ_LOCK_STATUS = TRUE > > INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf > > + # > + # AHCI Support > + # > + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf > + > + INF edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > + Same here > # FAT filesystem + GPT/MBR partitioning > # > INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > index 13a0ffb..002294e 100644 > --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > @@ -68,3 +68,5 @@ > gNxpQoriqLsTokenSpaceGuid.PcdDram3Size > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > index 7022528..4b04ff5 100644 > --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > @@ -49,6 +49,8 @@ > #define DRAM3_SIZE FixedPcdGet64 (PcdDram3Size) > #define QSPI_REGION_BASE_ADDR FixedPcdGet64 (PcdQspiRegionBaseAddr) > #define QSPI_REGION_SIZE FixedPcdGet64 (PcdQspiRegionSize) > +#define DCSR_BASE_ADDR FixedPcdGet64 (PcdDcsrBaseAddr) > +#define DCSR_SIZE FixedPcdGet64 (PcdDcsrSize) > > > /** > @@ -169,6 +171,12 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = QSPI_REGION_SIZE; > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > > + // DCSR Space > + VirtualMemoryTable[++Index].PhysicalBase = DCSR_BASE_ADDR; > + VirtualMemoryTable[Index].VirtualBase = DCSR_BASE_ADDR; > + VirtualMemoryTable[Index].Length = DCSR_SIZE; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > // End of Table > VirtualMemoryTable[++Index].PhysicalBase = 0; > VirtualMemoryTable[Index].VirtualBase = 0; > diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc > index 4e7230a..33c57ad 100644 > --- a/Silicon/NXP/LS1046A/LS1046A.dsc > +++ b/Silicon/NXP/LS1046A/LS1046A.dsc > @@ -74,5 +74,10 @@ > gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A0000 > gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B0000 > gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x20000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x04000000 > + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x3200000 > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x10000 > + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x1 > > ## > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller 2018-01-08 15:11 ` Ard Biesheuvel @ 2018-01-09 4:37 ` Meenakshi Aggarwal 2018-01-09 8:27 ` Ard Biesheuvel 0 siblings, 1 reply; 21+ messages in thread From: Meenakshi Aggarwal @ 2018-01-09 4:37 UTC (permalink / raw) To: Ard Biesheuvel Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Monday, January 08, 2018 8:42 PM > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D > <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA > controller > > On 8 January 2018 at 15:55, Meenakshi Aggarwal > <meenakshi.aggarwal@nxp.com> wrote: > > Enable support of SATA drives on ls1046 board. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> > > --- > > Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 8 ++++++++ > > Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12 > ++++++++++++ > > .../NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ > > .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 8 > ++++++++ > > Silicon/NXP/LS1046A/LS1046A.dsc | 5 +++++ > > 5 files changed, 35 insertions(+) > > > > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > > index 9d2482b..93fc848 100644 > > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc > > @@ -63,6 +63,13 @@ > > # > > gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 > > > > + # > > + # Errata Pcds > > + # > > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|TRUE > > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|TRUE > > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|TRUE > > + > > > ########################################################## > ###################### > > # > > # Components Section - list of all EDK II Modules needed by this Platform > > @@ -71,3 +78,4 @@ > > [Components.common] > > edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf > > edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf > > + edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > This looks wrong to me. Your .dsc/.fdf files should not contain these > edk2-platforms prefixes. Instead, you should set your PACKAGES_PATH > correctly to include your edk2-platforms directory. > OK, We will remove this from .dsc/.fdf files. My concern is as there are already a lot of patches are under review so it will be Better if review gets completed once, then we will share the updated in next revision of patch As this needs to be change in multiple patches. There is one more comment from you on keeping shred Drivers and Library in Silicon/NXP directory. In this case also, this will need a rework in all patches sent till date. So once review comments been recieved we will made the changes in next revision of patch. > > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > > index 169cef0..23b46ad 100644 > > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf > > @@ -142,6 +142,18 @@ READ_LOCK_STATUS = TRUE > > > > INF > MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntime > Dxe.inf > > > > + # > > + # AHCI Support > > + # > > + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > > + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > > + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > > + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > > + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > > + INF > MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePci > DeviceDxe.inf > > + > > + INF edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf > > + > > Same here > > > # FAT filesystem + GPT/MBR partitioning > > # > > INF > MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > > diff --git > a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > > index 13a0ffb..002294e 100644 > > --- > a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > > +++ > b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > > @@ -68,3 +68,5 @@ > > gNxpQoriqLsTokenSpaceGuid.PcdDram3Size > > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr > > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize > > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr > > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize > > diff --git > a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > > index 7022528..4b04ff5 100644 > > --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > > +++ > b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > > @@ -49,6 +49,8 @@ > > #define DRAM3_SIZE FixedPcdGet64 (PcdDram3Size) > > #define QSPI_REGION_BASE_ADDR FixedPcdGet64 > (PcdQspiRegionBaseAddr) > > #define QSPI_REGION_SIZE FixedPcdGet64 (PcdQspiRegionSize) > > +#define DCSR_BASE_ADDR FixedPcdGet64 (PcdDcsrBaseAddr) > > +#define DCSR_SIZE FixedPcdGet64 (PcdDcsrSize) > > > > > > /** > > @@ -169,6 +171,12 @@ ArmPlatformGetVirtualMemoryMap ( > > VirtualMemoryTable[Index].Length = QSPI_REGION_SIZE; > > VirtualMemoryTable[Index].Attributes = > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > > > > + // DCSR Space > > + VirtualMemoryTable[++Index].PhysicalBase = DCSR_BASE_ADDR; > > + VirtualMemoryTable[Index].VirtualBase = DCSR_BASE_ADDR; > > + VirtualMemoryTable[Index].Length = DCSR_SIZE; > > + VirtualMemoryTable[Index].Attributes = > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + > > // End of Table > > VirtualMemoryTable[++Index].PhysicalBase = 0; > > VirtualMemoryTable[Index].VirtualBase = 0; > > diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc > b/Silicon/NXP/LS1046A/LS1046A.dsc > > index 4e7230a..33c57ad 100644 > > --- a/Silicon/NXP/LS1046A/LS1046A.dsc > > +++ b/Silicon/NXP/LS1046A/LS1046A.dsc > > @@ -74,5 +74,10 @@ > > gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A0000 > > gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B0000 > > gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 > > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x20000000 > > + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x04000000 > > + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x3200000 > > + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x10000 > > + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x1 > > > > ## > > -- > > 1.9.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller 2018-01-09 4:37 ` Meenakshi Aggarwal @ 2018-01-09 8:27 ` Ard Biesheuvel 0 siblings, 0 replies; 21+ messages in thread From: Ard Biesheuvel @ 2018-01-09 8:27 UTC (permalink / raw) To: Meenakshi Aggarwal Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi On 9 January 2018 at 04:37, Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> wrote: > > >> -----Original Message----- >> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >> Sent: Monday, January 08, 2018 8:42 PM >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D >> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com> >> Subject: Re: [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA >> controller >> >> On 8 January 2018 at 15:55, Meenakshi Aggarwal >> <meenakshi.aggarwal@nxp.com> wrote: >> > Enable support of SATA drives on ls1046 board. >> > >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> >> > --- >> > Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 8 ++++++++ >> > Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12 >> ++++++++++++ >> > .../NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ >> > .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 8 >> ++++++++ >> > Silicon/NXP/LS1046A/LS1046A.dsc | 5 +++++ >> > 5 files changed, 35 insertions(+) >> > >> > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc >> b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc >> > index 9d2482b..93fc848 100644 >> > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc >> > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc >> > @@ -63,6 +63,13 @@ >> > # >> > gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 >> > >> > + # >> > + # Errata Pcds >> > + # >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|TRUE >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|TRUE >> > + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|TRUE >> > + >> > >> ########################################################## >> ###################### >> > # >> > # Components Section - list of all EDK II Modules needed by this Platform >> > @@ -71,3 +78,4 @@ >> > [Components.common] >> > edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf >> > edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf >> > + edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf >> >> This looks wrong to me. Your .dsc/.fdf files should not contain these >> edk2-platforms prefixes. Instead, you should set your PACKAGES_PATH >> correctly to include your edk2-platforms directory. >> > OK, We will remove this from .dsc/.fdf files. > My concern is as there are already a lot of patches are under review so it will be > Better if review gets completed once, then we will share the updated in next revision of patch > As this needs to be change in multiple patches. > > There is one more comment from you on keeping shred Drivers and Library in Silicon/NXP directory. > In this case also, this will need a rework in all patches sent till date. > > So once review comments been recieved we will made the changes in next revision of patch. > I have a better idea. Let's disregard all current submissions in flight, and repost the next one as a single series so that I don't have to keep track of all the different ones. ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2018-01-09 8:22 UTC | newest] Thread overview: 21+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 2/3] PciEmulation : Add support for Pci Emulation layer Meenakshi Aggarwal 2017-12-22 12:16 ` [PATCH edk2-platforms 3/3] SATA : Added SATA controller initialization driver Meenakshi Aggarwal 2017-12-22 15:31 ` [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Ard Biesheuvel 2018-01-04 11:27 ` Meenakshi Aggarwal 2018-01-04 11:33 ` Ard Biesheuvel 2018-01-04 12:56 ` Meenakshi Aggarwal 2018-01-05 6:47 ` Meenakshi Aggarwal 2018-01-05 7:40 ` Ard Biesheuvel 2018-01-05 8:53 ` Meenakshi Aggarwal 2018-01-05 9:16 ` Ard Biesheuvel 2018-01-08 15:55 ` [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support Meenakshi Aggarwal 2018-01-08 15:55 ` [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver Meenakshi Aggarwal 2018-01-08 15:05 ` Ard Biesheuvel 2018-01-09 4:50 ` Meenakshi Aggarwal 2018-01-09 8:26 ` Ard Biesheuvel 2018-01-08 15:55 ` [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller Meenakshi Aggarwal 2018-01-08 15:11 ` Ard Biesheuvel 2018-01-09 4:37 ` Meenakshi Aggarwal 2018-01-09 8:27 ` Ard Biesheuvel
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