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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2021 17:28:28.9651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32c4e0a3-f35f-43ed-3582-08d8cf7b9cb1 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT029.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR08MB5387 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Vijay, This patch needs similar changes as patch 2/3. Regards, Sami Mujawar -----Original Message----- From: Vijayenthiran Subramaniam =20 Sent: 03 February 2021 09:07 AM To: devel@edk2.groups.io; Jonathan.Cameron@Huawei.com; leif@nuviainc.com; a= rdb+tianocore@kernel.org; Sami Mujawar Cc: Thomas Abraham Subject: [edk2-platforms] [PATCH v2 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI= table for RD-V1-MC Add HMAT ACPI tables that is specific for RD-V1-MC quad-chip platform. The latencies mentioned in the table are hypothetical values and represents typical latency between four chips. These values are applicable only for RD-V1-MC quad-chip fixed virtual and should not be reused for other platforms. Signed-off-by: Vijayenthiran Subramaniam --- Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 144 ++++++++++++++++= ++++ 2 files changed, 145 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf index 051825993af0..f3552bc49003 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf @@ -22,6 +22,7 @@ [Sources] Iort.aslc Mcfg.aslc RdV1Mc/Dsdt.asl + RdV1Mc/Hmat.aslc RdV1Mc/Madt.aslc RdV1Mc/Srat.aslc Spcr.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc new file mode 100644 index 000000000000..d2c067d70be9 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc @@ -0,0 +1,144 @@ +/** @file +* Heterogeneous Memory Attribute Table (HMAT) +* +* Copyright (c) 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" +#include +#include +#include + +#define CHIP_CNT FixedPcdGet32 (PcdChipCount) +#define INITATOR_PROXIMITY_DOMAIN_CNT 4 +#define TARGET_PROXIMITY_DOMAIN_CNT 4 + +// +// HMAT Table +// +#pragma pack (1) + +typedef struct { + UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT]; + UINT32 TargetProximityDomain[TARGET_PROXIMITY_DOMAIN_CNT]; + UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOM= AIN_CNT]; +} InitiatorTargetProximityMatrix; + +typedef struct { + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER = Header; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES = Proximity[CHIP_CNT]; + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO = LatencyInfo; + InitiatorTargetProximityMatrix = Matrix; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache0; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache1; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache2; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache3; +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE; + +#pragma pack () + +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( = \ + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLine= Size \ + ) = \ +{ = \ + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLine= Size \ +} + +EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { + // Header + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE, + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE, + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION + ), + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + }, + + // Memory Proximity Domain + { + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + 1, 0x0, 0x0), + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + 1, 0x1, 0x1), + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + 1, 0x2, 0x2), + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + 1, 0x3, 0x3), + }, + + // Latency Info + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_I= NIT ( + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100)= , + { + {0, 1, 2, 3}, {0, 1, 2, 3}, + { + // + // The latencies mentioned in this table are hypothetical values and + // represents typical latency between four chips. These values are + // applicable only for RD-V1-MC quad-chip fixed virtual platform and + // should not be reused for other platforms. + // + 10, 20, 20, 20, + 20, 10, 20, 20, + 20, 20, 10, 20, + 20, 20, 20, 10, + } + }, + + // Memory Side Cache + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + 0x0, SIZE_1GB, + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( + 1, + 1, + 2, + 2, + 64 // 64 bytes cache line length + ), + 0), + + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + 0x1, SIZE_1GB, + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( + 1, + 1, + 2, + 2, + 64 // 64 bytes cache line length + ), + 0), + + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + 0x2, SIZE_1GB, + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( + 1, + 1, + 2, + 2, + 64 // 64 bytes cache line length + ), + 0), + + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + 0x3, SIZE_1GB, + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( + 1, + 1, + 2, + 2, + 64 // 64 bytes cache line length + ), + 0), +}; + +VOID* CONST ReferenceAcpiTable =3D &Hmat; --=20 2.17.1