* [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support
@ 2021-02-24 13:12 Chandni Cherukuri
2021-02-24 13:12 ` [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Chandni Cherukuri
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Chandni Cherukuri @ 2021-02-24 13:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
Morello is an ARMv8-A platform that implements the capability architecture
extension. This patch series provides ARMv8-A architecture enablement
for the Morello FVP platform.
The changes can be seen at:
https://github.com/chandnich/edk2-platforms/tree/morello_plat_support_v1
Anurag Koul (3):
Platform/ARM/Morello: Add Platform library implementation
Platform/ARM/Morello: Add PlatformDxe driver for Morello
Platform/ARM/Morello: Add initial support for Morello Platform
Chandni Cherukuri (2):
Platform/ARM/Morello: Add support for PciHostBridgeLib
Platform/ARM/Morello: Add Configuration Manager for Morello
Platform/ARM/Morello/MorelloPlatform.dec | 59 +
.../ConfigurationManagerFvp.dsc.inc | 16 +
Platform/ARM/Morello/MorelloPlatform.dsc.inc | 235 ++++
Platform/ARM/Morello/MorelloPlatformFvp.dsc | 60 +
Platform/ARM/Morello/MorelloPlatformFvp.fdf | 302 +++++
.../ConfigurationManagerDxeFvp.inf | 94 ++
.../Drivers/PlatformDxe/PlatformDxeFvp.inf | 43 +
.../PciHostBridgeLib/PciHostBridgeLibFvp.inf | 48 +
.../Library/PlatformLib/PlatformLib.inf | 52 +
.../ConfigurationManager.h | 304 +++++
.../ConfigurationManagerFvp.h | 81 ++
.../ConfigurationManagerDxe/Platform.h | 91 ++
.../Guid/MorelloVirtioDevicesFormSet.h | 14 +
.../ARM/Morello/Include/MorelloPlatform.h | 67 ++
.../ConfigurationManager.c | 1005 +++++++++++++++++
.../ConfigurationManagerFvp.c | 531 +++++++++
.../Drivers/PlatformDxe/PlatformDxeFvp.c | 58 +
.../Drivers/PlatformDxe/VirtioDevices.c | 91 ++
.../PciHostBridgeLib/PciHostBridgeLibFvp.c | 182 +++
.../Morello/Library/PlatformLib/PlatformLib.c | 66 ++
.../Library/PlatformLib/PlatformLibMem.c | 194 ++++
.../AslTables/DsdtFvp.asl | 114 ++
.../AslTables/SsdtPciFvp.asl | 130 +++
.../Library/PlatformLib/AArch64/Helper.S | 83 ++
24 files changed, 3920 insertions(+)
create mode 100644 Platform/ARM/Morello/MorelloPlatform.dec
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc
create mode 100644 Platform/ARM/Morello/MorelloPlatform.dsc.inc
create mode 100644 Platform/ARM/Morello/MorelloPlatformFvp.dsc
create mode 100644 Platform/ARM/Morello/MorelloPlatformFvp.fdf
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf
create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
create mode 100644 Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h
create mode 100644 Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
create mode 100644 Platform/ARM/Morello/Include/MorelloPlatform.h
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c
create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c
create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
create mode 100644 Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S
--
2.17.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri @ 2021-02-24 13:12 ` Chandni Cherukuri 2021-02-26 18:35 ` [edk2-devel] " Thomas Abraham 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib Chandni Cherukuri ` (4 subsequent siblings) 5 siblings, 2 replies; 15+ messages in thread From: Chandni Cherukuri @ 2021-02-24 13:12 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar From: Anurag Koul <anurag.koul@arm.com> This patch adds initial Morello Platform Library support. It includes virtual memory map and helper functions for platform initialization. Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 ++++++++++++++++++++ Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ 5 files changed, 462 insertions(+) diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..2066d1f3a3f8 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = ArmMorelloLib + FILE_GUID = 36853D86-7200-47B4-9408-E962A00963FD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base + + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress + gArmMorelloTokenSpaceGuid.PcdPciIoSize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/Morello/Include/MorelloPlatform.h new file mode 100644 index 000000000000..f61cfe7f9ee8 --- /dev/null +++ b/Platform/ARM/Morello/Include/MorelloPlatform.h @@ -0,0 +1,67 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_PLATFORM_H__ +#define MORELLO_PLATFORM_H__ + +#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB + +// **************************************************************************** +// Platform Memory Map +// **************************************************************************** + +// SubSystem Peripherals - UART0 +#define MORELLO_UART0_BASE 0x2A400000 +#define MORELLO_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define MORELLO_UART1_BASE 0x2A410000 +#define MORELLO_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define MORELLO_GENERIC_WDOG_BASE 0x2A440000 +#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define MORELLO_GIC_BASE 0x30000000 +#define MORELLO_GICR_BASE 0x300C0000 +#define MORELLO_GIC_SZ SIZE_256KB +#define MORELLO_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000 +#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define MORELLO_EXP_PERIPH_BASE 0x1C000000 +#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000 + +// Platform information structure base address +#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE + +/* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structure + * format. The elements of MORELLO_PLAT_INFO should be always in sync with + * the lower level firmware. + */ +#pragma pack(1) + +typedef struct { + /*! Local DDR memory size in Bytes */ + UINT64 LocalDdrSize; + /*! Remote DDR memory size in Bytes */ + UINT64 RemoteDdrSize; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 Mode; +} MORELLO_PLAT_INFO; + +#pragma pack() + +#endif diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..cd06ca5ce53f --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/BaseLib.h> +#include <Ppi/ArmMpCoreInfo.h> + +STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable = mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..140a6ec79bd3 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,194 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/MemoryAllocationLib.h> +#include <MorelloPlatform.h> + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +#if !defined(MDEPKG_NDEBUG) +STATIC CONST CHAR8 *tblAttrDesc[] = { + "UNCACHED_UNBUFFERED ", + "NONSECURE_UNCACHED_UNBUFFERED", + "WRITE_BACK ", + "NONSECURE_WRITE_BACK ", + "WB_NONSHAREABLE ", + "NONSECURE_WB_NONSHAREABLE ", + "WRITE_THROUGH ", + "NONSECURE_WRITE_THROUGH ", + "DEVICE ", + "NONSECURE_DEVICE " +}; +#endif + +#define LOG_MEM(desc) DEBUG (( \ + EFI_D_ERROR, \ + desc, \ + VirtualMemoryTable[Index].PhysicalBase, \ + (VirtualMemoryTable[Index].PhysicalBase + \ + VirtualMemoryTable[Index].Length - 1), \ + VirtualMemoryTable[Index].Length, \ + tblAttrDesc[VirtualMemoryTable[Index].Attributes] \ + )); + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MORELLO_PLAT_INFO * PlatInfo; + UINT64 DramBlock2Size = 0; + + PlatInfo = (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) + DramBlock2Size = PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE; + + if (DramBlock2Size != 0) { + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + } + + ASSERT (VirtualMemoryMap != NULL); + Index = 0; + + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + if (VirtualMemoryTable == NULL) { + return; + } + + DEBUG (( + EFI_D_ERROR, + " Memory Map\n----------------------------------------------------------\n" + )); + DEBUG (( + EFI_D_ERROR, + "Description : START - END " \ + "[ SIZE ] { ATTR }\n" + )); + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase = MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GIC_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GIC_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GICR_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GICR_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length = MORELLO_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_UART0_BASE; + VirtualMemoryTable[Index].Length = MORELLO_UART0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // DDR Primary + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // DDR Secondary + if (DramBlock2Size != 0) { + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].Length = DramBlock2Size; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + } + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = MORELLO_EXP_PERIPH_BASE_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - + FixedPcdGet32 (PcdPciBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI MMIO32/IO Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size) + + PcdGet32 (PcdPciIoSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI MMIO64 Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..f6cc087a132c --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,83 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary core. +// Primary core is the core responsible to initialize hardware and run UEFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Chandni Cherukuri @ 2021-02-26 18:35 ` Thomas Abraham 2021-03-01 5:21 ` chandni.cherukuri 2021-03-01 13:13 ` Sami Mujawar 1 sibling, 1 reply; 15+ messages in thread From: Thomas Abraham @ 2021-02-26 18:35 UTC (permalink / raw) To: devel@edk2.groups.io, Chandni Cherukuri Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar, nd On 2/24/21 6:42 PM, Chandni Cherukuri via groups.io wrote: > From: Anurag Koul <anurag.koul@arm.com> > > This patch adds initial Morello Platform Library support. > It includes virtual memory map and helper functions for > platform initialization. > > Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> > Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> > --- > Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ > Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ > Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ > Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 > ++++++++++++++++++++ > Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ > 5 files changed, 462 insertions(+) With the platform resources being very similar to that of N1SDP SoC (Silicon/ARM/NeoverseN1Soc), are there opportunities to reuse the NeoverseN1Soc code to build the Morello platform support ? - Thomas [...] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation 2021-02-26 18:35 ` [edk2-devel] " Thomas Abraham @ 2021-03-01 5:21 ` chandni.cherukuri 0 siblings, 0 replies; 15+ messages in thread From: chandni.cherukuri @ 2021-03-01 5:21 UTC (permalink / raw) To: devel, thomas.abraham; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar, nd Hi Thomas, Please find my response marked inline below. On Sat, Feb 27, 2021 at 12:06 AM Thomas Abraham <thomas.abraham@arm.com> wrote: > > On 2/24/21 6:42 PM, Chandni Cherukuri via groups.io wrote: > > From: Anurag Koul <anurag.koul@arm.com> > > > > This patch adds initial Morello Platform Library support. > > It includes virtual memory map and helper functions for > > platform initialization. > > > > Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> > > Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> > > --- > > Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ > > Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ > > Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ > > Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 > > ++++++++++++++++++++ > > Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ > > 5 files changed, 462 insertions(+) > > With the platform resources being very similar to that of N1SDP SoC (Silicon/ARM/NeoverseN1Soc), are there opportunities to reuse the NeoverseN1Soc code to build the Morello platform support ? > > - Thomas > > [...] > > Even though some of the platform resources are similar there are few IPs which are different between the two and one of them is the CPU being used. Morello platform is based on Rainier CPU whereas I assume Silicon/ARM/NeoverseN1Soc is for platforms which are based on NeoverseN1 CPU. Also there is going to be support for both Morello FVP and Morello Silicon platform in the future. Considering these differences I think it would be best to maintain Morello as a separate platform. - Chandni > > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Chandni Cherukuri 2021-02-26 18:35 ` [edk2-devel] " Thomas Abraham @ 2021-03-01 13:13 ` Sami Mujawar 1 sibling, 0 replies; 15+ messages in thread From: Sami Mujawar @ 2021-03-01 13:13 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Please find my response inline marked [SAMI]. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri <chandni.cherukuri@arm.com> Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com> Subject: [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation From: Anurag Koul <anurag.koul@arm.com> This patch adds initial Morello Platform Library support. It includes virtual memory map and helper functions for platform initialization. Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 ++++++++++++++++++++ Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ 5 files changed, 462 insertions(+) diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..2066d1f3a3f8 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = ArmMorelloLib + FILE_GUID = 36853D86-7200-47B4-9408-E962A00963FD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c [SAMI] Reorder in alphabetical order. Same for the FixedPcd section below. [/SAMI] + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base + + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress + gArmMorelloTokenSpaceGuid.PcdPciIoSize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/Morello/Include/MorelloPlatform.h new file mode 100644 index 000000000000..f61cfe7f9ee8 --- /dev/null +++ b/Platform/ARM/Morello/Include/MorelloPlatform.h @@ -0,0 +1,67 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_PLATFORM_H__ +#define MORELLO_PLATFORM_H__ [SAMI] See https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/53_include_files#5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard There is a ECC patch that has been recently merged to catch these issues. I would recommend that you run the ECC tool on the files/folders introduced in this patch series. e.g To run ecc on a folder you could use: python edk2\BaseTools\Source\Python\Ecc\EccMain.py -c edk2\BaseTools\Source\Python\Ecc\config.ini -e edk2\BaseTools\Source\Python\Ecc\exception.xml -r Ecc.csv -t <FolderPath> [/SAMI] + +#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB + +// **************************************************************************** +// Platform Memory Map +// **************************************************************************** + +// SubSystem Peripherals - UART0 +#define MORELLO_UART0_BASE 0x2A400000 +#define MORELLO_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define MORELLO_UART1_BASE 0x2A410000 +#define MORELLO_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define MORELLO_GENERIC_WDOG_BASE 0x2A440000 +#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define MORELLO_GIC_BASE 0x30000000 +#define MORELLO_GICR_BASE 0x300C0000 +#define MORELLO_GIC_SZ SIZE_256KB +#define MORELLO_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000 +#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define MORELLO_EXP_PERIPH_BASE 0x1C000000 +#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000 + +// Platform information structure base address +#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE + +/* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structure + * format. The elements of MORELLO_PLAT_INFO should be always in sync with + * the lower level firmware. + */ +#pragma pack(1) + +typedef struct { + /*! Local DDR memory size in Bytes */ [SAMI] The doxygen comment stype to be used should be /** instead of /*!. Alternatively, you could also follow https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/appendix_a_common_examples#type-declarations [/SAMI] + UINT64 LocalDdrSize; + /*! Remote DDR memory size in Bytes */ + UINT64 RemoteDdrSize; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 Mode; +} MORELLO_PLAT_INFO; + +#pragma pack() + +#endif diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..cd06ca5ce53f --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/BaseLib.h> +#include <Ppi/ArmMpCoreInfo.h> + +STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) [SAMI] Please add doxygen function documentation header. Same at other places in this patch series. [/SAMI] +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable = mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..140a6ec79bd3 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,194 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/MemoryAllocationLib.h> +#include <MorelloPlatform.h> + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +#if !defined(MDEPKG_NDEBUG) +STATIC CONST CHAR8 *tblAttrDesc[] = { + "UNCACHED_UNBUFFERED ", + "NONSECURE_UNCACHED_UNBUFFERED", + "WRITE_BACK ", + "NONSECURE_WRITE_BACK ", + "WB_NONSHAREABLE ", + "NONSECURE_WB_NONSHAREABLE ", + "WRITE_THROUGH ", + "NONSECURE_WRITE_THROUGH ", + "DEVICE ", + "NONSECURE_DEVICE " +}; +#endif + +#define LOG_MEM(desc) DEBUG (( \ + EFI_D_ERROR, \ [SAMI] Replace EFI_D_ERROR with DEBUG_ERROR at all places in this patch series. [/SAMI] + desc, \ + VirtualMemoryTable[Index].PhysicalBase, \ + (VirtualMemoryTable[Index].PhysicalBase + \ + VirtualMemoryTable[Index].Length - 1), \ + VirtualMemoryTable[Index].Length, \ + tblAttrDesc[VirtualMemoryTable[Index].Attributes] \ + )); + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MORELLO_PLAT_INFO * PlatInfo; + UINT64 DramBlock2Size = 0; + + PlatInfo = (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) [SAMI] Add { } braces, see https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/57_c_programming#5-7-3-4-1-the-if-statement-shall-be-followed-by-a-space-and-then-the-open-parenthesis + DramBlock2Size = PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE; + + if (DramBlock2Size != 0) { + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + } + + ASSERT (VirtualMemoryMap != NULL); + Index = 0; [SAMI] Redundant. [/SAMI] + + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + if (VirtualMemoryTable == NULL) { + return; + } + + DEBUG (( + EFI_D_ERROR, + " Memory Map\n----------------------------------------------------------\n" + )); + DEBUG (( + EFI_D_ERROR, + "Description : START - END " \ + "[ SIZE ] { ATTR }\n" + )); + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase = MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GIC_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GIC_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GICR_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GICR_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length = MORELLO_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_UART0_BASE; + VirtualMemoryTable[Index].Length = MORELLO_UART0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // DDR Primary + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // DDR Secondary + if (DramBlock2Size != 0) { + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].Length = DramBlock2Size; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + } + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = MORELLO_EXP_PERIPH_BASE_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - + FixedPcdGet32 (PcdPciBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI MMIO32/IO Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size) + + PcdGet32 (PcdPciIoSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI MMIO64 Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..f6cc087a132c --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,83 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary core. +// Primary core is the core responsible to initialize hardware and run UEFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Chandni Cherukuri @ 2021-02-24 13:12 ` Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello Chandni Cherukuri ` (3 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Chandni Cherukuri @ 2021-02-24 13:12 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar Morello FVP platform supports a PCIe root complex. This patch implements PciHostBridgeLib to support PCIe. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf | 48 ++++++ Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c | 182 ++++++++++++++++++++ 2 files changed, 230 insertions(+) diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf new file mode 100644 index 000000000000..3220704b2984 --- /dev/null +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf @@ -0,0 +1,48 @@ +## @file +# PCI Host Bridge Library instance for ARM Morello FVP platform. +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PciHostBridgeLib + FILE_GUID = 6879CEAD-DC94-42EB-895C-096D36B8083C + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + PciHostBridgeLibFvp.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c new file mode 100644 index 000000000000..a88da8950362 --- /dev/null +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c @@ -0,0 +1,182 @@ +/** @file + PCI Host Bridge Library instance for ARM Morello FVP platform. + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/PciHostBridgeLib.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> + +#define ROOT_COMPLEX_NUM 1 + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID(0x0A08), + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + }, +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count = ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib Chandni Cherukuri @ 2021-03-01 13:13 ` Sami Mujawar 0 siblings, 0 replies; 15+ messages in thread From: Sami Mujawar @ 2021-03-01 13:13 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Please find my response inline marked [SAMI]. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri <chandni.cherukuri@arm.com> Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com> Subject: [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib Morello FVP platform supports a PCIe root complex. This patch implements PciHostBridgeLib to support PCIe. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf | 48 ++++++ Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c | 182 ++++++++++++++++++++ 2 files changed, 230 insertions(+) diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf new file mode 100644 index 000000000000..3220704b2984 --- /dev/null +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf @@ -0,0 +1,48 @@ +## @file +# PCI Host Bridge Library instance for ARM Morello FVP platform. +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PciHostBridgeLib + FILE_GUID = 6879CEAD-DC94-42EB-895C-096D36B8083C + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + PciHostBridgeLibFvp.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec [SAMI] Reorder in alphabetical order. [/SAMI] + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c new file mode 100644 index 000000000000..a88da8950362 --- /dev/null +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c @@ -0,0 +1,182 @@ +/** @file + PCI Host Bridge Library instance for ARM Morello FVP platform. + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/PciHostBridgeLib.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> + +#define ROOT_COMPLEX_NUM 1 + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID(0x0A08), + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + }, +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count = ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) [SAMI] ARRAY_SIZE() ? [/SAMI] + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Chandni Cherukuri 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib Chandni Cherukuri @ 2021-02-24 13:12 ` Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager " Chandni Cherukuri ` (2 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Chandni Cherukuri @ 2021-02-24 13:12 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar From: Anurag Koul <anurag.koul@arm.com> This patch adds the PlatformDxe Driver for Morello platform. It includes the registration of the ramdisk device. Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf | 43 +++++++++ Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h | 14 +++ Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c | 58 +++++++++++++ Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c | 91 ++++++++++++++++++++ 4 files changed, 206 insertions(+) diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf new file mode 100644 index 000000000000..69df9019cde3 --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformDxe + FILE_GUID = 11FC8B5A-377D-47A8-AEE9-0093D3D3407F + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ArmMorelloEntryPoint + +[Sources.common] + PlatformDxeFvp.c + VirtioDevices.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + VirtioMmioDeviceLib + +[Protocols] + gEfiRamDiskProtocolGuid + +[FeaturePcd] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdRamDiskBase + gArmMorelloTokenSpaceGuid.PcdRamDiskSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + +[Depex] + gEfiRamDiskProtocolGuid diff --git a/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h new file mode 100644 index 000000000000..27ae61bb1cf5 --- /dev/null +++ b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h @@ -0,0 +1,14 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_VIRTIO_DEVICES_FORMSET_H__ +#define MORELLO_VIRTIO_DEVICES_FORMSET_H__ + +#define MORELLO_VIRTIO_BLOCK_GUID \ + { 0x2B6E62D0, 0x9346, 0x4E1A, { 0xAA, 0x1E, 0xCB, 0x01, 0xC3, 0x23, 0x4A, 0x00 } } + +#endif diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c new file mode 100644 index 000000000000..ff99c16b2c9a --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c @@ -0,0 +1,58 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/RamDisk.h> + +VOID +InitVirtioDevices ( + VOID + ); + +EFI_STATUS +EFIAPI +ArmMorelloEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RAM_DISK_PROTOCOL *RamDisk; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status = EFI_SUCCESS; + + InitVirtioDevices (); + + if (FeaturePcdGet (PcdRamDiskSupported)) { + Status = gBS->LocateProtocol ( + &gEfiRamDiskProtocolGuid, + NULL, + (VOID**)&RamDisk + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Couldn't find the RAM Disk protocol %r\n", + __FUNCTION__, Status)); + return Status; + } + + Status = RamDisk->Register ( + (UINTN)PcdGet32 (PcdRamDiskBase), + (UINTN)PcdGet32 (PcdRamDiskSize), + &gEfiVirtualCdGuid, + NULL, + &DevicePath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to register RAM Disk - %r\n", + __FUNCTION__, Status)); + } + } + + return Status; +} diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c new file mode 100644 index 000000000000..a83a4e71a47e --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Guid/MorelloVirtioDevicesFormSet.h> +#include <Library/VirtioMmioDeviceLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} VIRTIO_DEVICE_PATH; +#pragma pack () + +STATIC VIRTIO_DEVICE_PATH mVirtioBlockDevicePath = +{ + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + MORELLO_VIRTIO_BLOCK_GUID, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +// +// Initialize platform Virtio devices. +// +// @return None. +// +VOID +InitVirtioDevices ( + VOID + ) +{ + EFI_STATUS Status; + STATIC EFI_HANDLE mVirtIoBlkController = NULL; + + Status = EFI_SUCCESS; + + // Install protocol interface for storage device + if (FeaturePcdGet (PcdVirtioBlkSupported)) { + + Status = gBS->InstallProtocolInterface ( + &mVirtIoBlkController, + &gEfiDevicePathProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtioBlockDevicePath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to install EFI_DEVICE_PATH protocol " + "for Virtio Block device (Status = %r)\n", + __FUNCTION__, Status)); + } else { + // Declare the Virtio BlockIo device + Status = VirtioMmioInstallDevice ( + FixedPcdGet32 (PcdVirtioBlkBaseAddress), + mVirtIoBlkController + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find Virtio Block MMIO device " + "(Status == %r)\n", __FUNCTION__, Status)); + gBS->UninstallProtocolInterface ( + mVirtIoBlkController, + &gEfiDevicePathProtocolGuid, + &mVirtioBlockDevicePath + ); + } else { + DEBUG ((DEBUG_INIT, "%a: Installed Virtio Block device\n", + __FUNCTION__)); + } + } + } +} -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello Chandni Cherukuri @ 2021-03-01 13:13 ` Sami Mujawar 0 siblings, 0 replies; 15+ messages in thread From: Sami Mujawar @ 2021-03-01 13:13 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Please find my response inline marked [SAMI]. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri <chandni.cherukuri@arm.com> Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com> Subject: [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello From: Anurag Koul <anurag.koul@arm.com> This patch adds the PlatformDxe Driver for Morello platform. It includes the registration of the ramdisk device. Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf | 43 +++++++++ Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h | 14 +++ Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c | 58 +++++++++++++ Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c | 91 ++++++++++++++++++++ 4 files changed, 206 insertions(+) diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf new file mode 100644 index 000000000000..69df9019cde3 --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformDxe + FILE_GUID = 11FC8B5A-377D-47A8-AEE9-0093D3D3407F + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ArmMorelloEntryPoint + +[Sources.common] + PlatformDxeFvp.c + VirtioDevices.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + VirtioMmioDeviceLib + +[Protocols] + gEfiRamDiskProtocolGuid + +[FeaturePcd] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdRamDiskBase + gArmMorelloTokenSpaceGuid.PcdRamDiskSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + +[Depex] + gEfiRamDiskProtocolGuid diff --git a/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h new file mode 100644 index 000000000000..27ae61bb1cf5 --- /dev/null +++ b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h @@ -0,0 +1,14 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_VIRTIO_DEVICES_FORMSET_H__ +#define MORELLO_VIRTIO_DEVICES_FORMSET_H__ + +#define MORELLO_VIRTIO_BLOCK_GUID \ + { 0x2B6E62D0, 0x9346, 0x4E1A, { 0xAA, 0x1E, 0xCB, 0x01, 0xC3, 0x23, 0x4A, 0x00 } } + +#endif diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c new file mode 100644 index 000000000000..ff99c16b2c9a --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c @@ -0,0 +1,58 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/RamDisk.h> + +VOID +InitVirtioDevices ( + VOID + ); + +EFI_STATUS +EFIAPI +ArmMorelloEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RAM_DISK_PROTOCOL *RamDisk; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status = EFI_SUCCESS; + + InitVirtioDevices (); + + if (FeaturePcdGet (PcdRamDiskSupported)) { + Status = gBS->LocateProtocol ( + &gEfiRamDiskProtocolGuid, + NULL, + (VOID**)&RamDisk + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Couldn't find the RAM Disk protocol %r\n", + __FUNCTION__, Status)); + return Status; + } + + Status = RamDisk->Register ( + (UINTN)PcdGet32 (PcdRamDiskBase), + (UINTN)PcdGet32 (PcdRamDiskSize), + &gEfiVirtualCdGuid, + NULL, + &DevicePath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to register RAM Disk - %r\n", + __FUNCTION__, Status)); + } + } + + return Status; +} diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c new file mode 100644 index 000000000000..a83a4e71a47e --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Guid/MorelloVirtioDevicesFormSet.h> +#include <Library/VirtioMmioDeviceLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} VIRTIO_DEVICE_PATH; +#pragma pack () + +STATIC VIRTIO_DEVICE_PATH mVirtioBlockDevicePath = +{ + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + MORELLO_VIRTIO_BLOCK_GUID, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +// +// Initialize platform Virtio devices. +// +// @return None. +// +VOID +InitVirtioDevices ( + VOID + ) [SAMI] Use doxygen style function documentation headers. [/SAMI] +{ + EFI_STATUS Status; + STATIC EFI_HANDLE mVirtIoBlkController = NULL; [SAMI] Why is this variable static? [/SAMI] + + Status = EFI_SUCCESS; [SAMI] Is this needed? Should this function return the Status code? [/SAMI] + + // Install protocol interface for storage device + if (FeaturePcdGet (PcdVirtioBlkSupported)) { + + Status = gBS->InstallProtocolInterface ( + &mVirtIoBlkController, + &gEfiDevicePathProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtioBlockDevicePath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to install EFI_DEVICE_PATH protocol " + "for Virtio Block device (Status = %r)\n", + __FUNCTION__, Status)); + } else { + // Declare the Virtio BlockIo device + Status = VirtioMmioInstallDevice ( + FixedPcdGet32 (PcdVirtioBlkBaseAddress), + mVirtIoBlkController + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find Virtio Block MMIO device " + "(Status == %r)\n", __FUNCTION__, Status)); + gBS->UninstallProtocolInterface ( + mVirtIoBlkController, + &gEfiDevicePathProtocolGuid, + &mVirtioBlockDevicePath + ); + } else { + DEBUG ((DEBUG_INIT, "%a: Installed Virtio Block device\n", + __FUNCTION__)); + } + } + } +} -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager for Morello 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri ` (2 preceding siblings ...) 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello Chandni Cherukuri @ 2021-02-24 13:12 ` Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform Chandni Cherukuri 2021-03-01 13:13 ` [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Sami Mujawar 5 siblings, 1 reply; 15+ messages in thread From: Chandni Cherukuri @ 2021-02-24 13:12 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar This patch implements the configuration manager for Morello platform. It enables support for generating the following ACPI tables for Morello FVP Platform: 1. FADT 2. DSDT 3. GTDT 4. MADT 5. SPCR 6. DBG2 7. PPTT 8. IORT 9. MCFG 10. SSDT Structures have been created to add Common Platform information and FVP/Testchip platform specific information so that the same Dxe is usable for all variants of the platform. Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc | 16 + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf | 94 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 304 ++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h | 81 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h | 91 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 1005 ++++++++++++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c | 531 +++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl | 114 +++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl | 130 +++ 9 files changed, 2366 insertions(+) diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc new file mode 100644 index 000000000000..71916783c24c --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc @@ -0,0 +1,16 @@ +## @file +# dsc include file for Configuration Manager +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + +[BuildOptions] + +[Components.common] + # Configuration Manager + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf new file mode 100644 index 000000000000..9137de2dd118 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf @@ -0,0 +1,94 @@ +## @file +# Configuration Manager Dxe +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ConfigurationManagerDxe + FILE_GUID = 6F9C3B47-6F7D-44B6-87E5-4B7F44A60147 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ConfigurationManagerDxeInitialize + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + AslTables/DsdtFvp.asl + AslTables/SsdtPciFvp.asl + ConfigurationManagerFvp.c + ConfigurationManager.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + DynamicTablesPkg/DynamicTablesPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Protocols] + gEdkiiConfigurationManagerProtocolGuid + +[FixedPcd] + ## PL011 Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + # SBSA Generic Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt + + # PCI + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciBusCount + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress +[Pcd] + +[Depex] + TRUE diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h new file mode 100644 index 000000000000..b44270639001 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h @@ -0,0 +1,304 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef CONFIGURATION_MANAGER_H__ +#define CONFIGURATION_MANAGER_H__ + +/** The configuration manager version. +*/ +#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0) + +/** The OEM ID +*/ +#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' } +#define CFG_MGR_OEM_REVISION 0x20181101 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&CommonPlatformInfo + \ + OFFSET_OF (EDKII_COMMON_PLATFORM_REPOSITORY_INFO, Field)) + +/** A helper macro that constructs the MPID based on the + Aff0, Aff1, Aff2, Aff3 values +*/ +#define GET_MPID3(Aff3, Aff2, Aff1, Aff0) \ + (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0)) + +/** A helper macro for populating the GIC CPU information +*/ +#define GICC_ENTRY( \ + CPUInterfaceNumber, \ + Mpidr, \ + PmuIrq, \ + VGicIrq, \ + GicRedistBase, \ + EnergyEfficiency, \ + SpeIrq, \ + ProximityDomain, \ + ClockDomain \ + ) { \ + CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \ + CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \ + EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ + PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \ + 0, /* UINT64 ParkedAddress */ \ + FixedPcdGet64 ( \ + PcdGicInterruptInterfaceBase \ + ), /* UINT64 PhysicalBaseAddress */ \ + 0, /* UINT64 GICV */ \ + 0, /* UINT64 GICH */ \ + VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \ + GicRedistBase, /* UINT64 GICRBaseAddress */ \ + Mpidr, /* UINT64 MPIDR */ \ + EnergyEfficiency, /* UINT8 ProcessorPowerEfficiencyClass*/ \ + SpeIrq, /* UINT16 SpeOverflowInterrupt */ \ + ProximityDomain, /* UINT32 ProximityDomain */ \ + ClockDomain, /* UINT32 ClockDomain */ \ + EFI_ACPI_6_3_GICC_ENABLED,/* UINT32 Flags */ \ + } + +/** A helper macro for populating the Processor Hierarchy Node flags +*/ +#define PROC_NODE_FLAGS( \ + PhysicalPackage, \ + AcpiProcessorIdValid, \ + ProcessorIsThread, \ + NodeIsLeaf, \ + IdenticalImplementation \ + ) \ + ( \ + PhysicalPackage | \ + (AcpiProcessorIdValid << 1) | \ + (ProcessorIsThread << 2) | \ + (NodeIsLeaf << 3) | \ + (IdenticalImplementation << 4) \ + ) + +/** A helper macro for populating the Cache Type Structure's attributes +*/ +#define CACHE_ATTRIBUTES( \ + AllocationType, \ + CacheType, \ + WritePolicy \ + ) \ + ( \ + AllocationType | \ + (CacheType << 2) | \ + (WritePolicy << 4) \ + ) + +/** A helper macro for returning configuration manager objects +*/ +#define HANDLE_CM_OBJECT(ObjId, CmObjectId, Object, ObjectCount) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + CmObject->Size = sizeof (Object); \ + CmObject->Data = (VOID*)&Object; \ + CmObject->Count = ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr = 0x%p, Size = %d, Count = %d\n", \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + break; \ + } + +/** A helper macro for returning configuration manager objects + referenced by token +*/ +#define HANDLE_CM_OBJECT_REF_BY_TOKEN( \ + ObjId, \ + CmObjectId, \ + Object, \ + ObjectCount, \ + Token, \ + HandlerProc \ + ) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + if (Token == CM_NULL_TOKEN) { \ + CmObject->Size = sizeof (Object); \ + CmObject->Data = (VOID*)&Object; \ + CmObject->Count = ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr = 0x%p, Size = %d, Count = %d\n", \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } else { \ + Status = HandlerProc (This, CmObjectId, Token, CmObject); \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Token = 0x%p, Ptr = 0x%p, Size = %d, Count = %d\n", \ + (VOID*)Token, \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } \ + break; \ + } + +/** A helper macro for returning configuration manager objects referenced + by token when the entire platform repository is in scope and the + CM_NULL_TOKEN value is not allowed. +*/ +#define HANDLE_CM_OBJECT_SEARCH_PLAT_REPO( \ + ObjId, \ + CmObjectId, \ + Token, \ + HandlerProc \ + ) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + if (Token == CM_NULL_TOKEN) { \ + Status = EFI_INVALID_PARAMETER; \ + DEBUG (( \ + DEBUG_ERROR, \ + #ObjId ": CM_NULL_TOKEN value is not allowed when searching" \ + " the entire platform repository.\n" \ + )); \ + } else { \ + Status = HandlerProc (This, CmObjectId, Token, CmObject); \ + DEBUG (( \ + DEBUG_INFO, \ + #ObjId ": Token = 0x%p, Ptr = 0x%p, Size = %d, Count = %d\n", \ + (VOID*)Token, \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } \ + break; \ + } + +/** The number of CPUs +*/ +#define PLAT_CPU_COUNT 4 + +/** The number of platform generic timer blocks +*/ +#define PLAT_GTBLOCK_COUNT 1 + +/** The number of timer frames per generic timer block +*/ +#define PLAT_GTFRAME_COUNT 2 + +/** The number of Processor Hierarchy Nodes + - one package node + - two cluster nodes + - two cores in cluster 0 + - two cores in cluster 1 +*/ +#define PLAT_PROC_HIERARCHY_NODE_COUNT 7 + +/** The number of unique cache structures: + - cluster L3 unified cache + - core L1 instruction cache + - core L1 data cache + - core L2 cache + - slc unified cache +*/ +#define PLAT_CACHE_COUNT 5 + +/** The number of resources private to the cluster + - L3 cache +*/ +#define CLUSTER_RESOURCE_COUNT 1 + +/** The number of resources private to 'core instance + - L1 data cache + - L1 instruction cache + - L2 cache +*/ +#define CORE_RESOURCE_COUNT 3 + +/** The number of resources private to SoC + - slc cache + - Proc Node Id Info +*/ +#define SOC_RESOURCE_COUNT 2 + +/** A structure describing the platform configuration + manager repository information +*/ +typedef struct CommonPlatformRepositoryInfo { + /// Configuration Manager Information + CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo; + + /// Boot architecture information + CM_ARM_BOOT_ARCH_INFO BootArchInfo; + +#ifdef HEADLESS_PLATFORM + /// Fixed feature flag information + CM_ARM_FIXED_FEATURE_FLAGS FixedFeatureFlags; +#endif + + /// Power management profile information + CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo; + + /// GIC CPU interface information + CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT]; + + /// GIC distributor information + CM_ARM_GICD_INFO GicDInfo; + + /// GIC Redistributor information + CM_ARM_GIC_REDIST_INFO GicRedistInfo; + + /// Generic timer information + CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo; + + /// Generic timer block information + CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT]; + + /// Generic timer frame information + CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COUNT]; + + /// Watchdog information + CM_ARM_GENERIC_WATCHDOG_INFO Watchdog; + + /** Serial port information for the + serial port console redirection port + */ + CM_ARM_SERIAL_PORT_INFO SpcrSerialPort; + + /// Serial port information for the DBG2 UART port + CM_ARM_SERIAL_PORT_INFO DbgSerialPort; + + // Processor topology information + CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT]; + + // Processor Node Id Info + CM_ARM_PROC_NODE_ID_INFO ProcNodeIdInfo; + + + // Cache information + CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT]; + + // Cluster private resources + CM_ARM_OBJ_REF ClusterResources[CLUSTER_RESOURCE_COUNT]; + + // Core private resources + CM_ARM_OBJ_REF CoreResources[CORE_RESOURCE_COUNT]; + + // SoC Resources + CM_ARM_OBJ_REF SocResources[SOC_RESOURCE_COUNT]; + +} EDKII_COMMON_PLATFORM_REPOSITORY_INFO; + +#endif // CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h new file mode 100644 index 000000000000..be0f02fab1ce --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h @@ -0,0 +1,81 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef FVP_CONFIGURATION_MANAGER_H__ +#define FVP_CONFIGURATION_MANAGER_H__ + +#include "ConfigurationManager.h" + +/** The number of ACPI tables to install +*/ +#define PLAT_ACPI_TABLE_COUNT 10 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN_FVP(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&MorelloFvpRepositoryInfo + \ + OFFSET_OF (EDKII_FVP_PLATFORM_REPOSITORY_INFO, Field)) + +/** C array containing the compiled AML template. + These symbols are defined in the auto generated C file + containing the AML bytecode array. +*/ +extern CHAR8 dsdtfvp_aml_code[]; +extern CHAR8 ssdtpcifvp_aml_code[]; + +//Add FVP Platform specific information +typedef struct FvpPlatformRepositoryInfo { + /// List of ACPI tables + CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT]; + + /// GIC ITS information + CM_ARM_GIC_ITS_INFO GicItsInfo[2]; + + /// ITS Group node + CM_ARM_ITS_GROUP_NODE ItsGroupInfo[2]; + + /// ITS Identifier array + CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[2]; + + /// SMMUv3 node + CM_ARM_SMMUV3_NODE SmmuV3Info[1]; + + /// PCI Root complex node + CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[1]; + + /// Array of DeviceID mapping + CM_ARM_ID_MAPPING DeviceIdMapping[2][2]; + + /// PCI configuration space information + CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[1]; + +} EDKII_FVP_PLATFORM_REPOSITORY_INFO; + +typedef struct PlatformRepositoryInfo { + + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepoInfo; + + EDKII_FVP_PLATFORM_REPOSITORY_INFO * FvpPlatRepoInfo; + +} EDKII_PLATFORM_REPOSITORY_INFO; + +extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo; + +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ); + +#endif // FVP_CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h new file mode 100644 index 000000000000..2e5286e892df --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PLATFORM_H__ +#define PLATFORM_H__ + +#define ENABLE_MEM_MAPPED_TIMER + +#ifdef ENABLE_MEM_MAPPED_TIMER +// REFCLK CNTControl +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0x2A430000 +// REFCLK CNTRead +#define MORELLO_CNT_READ_BASE_ADDRESS 0x2A800000 +#else +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#define MORELLO_CNT_READ_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +// GT Block Timer +// AP_REFCLK CNTCTL +#define MORELLO_GT_BLOCK_CTL_BASE 0x2A810000 +#define MORELLO_TIMER_FRAMES_COUNT 2 + +// GT Block Timer Frames +// AP_REFCLK_NS CNTBase0 +#define MORELLO_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000 +#define MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME0_GSIV 92 + +// AP_REFCLK_S CNTBase1 +#define MORELLO_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000 +#define MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME1_GSIV 91 + +#define GTDT_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | \ + GTDT_TIMER_ACTIVE_LOW | \ + GTDT_TIMER_LEVEL_TRIGGERED) + +// GT Block Timer Flags +#define GTX_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define MORELLO_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | \ + GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_SECURE) +#define MORELLO_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_NON_SECURE) + +// Watchdog +#define SBSA_WATCHDOG_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define MORELLO_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | \ + SBSA_WATCHDOG_ACTIVE_HIGH | \ + SBSA_WATCHDOG_LEVEL_TRIGGERED) + +#endif // PLATFORM_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c new file mode 100644 index 000000000000..e324cc50853f --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c @@ -0,0 +1,1005 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include <IndustryStandard/DebugPort2Table.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/ConfigurationManagerProtocol.h> + +#include "ConfigurationManagerFvp.h" +#include "ConfigurationManager.h" +#include "Platform.h" + +extern EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo; + +// The platform configuration repository information. +EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo = { + // Configuration Manager information + { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID }, + + // Boot architecture information + { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags + +#ifdef HEADLESS_PLATFORM + // Fixed feature flag information + { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags +#endif + + // Power management profile information + { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile + + /* GIC CPU Interface information + GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase, + EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain) + */ + { + GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + }, + + // GIC Distributor Info + { + FixedPcdGet64 (PcdGicDistributorBase), // UINT64 PhysicalBaseAddress + 0, // UINT32 SystemVectorBase + 3 // UINT8 GicVersion + }, + + // GIC Re-Distributor Info + { + // UINT64 DiscoveryRangeBaseAddress + FixedPcdGet64 (PcdGicRedistributorsBase), + // UINT32 DiscoveryRangeLength + SIZE_1MB + }, + + // Generic Timer Info + { + // The physical base address for the counter control frame + MORELLO_SYSTEM_TIMER_BASE_ADDRESS, + // The physical base address for the counter read frame + MORELLO_CNT_READ_BASE_ADDRESS, + // The secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), + // The secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerIntrNum), + // The non-secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The virtual timer interrupt + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), + // The virtual timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL2 timer interrupt + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), + // The non-secure PL2 timer flags + MORELLO_GTDT_GTIMER_FLAGS + }, + + // Generic Timer Block Information + { + { + // The physical base address for the GT Block Timer structure + MORELLO_GT_BLOCK_CTL_BASE, + // The number of timer frames implemented in the GT Block + MORELLO_TIMER_FRAMES_COUNT, + // Reference token for the GT Block timer frame list + REFERENCE_TOKEN (GTBlock0TimerInfo) + } + }, + + // GT Block Timer Frames + { + // Frame 0 + { + 0, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 PhysicalAddressCntBase + MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base + MORELLO_GT_BLOCK_FRAME0_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_NS // UINT32 CommonFlags + }, + // Frame 1 + { + 1, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 PhysicalAddressCntBase + MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base + MORELLO_GT_BLOCK_FRAME1_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_S // UINT32 CommonFlags + }, + }, + + // Watchdog Info + { + // The physical base address of the SBSA Watchdog control frame + FixedPcdGet64 (PcdGenericWatchdogControlBase), + // The physical base address of the SBSA Watchdog refresh frame + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), + // The watchdog interrupt + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + // The watchdog flags + MORELLO_SBSA_WATCHDOG_FLAGS + }, + + // SPCR Serial Port + { + FixedPcdGet64 (PcdSerialRegisterBase), // BaseAddress + FixedPcdGet32 (PL011UartInterrupt), // Interrupt + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet32 (PL011UartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Debug Serial Port + { + FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress + 0, // Interrupt -unused + FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate + FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Processor Hierarchy Nodes + { + // Package + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[0]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + CM_NULL_TOKEN, + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + SOC_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (SocResources) + }, + + // Cluster0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[1]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[2]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster0 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[0]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster0 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[1]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster1 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[2]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + + // Cluster1 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[3]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + }, + + // Processor Node Id Info + { + // A unique token used to identify this object + REFERENCE_TOKEN (ProcNodeIdInfo), + // Vendor ID (as described in ACPI ID registry) + SIGNATURE_32('A', 'R', 'M', 'H'), + // First level unique node ID + 0, + // Second level unique node ID + 0, + // Major revision of the node + 0, + // Minor revision of the node + 0, + // Spin revision of the node + 0 + }, + + // Cache information + { + // 'cluster's L3 cache + { + REFERENCE_TOKEN (CacheInfo[0]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 instruction cache + { + REFERENCE_TOKEN (CacheInfo[1]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 data cache + { + REFERENCE_TOKEN (CacheInfo[2]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // cores's L2 cache + { + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // slc cache + { + REFERENCE_TOKEN (CacheInfo[4]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_8MB, // UINT32 Size + 4096, // UINT32 NumberOfSets + 16, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + }, + // Resources private to the 'cluster (shared among cores) in Cluster + { + { REFERENCE_TOKEN (CacheInfo[0]) } // -> 'cluster's L3 cache in Cluster + }, + // Resources private to each individual 'core instance in Cluster + { + { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[2]) }, // -> 'core's L1 D-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[3]) } // -> 'core's L2 cache in Cluster + }, + + // Resources private to the SoC + { + { REFERENCE_TOKEN (CacheInfo[4]) }, // -> slc for SoC + { REFERENCE_TOKEN (ProcNodeIdInfo) }, // -> ProcNodeIdInfo for SoC + }, +}; + +/** Initialize the Platform Configuration Repository. + + @param [in] This Pointer to the Platform Configuration Repository. + + @retval + EFI_SUCCESS Success +**/ +STATIC +EFI_STATUS +EFIAPI +InitializePlatformRepository ( + IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatformRepo + ) +{ + return EFI_SUCCESS; +} + +/** Return a GT Block timer frame info list. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetGTBlockTimerFrameInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo; + + if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) { + return EFI_NOT_FOUND; + } + + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->GTBlock0TimerInfo); + CmObject->Data = (VOID*)&PlatformRepo->GTBlock0TimerInfo; + CmObject->Count = sizeof (PlatformRepo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->GTBlock0TimerInfo[0]); + return EFI_SUCCESS; +} + +/** Return GIC CPU Interface Info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the requested + CM_ARM_GICC_INFO object. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetGicCInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 TotalObjCount; + UINT32 ObjIndex; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo; + TotalObjCount = PLAT_CPU_COUNT; + + for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) { + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjIndex]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->GicCInfo[ObjIndex]); + CmObject->Data = (VOID*)&PlatformRepo->GicCInfo[ObjIndex]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return a list of Configuration Manager object references pointed to by the + given input token. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the requested + CM_ARM_OBJ_REF list. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetCmObjRefs ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo; + + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->ClusterResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->ClusterResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->ClusterResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->ClusterResources); + return EFI_SUCCESS; + } + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->CoreResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->CoreResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->CoreResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CoreResources); + return EFI_SUCCESS; + } + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->SocResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->SocResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->SocResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->SocResources); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** Return a standard namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetStandardNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EStdObjCfgMgrInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CmInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EStdObjAcpiTableList, + CmObjectId, + PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList, + (sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList) / + sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList[0])) + ); + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 GicRedistCount; + UINT32 GicCpuCount; + UINT32 ProcHierarchyInfoCount; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo; + + GicRedistCount = 1; + GicCpuCount = PLAT_CPU_COUNT; + ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT; + + Status = GetArmNameSpaceObjectPlat (This, CmObjectId, Token, CmObject); + + if (Status == EFI_NOT_FOUND) { + + Status = EFI_SUCCESS; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjBootArchInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->BootArchInfo, + 1 + ); + +#ifdef HEADLESS_PLATFORM + HANDLE_CM_OBJECT ( + EArmObjFixedFeatureFlags, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->FixedFeatureFlags, + 1 + ); +#endif + HANDLE_CM_OBJECT ( + EArmObjPowerManagementProfileInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->PmProfileInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGenericTimerInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GenericTimerInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGenericWatchdogInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->Watchdog, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGTBlockInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlockInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo[0])) + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGTBlockTimerFrameInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo[0])), + Token, + GetGTBlockTimerFrameInfo + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicCInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicCInfo, + GicCpuCount, + Token, + GetGicCInfo + ); + HANDLE_CM_OBJECT ( + EArmObjGicDInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicDInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGicRedistributorInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicRedistInfo, + GicRedistCount + ); + HANDLE_CM_OBJECT ( + EArmObjSerialConsolePortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->SpcrSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjSerialDebugPortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->DbgSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjProcHierarchyInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcHierarchyInfo, + ProcHierarchyInfoCount + ); + HANDLE_CM_OBJECT ( + EArmObjProcNodeIdInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcNodeIdInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjCacheInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CacheInfo, + ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CacheInfo) + ); + HANDLE_CM_OBJECT_SEARCH_PLAT_REPO ( + EArmObjCmRef, + CmObjectId, + Token, + GetCmObjRefs + ); + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_INFO, + "INFO: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + }//switch + } + return Status; +} + +/** Return an OEM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetOemNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The GetObject function defines the interface implemented by the + Configuration Manager Protocol for returning the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformGetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_NAMESPACE_ID (CmObjectId)) { + case EObjNameSpaceStandard: + Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceArm: + Status = GetArmNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceOem: + Status = GetOemNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + default: { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The SetObject function defines the interface implemented by the + Configuration Manager Protocol for updating the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in] CmObject Pointer to the Configuration Manager Object + descriptor describing the Object. + + @retval EFI_UNSUPPORTED This operation is not supported. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformSetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + return EFI_UNSUPPORTED; +} + +/** A structure describing the configuration manager protocol interface. +*/ +STATIC +CONST +EDKII_CONFIGURATION_MANAGER_PROTOCOL MorelloPlatformConfigManagerProtocol = { + CREATE_REVISION(1,0), + MorelloPlatformGetObject, + MorelloPlatformSetObject, + &MorelloRepositoryInfo +}; + +/** + Entrypoint of Configuration Manager Dxe. + + @param ImageHandle + @param SystemTable + + @return EFI_SUCCESS + @return EFI_LOAD_ERROR + @return EFI_OUT_OF_RESOURCES + +**/ +EFI_STATUS +EFIAPI +ConfigurationManagerDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE * SystemTable + ) +{ + EFI_STATUS Status; + + // Initialize the Platform Configuration Repository before installing the + // Configuration Manager Protocol + Status = InitializePlatformRepository ( + MorelloPlatformConfigManagerProtocol.PlatRepoInfo + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to initialize the Platform Configuration Repository." \ + " Status = %r\n", + Status + )); + } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gEdkiiConfigurationManagerProtocolGuid, + EFI_NATIVE_INTERFACE, + (VOID*)&MorelloPlatformConfigManagerProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to get Install Configuration Manager Protocol." \ + " Status = %r\n", + Status + )); + goto error_handler; + } + +error_handler: + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c new file mode 100644 index 000000000000..b50a9db220a2 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c @@ -0,0 +1,531 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include <IndustryStandard/DebugPort2Table.h> +#include <IndustryStandard/IoRemappingTable.h> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/ConfigurationManagerProtocol.h> + +#include "ConfigurationManagerFvp.h" +#include "Platform.h" + +EDKII_FVP_PLATFORM_REPOSITORY_INFO MorelloFvpRepositoryInfo = { + // ACPI Table List + { + // FADT Table + { + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), + NULL + }, + // GTDT Table + { + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt), + NULL + }, + // MADT Table + { + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), + NULL + }, + // SPCR Table + { + EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr), + NULL + }, + // DSDT Table + { + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)dsdtfvp_aml_code + }, + // DBG2 Table + { + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2), + NULL + }, + // PPTT Table + { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt), + NULL + }, + // IORT Table + { + EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort), + NULL + }, + // PCI MCFG Table + { + EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg), + NULL, + }, + // SSDT table describing the PCI root complex + { + EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpcifvp_aml_code + }, + }, + + // GIC ITS + { + // GIC ITS - PCIe TCU + { + // The GIC ITS ID. + 0, + // The physical address for the Interrupt Translation Service + 0x30060000, + //Proximity Domain + 0 + }, + // GIC ITS - PCIe RC + { + // The GIC ITS ID. + 1, + // The physical address for the Interrupt Translation Service + 0x300A0000, + //Proximity Domain + 0 + }, + }, + + // ITS group node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[0]) + }, + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[1]) + }, + }, + + // ITS identifier array + { + { + // The ITS Identifier + 0 + }, + { + // The ITS Identifier + 1 + }, + }, + + // SMMUv3 Node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Number of ID mappings + 2, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[0][0]), + // SMMU Base Address + 0x4F400000, + // SMMU flags + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, + // VATOS address + 0, + // Model + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, + // GSIV of the Event interrupt if SPI based + 0x10B, + // PRI Interrupt if SPI based + 0, + // GERR interrupt if GSIV based + 0x10D, + // Sync interrupt if GSIV based + 0x10C, + // Proximity domain flag, ignored in this case + 0, + // Index into the array of ID mapping, ignored as SMMU + // control interrupts are GSIV based + 1 + }, + }, + + // Root Complex node info + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (RootComplexInfo[0]), + // Number of ID mappings + 1, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[1][0]), + + // Memory access properties : Cache coherent attributes + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + // Memory access properties : Allocation hints + 0, + // Memory access properties : Memory access flags + 0, + // ATS attributes + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED, + // PCI segment number + 0, + // Memory address size limit + 42 + }, + }, + + // Array of Device ID mappings + { + // DeviceIdMapping[0][0] - [0][1] + { + /* Mapping SMMUv3 -> ITS Group + */ + + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // Flags + 0 + }, + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x00000001, + // Output Base + 0x0, + // Output reference token for the IORT node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // Flags + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, + // DeviceIdMapping[1][0] + { + // Mapping for RootComplex -> SMMUv3 + + // Device ID mapping for Root complex node + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Flags + 0 + }, + }, + }, + // PCI Configuration Space Info + { + // PCIe ECAM + { + FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address + 0x0, // Segment Group Number + FixedPcdGet32 (PcdPciBusMin), // Start Bus Number + FixedPcdGet32 (PcdPciBusMax) // End Bus Number + }, + }, +}; + +EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = { + &CommonPlatformInfo, + &MorelloFvpRepositoryInfo +}; + +/** Return a device Id mapping array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetDeviceIdMappingArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n")); + + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) { + Count = 2; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n")); + } else if (Token == + (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) { + Count = 1; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n")); + } else { + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n")); + return EFI_NOT_FOUND; + } + + CmObject->Data = (VOID*)Token; + CmObject->ObjectId = CmObjectId; + CmObject->Count = Count; + CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING); + + return EFI_SUCCESS; +} + +/** Return an ITS identifier array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetItsIdentifierArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + Count = sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0]); + + for (Index = 0; Index < Count; Index++) { + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]); + CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray[Index]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ITS group info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetItsGroupInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + Count = sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0]); + + for (Index = 0; Index < Count; Index++) { + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]); + CmObject->Data = (VOID*)&PlatformRepo->ItsGroupInfo[Index]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjGicItsInfo, + CmObjectId, + PlatformRepo->GicItsInfo, + (sizeof (PlatformRepo->GicItsInfo) / + sizeof (PlatformRepo->GicItsInfo[0])) + ); + + HANDLE_CM_OBJECT ( + EArmObjSmmuV3, + CmObjectId, + PlatformRepo->SmmuV3Info[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjItsGroup, + CmObjectId, + PlatformRepo->ItsGroupInfo, + (sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0])), + Token, + GetItsGroupInfo + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicItsIdentifierArray, + CmObjectId, + PlatformRepo->ItsIdentifierArray, + (sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0])), + Token, + GetItsIdentifierArray + ); + + HANDLE_CM_OBJECT ( + EArmObjRootComplex, + CmObjectId, + PlatformRepo->RootComplexInfo[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjIdMappingArray, + CmObjectId, + PlatformRepo->DeviceIdMapping, + (sizeof (PlatformRepo->DeviceIdMapping) / + sizeof (PlatformRepo->DeviceIdMapping[0][0])), + Token, + GetDeviceIdMappingArray + ); + + HANDLE_CM_OBJECT ( + EArmObjPciConfigSpaceInfo, + CmObjectId, + PlatformRepo->PciConfigInfo[0], + 1 + ); + default: { + Status = EFI_NOT_FOUND; + break; + } + }//switch + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl new file mode 100644 index 000000000000..f048f81d0646 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl @@ -0,0 +1,114 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2021, ARM Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) { + Scope(_SB) { + Device(CP00) { // Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Name(_STA, 0xF) + } + + Device(CP01) { // Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Name(_STA, 0xF) + } + + Device(CP02) { // Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Name(_STA, 0xF) + } + + Device(CP03) { // Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Name(_STA, 0xF) + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "ARMH0011") + Name(_UID, 0) + + Method(_STA) { + Return(0xF) + } + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x2A400000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } + }) + } + + // VIRTIO DISK + Device(VR00) { + Name(_HID, "LNRO0005") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed( + ReadWrite, + FixedPcdGet32(PcdVirtioBlkBaseAddress), + FixedPcdGet32(PcdVirtioBlkSize) + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { + FixedPcdGet32(PcdVirtioBlkInterrupt) + } + }) + } + + // VIRTIO NET + Device(VR01) { + Name(_HID, "LNRO0005") + Name(_UID, 1) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C180000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 134 } + }) + } + + // VIRTIO RANDOM + Device(VR02) { + Name(_HID, "LNRO0005") + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C190000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 133 } + }) + } + + // VIRTIO P9 Device + Device(VR03) { + Name(_HID, "LNRO0005") + Name(_UID, 3) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C1A0000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 135 } + }) + } + + // SMC91X + Device(NET0) { + Name(_HID, "LNRO0003") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1D100000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 130 } + }) + } + } // Scope(_SB) +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl new file mode 100644 index 000000000000..bdf2f06aed69 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl @@ -0,0 +1,130 @@ +/** @file + Secondary System Description Table (SSDT) + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device(Link_Name) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, Unique_Id) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ +} + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, /* uses the same format as _ADR */ \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \ + Link, /* Interrupt allocated via Link device */ \ + Zero /* global system interrupt number (no used) */ \ +} + +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge. + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO", + CFG_MGR_OEM_REVISION) +{ + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 201) + LNK_DEVICE(2, LNKB, 202) + LNK_DEVICE(3, LNKC, 203) + LNK_DEVICE(4, LNKD, 204) + + // PCI Root Complex + Device(PCI0) { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + 0, // AddressGranularity + FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number + FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + FixedPcdGet32 (PcdPciBusCount) // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address + FixedPcdGet32 (PcdPciMmio32MaxBase), // Max Base Address + FixedPcdGet32 (PcdPciMmio32Translation), // Translate + FixedPcdGet32 (PcdPciMmio32Size) // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address + FixedPcdGet64 (PcdPciMmio64MaxBase), // Max Base Address + FixedPcdGet64 (PcdPciMmio64Translation), // Translate + FixedPcdGet64 (PcdPciMmio64Size) // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciIoBase), // Min Base Address + FixedPcdGet32 (PcdPciIoMaxBase), // Max Base Address + FixedPcdGet32 (PcdPciIoTranslation), // Translate + FixedPcdGet32 (PcdPciIoSize), // Length + , + , + , + TypeTranslation + ) + }) // Name(RBUF) + Return (RBUF) + } // Method (_CRS) + } // Device (PCI0) + } // _SB +} // DB -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager for Morello 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager " Chandni Cherukuri @ 2021-03-01 13:13 ` Sami Mujawar 2021-03-05 23:32 ` Sami Mujawar 0 siblings, 1 reply; 15+ messages in thread From: Sami Mujawar @ 2021-03-01 13:13 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Please find my response inline marked [SAMI]. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri <chandni.cherukuri@arm.com> Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com> Subject: [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager for Morello This patch implements the configuration manager for Morello platform. It enables support for generating the following ACPI tables for Morello FVP Platform: 1. FADT 2. DSDT 3. GTDT 4. MADT 5. SPCR 6. DBG2 7. PPTT 8. IORT 9. MCFG 10. SSDT Structures have been created to add Common Platform information and FVP/Testchip platform specific information so that the same Dxe is usable for all variants of the platform. Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc | 16 + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf | 94 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 304 ++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h | 81 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h | 91 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 1005 ++++++++++++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c | 531 +++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl | 114 +++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl | 130 +++ 9 files changed, 2366 insertions(+) diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc new file mode 100644 index 000000000000..71916783c24c --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc @@ -0,0 +1,16 @@ +## @file +# dsc include file for Configuration Manager +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + +[BuildOptions] + +[Components.common] + # Configuration Manager + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf new file mode 100644 index 000000000000..9137de2dd118 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf @@ -0,0 +1,94 @@ +## @file +# Configuration Manager Dxe +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ConfigurationManagerDxe + FILE_GUID = 6F9C3B47-6F7D-44B6-87E5-4B7F44A60147 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ConfigurationManagerDxeInitialize + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + AslTables/DsdtFvp.asl + AslTables/SsdtPciFvp.asl + ConfigurationManagerFvp.c + ConfigurationManager.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + DynamicTablesPkg/DynamicTablesPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Protocols] + gEdkiiConfigurationManagerProtocolGuid + +[FixedPcd] + ## PL011 Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + # SBSA Generic Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt + + # PCI + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciBusCount + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress [SAMI] Reorder based on alphabetical order. Also remove following Pcd section if not needed. [/SAMI] +[Pcd] + +[Depex] + TRUE diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h new file mode 100644 index 000000000000..b44270639001 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h @@ -0,0 +1,304 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef CONFIGURATION_MANAGER_H__ +#define CONFIGURATION_MANAGER_H__ + +/** The configuration manager version. +*/ +#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0) + +/** The OEM ID +*/ +#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' } +#define CFG_MGR_OEM_REVISION 0x20181101 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&CommonPlatformInfo + \ + OFFSET_OF (EDKII_COMMON_PLATFORM_REPOSITORY_INFO, Field)) + +/** A helper macro that constructs the MPID based on the + Aff0, Aff1, Aff2, Aff3 values +*/ +#define GET_MPID3(Aff3, Aff2, Aff1, Aff0) \ + (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0)) + +/** A helper macro for populating the GIC CPU information +*/ +#define GICC_ENTRY( \ + CPUInterfaceNumber, \ + Mpidr, \ + PmuIrq, \ + VGicIrq, \ + GicRedistBase, \ + EnergyEfficiency, \ + SpeIrq, \ + ProximityDomain, \ + ClockDomain \ + ) { \ + CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \ + CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \ + EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ + PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \ + 0, /* UINT64 ParkedAddress */ \ + FixedPcdGet64 ( \ + PcdGicInterruptInterfaceBase \ + ), /* UINT64 PhysicalBaseAddress */ \ + 0, /* UINT64 GICV */ \ + 0, /* UINT64 GICH */ \ + VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \ + GicRedistBase, /* UINT64 GICRBaseAddress */ \ + Mpidr, /* UINT64 MPIDR */ \ + EnergyEfficiency, /* UINT8 ProcessorPowerEfficiencyClass*/ \ + SpeIrq, /* UINT16 SpeOverflowInterrupt */ \ + ProximityDomain, /* UINT32 ProximityDomain */ \ + ClockDomain, /* UINT32 ClockDomain */ \ + EFI_ACPI_6_3_GICC_ENABLED,/* UINT32 Flags */ \ + } + +/** A helper macro for populating the Processor Hierarchy Node flags +*/ +#define PROC_NODE_FLAGS( \ + PhysicalPackage, \ + AcpiProcessorIdValid, \ + ProcessorIsThread, \ + NodeIsLeaf, \ + IdenticalImplementation \ + ) \ + ( \ + PhysicalPackage | \ + (AcpiProcessorIdValid << 1) | \ + (ProcessorIsThread << 2) | \ + (NodeIsLeaf << 3) | \ + (IdenticalImplementation << 4) \ + ) + +/** A helper macro for populating the Cache Type Structure's attributes +*/ +#define CACHE_ATTRIBUTES( \ + AllocationType, \ + CacheType, \ + WritePolicy \ + ) \ + ( \ + AllocationType | \ + (CacheType << 2) | \ + (WritePolicy << 4) \ + ) + +/** A helper macro for returning configuration manager objects +*/ +#define HANDLE_CM_OBJECT(ObjId, CmObjectId, Object, ObjectCount) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + CmObject->Size = sizeof (Object); \ + CmObject->Data = (VOID*)&Object; \ + CmObject->Count = ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr = 0x%p, Size = %d, Count = %d\n", \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + break; \ + } + +/** A helper macro for returning configuration manager objects + referenced by token +*/ +#define HANDLE_CM_OBJECT_REF_BY_TOKEN( \ + ObjId, \ + CmObjectId, \ + Object, \ + ObjectCount, \ + Token, \ + HandlerProc \ + ) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + if (Token == CM_NULL_TOKEN) { \ + CmObject->Size = sizeof (Object); \ + CmObject->Data = (VOID*)&Object; \ + CmObject->Count = ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr = 0x%p, Size = %d, Count = %d\n", \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } else { \ + Status = HandlerProc (This, CmObjectId, Token, CmObject); \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Token = 0x%p, Ptr = 0x%p, Size = %d, Count = %d\n", \ + (VOID*)Token, \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } \ + break; \ + } + +/** A helper macro for returning configuration manager objects referenced + by token when the entire platform repository is in scope and the + CM_NULL_TOKEN value is not allowed. +*/ +#define HANDLE_CM_OBJECT_SEARCH_PLAT_REPO( \ + ObjId, \ + CmObjectId, \ + Token, \ + HandlerProc \ + ) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + if (Token == CM_NULL_TOKEN) { \ + Status = EFI_INVALID_PARAMETER; \ + DEBUG (( \ + DEBUG_ERROR, \ + #ObjId ": CM_NULL_TOKEN value is not allowed when searching" \ + " the entire platform repository.\n" \ + )); \ + } else { \ + Status = HandlerProc (This, CmObjectId, Token, CmObject); \ + DEBUG (( \ + DEBUG_INFO, \ + #ObjId ": Token = 0x%p, Ptr = 0x%p, Size = %d, Count = %d\n", \ + (VOID*)Token, \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } \ + break; \ + } [SAMI] EDKII coding standard discourages the use of functional macros. See See https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/55_preprocessor_directives#5-5-2-1-functional-macros-are-generally-discouraged Can you change this to use functions, please? You can refer to a recent change that has been done for Juno at https://github.com/tianocore/edk2-platforms/commit/b4d9dd5db30222880a32d2d4f69e25f186848f22#diff-96a7068366e9a005b9cebcf6f79b9f8bd5ea7d9888b586af601cac90d3e1956e [/SAMI] + +/** The number of CPUs +*/ +#define PLAT_CPU_COUNT 4 + +/** The number of platform generic timer blocks +*/ +#define PLAT_GTBLOCK_COUNT 1 + +/** The number of timer frames per generic timer block +*/ +#define PLAT_GTFRAME_COUNT 2 + +/** The number of Processor Hierarchy Nodes + - one package node + - two cluster nodes + - two cores in cluster 0 + - two cores in cluster 1 +*/ +#define PLAT_PROC_HIERARCHY_NODE_COUNT 7 + +/** The number of unique cache structures: + - cluster L3 unified cache + - core L1 instruction cache + - core L1 data cache + - core L2 cache + - slc unified cache +*/ +#define PLAT_CACHE_COUNT 5 + +/** The number of resources private to the cluster + - L3 cache +*/ +#define CLUSTER_RESOURCE_COUNT 1 + +/** The number of resources private to 'core instance + - L1 data cache + - L1 instruction cache + - L2 cache +*/ +#define CORE_RESOURCE_COUNT 3 + +/** The number of resources private to SoC + - slc cache + - Proc Node Id Info +*/ +#define SOC_RESOURCE_COUNT 2 + +/** A structure describing the platform configuration + manager repository information +*/ +typedef struct CommonPlatformRepositoryInfo { + /// Configuration Manager Information + CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo; + + /// Boot architecture information + CM_ARM_BOOT_ARCH_INFO BootArchInfo; + +#ifdef HEADLESS_PLATFORM + /// Fixed feature flag information + CM_ARM_FIXED_FEATURE_FLAGS FixedFeatureFlags; +#endif + + /// Power management profile information + CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo; + + /// GIC CPU interface information + CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT]; + + /// GIC distributor information + CM_ARM_GICD_INFO GicDInfo; + + /// GIC Redistributor information + CM_ARM_GIC_REDIST_INFO GicRedistInfo; + + /// Generic timer information + CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo; + + /// Generic timer block information + CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT]; + + /// Generic timer frame information + CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COUNT]; + + /// Watchdog information + CM_ARM_GENERIC_WATCHDOG_INFO Watchdog; + + /** Serial port information for the + serial port console redirection port + */ + CM_ARM_SERIAL_PORT_INFO SpcrSerialPort; + + /// Serial port information for the DBG2 UART port + CM_ARM_SERIAL_PORT_INFO DbgSerialPort; + + // Processor topology information + CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT]; + + // Processor Node Id Info + CM_ARM_PROC_NODE_ID_INFO ProcNodeIdInfo; + + + // Cache information + CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT]; + + // Cluster private resources + CM_ARM_OBJ_REF ClusterResources[CLUSTER_RESOURCE_COUNT]; + + // Core private resources + CM_ARM_OBJ_REF CoreResources[CORE_RESOURCE_COUNT]; + + // SoC Resources + CM_ARM_OBJ_REF SocResources[SOC_RESOURCE_COUNT]; + +} EDKII_COMMON_PLATFORM_REPOSITORY_INFO; + +#endif // CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h new file mode 100644 index 000000000000..be0f02fab1ce --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h @@ -0,0 +1,81 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef FVP_CONFIGURATION_MANAGER_H__ +#define FVP_CONFIGURATION_MANAGER_H__ + +#include "ConfigurationManager.h" + +/** The number of ACPI tables to install +*/ +#define PLAT_ACPI_TABLE_COUNT 10 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN_FVP(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&MorelloFvpRepositoryInfo + \ + OFFSET_OF (EDKII_FVP_PLATFORM_REPOSITORY_INFO, Field)) + +/** C array containing the compiled AML template. + These symbols are defined in the auto generated C file + containing the AML bytecode array. +*/ +extern CHAR8 dsdtfvp_aml_code[]; +extern CHAR8 ssdtpcifvp_aml_code[]; + +//Add FVP Platform specific information +typedef struct FvpPlatformRepositoryInfo { + /// List of ACPI tables + CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT]; + + /// GIC ITS information + CM_ARM_GIC_ITS_INFO GicItsInfo[2]; + + /// ITS Group node + CM_ARM_ITS_GROUP_NODE ItsGroupInfo[2]; + + /// ITS Identifier array + CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[2]; + + /// SMMUv3 node + CM_ARM_SMMUV3_NODE SmmuV3Info[1]; + + /// PCI Root complex node + CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[1]; + + /// Array of DeviceID mapping + CM_ARM_ID_MAPPING DeviceIdMapping[2][2]; + + /// PCI configuration space information + CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[1]; + +} EDKII_FVP_PLATFORM_REPOSITORY_INFO; + +typedef struct PlatformRepositoryInfo { + + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepoInfo; + + EDKII_FVP_PLATFORM_REPOSITORY_INFO * FvpPlatRepoInfo; + +} EDKII_PLATFORM_REPOSITORY_INFO; [SAMI] Doxygen documentation, please. [/SAMI] + +extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo; + +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ); + +#endif // FVP_CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h new file mode 100644 index 000000000000..2e5286e892df --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PLATFORM_H__ +#define PLATFORM_H__ + +#define ENABLE_MEM_MAPPED_TIMER + +#ifdef ENABLE_MEM_MAPPED_TIMER +// REFCLK CNTControl +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0x2A430000 +// REFCLK CNTRead +#define MORELLO_CNT_READ_BASE_ADDRESS 0x2A800000 +#else +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#define MORELLO_CNT_READ_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +// GT Block Timer +// AP_REFCLK CNTCTL +#define MORELLO_GT_BLOCK_CTL_BASE 0x2A810000 +#define MORELLO_TIMER_FRAMES_COUNT 2 + +// GT Block Timer Frames +// AP_REFCLK_NS CNTBase0 +#define MORELLO_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000 +#define MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME0_GSIV 92 + +// AP_REFCLK_S CNTBase1 +#define MORELLO_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000 +#define MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME1_GSIV 91 + +#define GTDT_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | \ + GTDT_TIMER_ACTIVE_LOW | \ + GTDT_TIMER_LEVEL_TRIGGERED) + +// GT Block Timer Flags +#define GTX_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define MORELLO_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | \ + GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_SECURE) +#define MORELLO_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_NON_SECURE) + +// Watchdog +#define SBSA_WATCHDOG_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define MORELLO_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | \ + SBSA_WATCHDOG_ACTIVE_HIGH | \ + SBSA_WATCHDOG_LEVEL_TRIGGERED) + +#endif // PLATFORM_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c new file mode 100644 index 000000000000..e324cc50853f --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c @@ -0,0 +1,1005 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include <IndustryStandard/DebugPort2Table.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/ConfigurationManagerProtocol.h> + +#include "ConfigurationManagerFvp.h" +#include "ConfigurationManager.h" +#include "Platform.h" + +extern EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo; + +// The platform configuration repository information. +EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo = { + // Configuration Manager information + { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID }, + + // Boot architecture information + { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags + +#ifdef HEADLESS_PLATFORM + // Fixed feature flag information + { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags +#endif + + // Power management profile information + { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile + + /* GIC CPU Interface information + GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase, + EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain) + */ + { + GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + }, + + // GIC Distributor Info + { + FixedPcdGet64 (PcdGicDistributorBase), // UINT64 PhysicalBaseAddress + 0, // UINT32 SystemVectorBase + 3 // UINT8 GicVersion + }, + + // GIC Re-Distributor Info + { + // UINT64 DiscoveryRangeBaseAddress + FixedPcdGet64 (PcdGicRedistributorsBase), + // UINT32 DiscoveryRangeLength + SIZE_1MB + }, + + // Generic Timer Info + { + // The physical base address for the counter control frame + MORELLO_SYSTEM_TIMER_BASE_ADDRESS, + // The physical base address for the counter read frame + MORELLO_CNT_READ_BASE_ADDRESS, + // The secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), + // The secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerIntrNum), + // The non-secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The virtual timer interrupt + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), + // The virtual timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL2 timer interrupt + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), + // The non-secure PL2 timer flags + MORELLO_GTDT_GTIMER_FLAGS + }, + + // Generic Timer Block Information + { + { + // The physical base address for the GT Block Timer structure + MORELLO_GT_BLOCK_CTL_BASE, + // The number of timer frames implemented in the GT Block + MORELLO_TIMER_FRAMES_COUNT, + // Reference token for the GT Block timer frame list + REFERENCE_TOKEN (GTBlock0TimerInfo) + } + }, + + // GT Block Timer Frames + { + // Frame 0 + { + 0, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 PhysicalAddressCntBase + MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base + MORELLO_GT_BLOCK_FRAME0_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_NS // UINT32 CommonFlags + }, + // Frame 1 + { + 1, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 PhysicalAddressCntBase + MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base + MORELLO_GT_BLOCK_FRAME1_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_S // UINT32 CommonFlags + }, + }, + + // Watchdog Info + { + // The physical base address of the SBSA Watchdog control frame + FixedPcdGet64 (PcdGenericWatchdogControlBase), + // The physical base address of the SBSA Watchdog refresh frame + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), + // The watchdog interrupt + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + // The watchdog flags + MORELLO_SBSA_WATCHDOG_FLAGS + }, + + // SPCR Serial Port + { + FixedPcdGet64 (PcdSerialRegisterBase), // BaseAddress + FixedPcdGet32 (PL011UartInterrupt), // Interrupt + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet32 (PL011UartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Debug Serial Port + { + FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress + 0, // Interrupt -unused + FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate + FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Processor Hierarchy Nodes + { + // Package + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[0]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + CM_NULL_TOKEN, + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + SOC_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (SocResources) + }, + + // Cluster0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[1]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[2]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster0 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[0]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster0 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[1]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster1 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[2]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + + // Cluster1 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[3]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + }, + + // Processor Node Id Info + { + // A unique token used to identify this object + REFERENCE_TOKEN (ProcNodeIdInfo), + // Vendor ID (as described in ACPI ID registry) + SIGNATURE_32('A', 'R', 'M', 'H'), + // First level unique node ID + 0, + // Second level unique node ID + 0, + // Major revision of the node + 0, + // Minor revision of the node + 0, + // Spin revision of the node + 0 + }, + + // Cache information + { + // 'cluster's L3 cache + { + REFERENCE_TOKEN (CacheInfo[0]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 instruction cache + { + REFERENCE_TOKEN (CacheInfo[1]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 data cache + { + REFERENCE_TOKEN (CacheInfo[2]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // cores's L2 cache + { + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // slc cache + { + REFERENCE_TOKEN (CacheInfo[4]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_8MB, // UINT32 Size + 4096, // UINT32 NumberOfSets + 16, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + }, + // Resources private to the 'cluster (shared among cores) in Cluster + { + { REFERENCE_TOKEN (CacheInfo[0]) } // -> 'cluster's L3 cache in Cluster + }, + // Resources private to each individual 'core instance in Cluster + { + { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[2]) }, // -> 'core's L1 D-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[3]) } // -> 'core's L2 cache in Cluster + }, + + // Resources private to the SoC + { + { REFERENCE_TOKEN (CacheInfo[4]) }, // -> slc for SoC + { REFERENCE_TOKEN (ProcNodeIdInfo) }, // -> ProcNodeIdInfo for SoC + }, +}; + +/** Initialize the Platform Configuration Repository. + + @param [in] This Pointer to the Platform Configuration Repository. + + @retval + EFI_SUCCESS Success +**/ +STATIC +EFI_STATUS +EFIAPI +InitializePlatformRepository ( + IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatformRepo + ) +{ + return EFI_SUCCESS; +} + +/** Return a GT Block timer frame info list. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetGTBlockTimerFrameInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo; + + if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) { + return EFI_NOT_FOUND; + } + + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->GTBlock0TimerInfo); + CmObject->Data = (VOID*)&PlatformRepo->GTBlock0TimerInfo; + CmObject->Count = sizeof (PlatformRepo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->GTBlock0TimerInfo[0]); [SAMI] ARRAY_SIZE () ? [/SAMI] + return EFI_SUCCESS; +} + +/** Return GIC CPU Interface Info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the requested + CM_ARM_GICC_INFO object. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetGicCInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 TotalObjCount; + UINT32 ObjIndex; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo; + TotalObjCount = PLAT_CPU_COUNT; [SAMI] Is TotalObjCount variable needed ? [/SAMI] + + for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) { + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjIndex]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->GicCInfo[ObjIndex]); + CmObject->Data = (VOID*)&PlatformRepo->GicCInfo[ObjIndex]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return a list of Configuration Manager object references pointed to by the + given input token. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the requested + CM_ARM_OBJ_REF list. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetCmObjRefs ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo; + + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->ClusterResources) { [SAMI] It would be better to have a local variable for PlatformRepo->CommonPlatRepoInfo instead of PlatformRepo. [/SAMI] + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->ClusterResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->ClusterResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->ClusterResources); + return EFI_SUCCESS; + } + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->CoreResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->CoreResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->CoreResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CoreResources); + return EFI_SUCCESS; + } + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->SocResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->SocResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->SocResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->SocResources); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** Return a standard namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetStandardNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EStdObjCfgMgrInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CmInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EStdObjAcpiTableList, + CmObjectId, + PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList, + (sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList) / + sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList[0])) [SAMI] ARRAY_SIZE () ? [/SAMI] + ); + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 GicRedistCount; + UINT32 GicCpuCount; + UINT32 ProcHierarchyInfoCount; [SAMI] Are these local variables needed? If not, can these be removed, and the values/macros used at the right places instead? [/SAMI] + + Status = EFI_SUCCESS; [SAMI] It is safer to start with EFI_NOT_FOUND. Also, this could be moved along with the PlatformRepo initialisation below. [/SAMI] + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo; + + GicRedistCount = 1; + GicCpuCount = PLAT_CPU_COUNT; + ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT; + + Status = GetArmNameSpaceObjectPlat (This, CmObjectId, Token, CmObject); [SAMI] Add a comment describing why this is done. [/SAMI] + + if (Status == EFI_NOT_FOUND) { + + Status = EFI_SUCCESS; [SAMI] Is this needed? + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjBootArchInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->BootArchInfo, + 1 + ); + +#ifdef HEADLESS_PLATFORM + HANDLE_CM_OBJECT ( + EArmObjFixedFeatureFlags, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->FixedFeatureFlags, + 1 + ); +#endif + HANDLE_CM_OBJECT ( + EArmObjPowerManagementProfileInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->PmProfileInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGenericTimerInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GenericTimerInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGenericWatchdogInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->Watchdog, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGTBlockInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlockInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo[0])) + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGTBlockTimerFrameInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo[0])), + Token, + GetGTBlockTimerFrameInfo + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicCInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicCInfo, + GicCpuCount, + Token, + GetGicCInfo + ); + HANDLE_CM_OBJECT ( + EArmObjGicDInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicDInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGicRedistributorInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicRedistInfo, + GicRedistCount + ); + HANDLE_CM_OBJECT ( + EArmObjSerialConsolePortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->SpcrSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjSerialDebugPortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->DbgSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjProcHierarchyInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcHierarchyInfo, + ProcHierarchyInfoCount + ); + HANDLE_CM_OBJECT ( + EArmObjProcNodeIdInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcNodeIdInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjCacheInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CacheInfo, + ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CacheInfo) + ); + HANDLE_CM_OBJECT_SEARCH_PLAT_REPO ( + EArmObjCmRef, + CmObjectId, + Token, + GetCmObjRefs + ); + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_INFO, + "INFO: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + }//switch + } + return Status; +} + +/** Return an OEM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetOemNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The GetObject function defines the interface implemented by the + Configuration Manager Protocol for returning the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformGetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_NAMESPACE_ID (CmObjectId)) { + case EObjNameSpaceStandard: + Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceArm: + Status = GetArmNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceOem: + Status = GetOemNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + default: { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The SetObject function defines the interface implemented by the + Configuration Manager Protocol for updating the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in] CmObject Pointer to the Configuration Manager Object + descriptor describing the Object. + + @retval EFI_UNSUPPORTED This operation is not supported. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformSetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + return EFI_UNSUPPORTED; +} + +/** A structure describing the configuration manager protocol interface. +*/ +STATIC +CONST +EDKII_CONFIGURATION_MANAGER_PROTOCOL MorelloPlatformConfigManagerProtocol = { + CREATE_REVISION(1,0), + MorelloPlatformGetObject, + MorelloPlatformSetObject, + &MorelloRepositoryInfo +}; + +/** + Entrypoint of Configuration Manager Dxe. + + @param ImageHandle + @param SystemTable + + @return EFI_SUCCESS + @return EFI_LOAD_ERROR + @return EFI_OUT_OF_RESOURCES + +**/ +EFI_STATUS +EFIAPI +ConfigurationManagerDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE * SystemTable + ) +{ + EFI_STATUS Status; + + // Initialize the Platform Configuration Repository before installing the + // Configuration Manager Protocol + Status = InitializePlatformRepository ( + MorelloPlatformConfigManagerProtocol.PlatRepoInfo + ); [SAMI] Align according to coding standard. [/SAMI] + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to initialize the Platform Configuration Repository." \ + " Status = %r\n", + Status + )); + } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gEdkiiConfigurationManagerProtocolGuid, + EFI_NATIVE_INTERFACE, + (VOID*)&MorelloPlatformConfigManagerProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to get Install Configuration Manager Protocol." \ + " Status = %r\n", + Status + )); + goto error_handler; + } + +error_handler: + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c new file mode 100644 index 000000000000..b50a9db220a2 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c @@ -0,0 +1,531 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include <IndustryStandard/DebugPort2Table.h> +#include <IndustryStandard/IoRemappingTable.h> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/ConfigurationManagerProtocol.h> + +#include "ConfigurationManagerFvp.h" +#include "Platform.h" + +EDKII_FVP_PLATFORM_REPOSITORY_INFO MorelloFvpRepositoryInfo = { + // ACPI Table List + { + // FADT Table + { + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), + NULL + }, + // GTDT Table + { + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt), + NULL + }, + // MADT Table + { + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), + NULL + }, + // SPCR Table + { + EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr), + NULL + }, + // DSDT Table + { + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)dsdtfvp_aml_code + }, + // DBG2 Table + { + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2), + NULL + }, + // PPTT Table + { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt), + NULL + }, + // IORT Table + { + EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort), + NULL + }, + // PCI MCFG Table + { + EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg), + NULL, + }, + // SSDT table describing the PCI root complex + { + EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpcifvp_aml_code + }, + }, + + // GIC ITS + { + // GIC ITS - PCIe TCU + { + // The GIC ITS ID. + 0, + // The physical address for the Interrupt Translation Service + 0x30060000, + //Proximity Domain + 0 + }, + // GIC ITS - PCIe RC + { + // The GIC ITS ID. + 1, + // The physical address for the Interrupt Translation Service + 0x300A0000, + //Proximity Domain + 0 + }, + }, + + // ITS group node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[0]) + }, + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[1]) + }, + }, + + // ITS identifier array + { + { + // The ITS Identifier + 0 + }, + { + // The ITS Identifier + 1 + }, + }, + + // SMMUv3 Node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Number of ID mappings + 2, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[0][0]), + // SMMU Base Address + 0x4F400000, + // SMMU flags + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, + // VATOS address + 0, + // Model + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, + // GSIV of the Event interrupt if SPI based + 0x10B, + // PRI Interrupt if SPI based + 0, + // GERR interrupt if GSIV based + 0x10D, + // Sync interrupt if GSIV based + 0x10C, + // Proximity domain flag, ignored in this case + 0, + // Index into the array of ID mapping, ignored as SMMU + // control interrupts are GSIV based + 1 + }, + }, + + // Root Complex node info + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (RootComplexInfo[0]), + // Number of ID mappings + 1, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[1][0]), + + // Memory access properties : Cache coherent attributes + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + // Memory access properties : Allocation hints + 0, + // Memory access properties : Memory access flags + 0, + // ATS attributes + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED, + // PCI segment number + 0, + // Memory address size limit + 42 + }, + }, + + // Array of Device ID mappings + { + // DeviceIdMapping[0][0] - [0][1] + { + /* Mapping SMMUv3 -> ITS Group + */ + + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // Flags + 0 + }, + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x00000001, + // Output Base + 0x0, + // Output reference token for the IORT node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // Flags + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, + // DeviceIdMapping[1][0] + { + // Mapping for RootComplex -> SMMUv3 + + // Device ID mapping for Root complex node + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Flags + 0 + }, + }, + }, + // PCI Configuration Space Info + { + // PCIe ECAM + { + FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address + 0x0, // Segment Group Number + FixedPcdGet32 (PcdPciBusMin), // Start Bus Number + FixedPcdGet32 (PcdPciBusMax) // End Bus Number + }, + }, +}; + +EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = { + &CommonPlatformInfo, + &MorelloFvpRepositoryInfo +}; + +/** Return a device Id mapping array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetDeviceIdMappingArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n")); + + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) { + Count = 2; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n")); + } else if (Token == + (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) { + Count = 1; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n")); + } else { + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n")); + return EFI_NOT_FOUND; + } + + CmObject->Data = (VOID*)Token; + CmObject->ObjectId = CmObjectId; + CmObject->Count = Count; + CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING); + + return EFI_SUCCESS; +} + +/** Return an ITS identifier array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetItsIdentifierArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + Count = sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0]); [SAMI] ARRAY_SIZE () ?. Same at other places in this patch series. [/SAMI] + + for (Index = 0; Index < Count; Index++) { + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]); + CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray[Index]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ITS group info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetItsGroupInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + Count = sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0]); + + for (Index = 0; Index < Count; Index++) { + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]); + CmObject->Data = (VOID*)&PlatformRepo->ItsGroupInfo[Index]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status = EFI_SUCCESS; [SAMI] It is better to set this to EFI_NOT_FOUND. Also move it with PlatformRepo initialisation below. + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjGicItsInfo, + CmObjectId, + PlatformRepo->GicItsInfo, + (sizeof (PlatformRepo->GicItsInfo) / + sizeof (PlatformRepo->GicItsInfo[0])) + ); + + HANDLE_CM_OBJECT ( + EArmObjSmmuV3, + CmObjectId, + PlatformRepo->SmmuV3Info[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjItsGroup, + CmObjectId, + PlatformRepo->ItsGroupInfo, + (sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0])), + Token, + GetItsGroupInfo + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicItsIdentifierArray, + CmObjectId, + PlatformRepo->ItsIdentifierArray, + (sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0])), + Token, + GetItsIdentifierArray + ); + + HANDLE_CM_OBJECT ( + EArmObjRootComplex, + CmObjectId, + PlatformRepo->RootComplexInfo[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjIdMappingArray, + CmObjectId, + PlatformRepo->DeviceIdMapping, + (sizeof (PlatformRepo->DeviceIdMapping) / + sizeof (PlatformRepo->DeviceIdMapping[0][0])), + Token, + GetDeviceIdMappingArray + ); + + HANDLE_CM_OBJECT ( + EArmObjPciConfigSpaceInfo, + CmObjectId, + PlatformRepo->PciConfigInfo[0], + 1 + ); + default: { + Status = EFI_NOT_FOUND; + break; + } + }//switch + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl new file mode 100644 index 000000000000..f048f81d0646 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl @@ -0,0 +1,114 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2021, ARM Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) { + Scope(_SB) { + Device(CP00) { // Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Name(_STA, 0xF) + } + + Device(CP01) { // Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Name(_STA, 0xF) + } + + Device(CP02) { // Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Name(_STA, 0xF) + } + + Device(CP03) { // Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Name(_STA, 0xF) + } + + // UART PL011 + Device(COM0) { [SAMI] This is automatically defined in an SSDT by the DynamicTables Framework if a DBG2/SPCR table is included. Use Acpiview to dump the SSDT tables and check. So, this COM0 device definition must be removed. Also look at my comment in MorelloPlatform.dsc.inc for PcdSerialDbgRegisterBase. [/SAMI] + Name(_HID, "ARMH0011") + Name(_CID, "ARMH0011") + Name(_UID, 0) + + Method(_STA) { + Return(0xF) + } + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x2A400000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } + }) + } + + // VIRTIO DISK + Device(VR00) { + Name(_HID, "LNRO0005") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed( + ReadWrite, + FixedPcdGet32(PcdVirtioBlkBaseAddress), + FixedPcdGet32(PcdVirtioBlkSize) + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { + FixedPcdGet32(PcdVirtioBlkInterrupt) + } + }) + } + + // VIRTIO NET + Device(VR01) { [SAMI] Is initialisation of VIRTIO Network device not required in Drivers\PlatformDxe\VirtioDevices.c ? [/SAMI] + Name(_HID, "LNRO0005") + Name(_UID, 1) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C180000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 134 } + }) + } + + // VIRTIO RANDOM + Device(VR02) { + Name(_HID, "LNRO0005") + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C190000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 133 } + }) + } + + // VIRTIO P9 Device + Device(VR03) { + Name(_HID, "LNRO0005") + Name(_UID, 3) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C1A0000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 135 } + }) + } + + // SMC91X + Device(NET0) { + Name(_HID, "LNRO0003") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1D100000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 130 } + }) + } + } // Scope(_SB) +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl new file mode 100644 index 000000000000..bdf2f06aed69 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl @@ -0,0 +1,130 @@ +/** @file + Secondary System Description Table (SSDT) + + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device(Link_Name) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, Unique_Id) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ +} + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, /* uses the same format as _ADR */ \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \ + Link, /* Interrupt allocated via Link device */ \ + Zero /* global system interrupt number (no used) */ \ +} + +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge. + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO", + CFG_MGR_OEM_REVISION) +{ + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 201) + LNK_DEVICE(2, LNKB, 202) + LNK_DEVICE(3, LNKC, 203) + LNK_DEVICE(4, LNKD, 204) + + // PCI Root Complex + Device(PCI0) { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + 0, // AddressGranularity + FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number + FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + FixedPcdGet32 (PcdPciBusCount) // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address + FixedPcdGet32 (PcdPciMmio32MaxBase), // Max Base Address + FixedPcdGet32 (PcdPciMmio32Translation), // Translate + FixedPcdGet32 (PcdPciMmio32Size) // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address + FixedPcdGet64 (PcdPciMmio64MaxBase), // Max Base Address + FixedPcdGet64 (PcdPciMmio64Translation), // Translate + FixedPcdGet64 (PcdPciMmio64Size) // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciIoBase), // Min Base Address + FixedPcdGet32 (PcdPciIoMaxBase), // Max Base Address + FixedPcdGet32 (PcdPciIoTranslation), // Translate + FixedPcdGet32 (PcdPciIoSize), // Length + , + , + , + TypeTranslation + ) + }) // Name(RBUF) + Return (RBUF) + } // Method (_CRS) + } // Device (PCI0) + } // _SB +} // DB -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager for Morello 2021-03-01 13:13 ` Sami Mujawar @ 2021-03-05 23:32 ` Sami Mujawar 0 siblings, 0 replies; 15+ messages in thread From: Sami Mujawar @ 2021-03-05 23:32 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Just remembered one more thing. + // Processor Node Id Info + { + // A unique token used to identify this object + REFERENCE_TOKEN (ProcNodeIdInfo), + // Vendor ID (as described in ACPI ID registry) + SIGNATURE_32('A', 'R', 'M', 'H'), + // First level unique node ID + 0, + // Second level unique node ID + 0, + // Major revision of the node + 0, + // Minor revision of the node + 0, + // Spin revision of the node + 0 + }, The 'PPTT Type 2 - Processor ID' is deprecated so don’t add this information. Regards, Sami Mujawar ^ permalink raw reply [flat|nested] 15+ messages in thread
* [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri ` (3 preceding siblings ...) 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager " Chandni Cherukuri @ 2021-02-24 13:12 ` Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-03-01 13:13 ` [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Sami Mujawar 5 siblings, 1 reply; 15+ messages in thread From: Chandni Cherukuri @ 2021-02-24 13:12 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar From: Anurag Koul <anurag.koul@arm.com> This patch adds the initial support for Morello FVP platform. Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/MorelloPlatform.dec | 59 ++++ Platform/ARM/Morello/MorelloPlatform.dsc.inc | 235 +++++++++++++++ Platform/ARM/Morello/MorelloPlatformFvp.dsc | 60 ++++ Platform/ARM/Morello/MorelloPlatformFvp.fdf | 302 ++++++++++++++++++++ 4 files changed, 656 insertions(+) diff --git a/Platform/ARM/Morello/MorelloPlatform.dec b/Platform/ARM/Morello/MorelloPlatform.dec new file mode 100644 index 000000000000..5bf9f5f12005 --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dec @@ -0,0 +1,59 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = Morello + PACKAGE_GUID = F09A2C11-7864-4B1D-869E-03EE2AD79288 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmMorelloTokenSpaceGuid = { 0x0A8C3A78, 0xA56F, 0x4788, { 0x83, 0xB4, 0xCD, 0x29, 0x62, 0x96, 0x77, 0x51 } } + +[PcdsFixedAtBuild] + # Ramdisk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000003 + + # Virtio Block device + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00000004 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|0x00000000|UINT32|0x00000006 + + # PCIe + gArmMorelloTokenSpaceGuid.PcdPciBusMin|0|UINT32|0x00000009 + gArmMorelloTokenSpaceGuid.PcdPciBusMax|15|UINT32|0x0000000A + gArmMorelloTokenSpaceGuid.PcdPciBusCount|16|UINT32|0x0000000B + gArmMorelloTokenSpaceGuid.PcdPciIoBase|0x0|UINT32|0x0000000C + gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00800000|UINT32|0x0000000D + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x007FFFFF|UINT32|0x0000000E + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x67800000|UINT32|0x0000000F + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base|0x60000000|UINT32|0x00000010 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x07800000|UINT32|0x00000011 + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x677FFFFF|UINT32|0x00000012 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT32|0x00000013 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base|0x900000000|UINT64|0x00000014 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000|UINT64|0x00000015 + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000016 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017 + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x00000018 + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008 diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc b/Platform/ARM/Morello/MorelloPlatform.dsc.inc new file mode 100644 index 000000000000..0715d5e24a6b --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc @@ -0,0 +1,235 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf + BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # Ramdisk Support + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + +[LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + +[LibraryClasses.common.PEI_CORE] + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.common.DXE_DRIVER] + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 + + # System Memory (2GB - 16MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0x8080000000 + + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 + + # PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|50000000 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C100000 + + # ARM Architectural Timer Frequency + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # ACPI Table Version + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + + # Runtime Variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # RAM Disk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000 + + # PCIe + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # PEI Phase modules + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # DXE + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + } + + # Architectural Protocols + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + + # ACPI Support + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # Bds + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # RAM Disk + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # Required by PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + + # AHCI Support + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc b/Platform/ARM/Morello/MorelloPlatformFvp.dsc new file mode 100644 index 000000000000..04a966c33f8d --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = morellofvp + PLATFORM_GUID = CB995FFD-EAEF-4d5E-8A4B-3213B39CD14A + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) +!endif + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/Morello/MorelloPlatformFvp.fdf + BUILD_NUMBER = 1 + + # Network definition + DEFINE NETWORK_ISCSI_ENABLE = FALSE + +!include Platform/ARM/Morello/MorelloPlatform.dsc.inc +!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +!include DynamicTablesPkg/DynamicTables.dsc.inc +!include Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc + +[LibraryClasses.common] + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PciHostBridgeLib|Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|TRUE + +[PcdsFixedAtBuild.common] + # Virtio Disk + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1C170000 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x200 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|128 + +[Components.common] + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # Platform driver + Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.fdf b/Platform/ARM/Morello/MorelloPlatformFvp.fdf new file mode 100644 index 000000000000..29e7e099cc7b --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.fdf @@ -0,0 +1,302 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_AP_UEFI] +BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x200 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of +# different images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) +# followed by the pipe "|" character, followed by the size of the region, also +# in hex with the leading "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a +# flash device file. This section also defines order the components and modules +# are positioned within the image. The [FV] section consists of define +# statements, set statements and module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # ACPI Support + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # Configuration Manager + INF Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf + + # Dynamic Table fdf + !include DynamicTablesPkg/DynamicTables.fdf.inc + + # Multiple Console IO support + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # Virtio Block Device support + INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # FAT filesystem + GPT/MBR partitioning + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # UEFI applications + INF ShellPkg/Application/Shell/Shell.inf + + # Platform driver + INF Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf + + # Bds + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + # Required by PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # AHCI Support + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +BlockSize = 0x1000 +NumBlocks = 0x200 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +# +# These SEC rules are used for ArmPlatformPkg/PrePeiCore module. +# ArmPlatformPkg/PrePeiCore is declared as a SEC module to make GenFv patch +# the UEFI Firmware to jump to ArmPlatformPkg/PrePeiCore entrypoint +# + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform Chandni Cherukuri @ 2021-03-01 13:13 ` Sami Mujawar 0 siblings, 0 replies; 15+ messages in thread From: Sami Mujawar @ 2021-03-01 13:13 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Please find my response inline marked [SAMI]. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri <chandni.cherukuri@arm.com> Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com> Subject: [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform From: Anurag Koul <anurag.koul@arm.com> This patch adds the initial support for Morello FVP platform. Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> --- Platform/ARM/Morello/MorelloPlatform.dec | 59 ++++ Platform/ARM/Morello/MorelloPlatform.dsc.inc | 235 +++++++++++++++ Platform/ARM/Morello/MorelloPlatformFvp.dsc | 60 ++++ Platform/ARM/Morello/MorelloPlatformFvp.fdf | 302 ++++++++++++++++++++ 4 files changed, 656 insertions(+) diff --git a/Platform/ARM/Morello/MorelloPlatform.dec b/Platform/ARM/Morello/MorelloPlatform.dec new file mode 100644 index 000000000000..5bf9f5f12005 --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dec @@ -0,0 +1,59 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = Morello + PACKAGE_GUID = F09A2C11-7864-4B1D-869E-03EE2AD79288 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmMorelloTokenSpaceGuid = { 0x0A8C3A78, 0xA56F, 0x4788, { 0x83, 0xB4, 0xCD, 0x29, 0x62, 0x96, 0x77, 0x51 } } + +[PcdsFixedAtBuild] + # Ramdisk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000003 + + # Virtio Block device + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00000004 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|0x00000000|UINT32|0x00000006 + + # PCIe + gArmMorelloTokenSpaceGuid.PcdPciBusMin|0|UINT32|0x00000009 + gArmMorelloTokenSpaceGuid.PcdPciBusMax|15|UINT32|0x0000000A + gArmMorelloTokenSpaceGuid.PcdPciBusCount|16|UINT32|0x0000000B + gArmMorelloTokenSpaceGuid.PcdPciIoBase|0x0|UINT32|0x0000000C + gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00800000|UINT32|0x0000000D + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x007FFFFF|UINT32|0x0000000E + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x67800000|UINT32|0x0000000F + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base|0x60000000|UINT32|0x00000010 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x07800000|UINT32|0x00000011 + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x677FFFFF|UINT32|0x00000012 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT32|0x00000013 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base|0x900000000|UINT64|0x00000014 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000|UINT64|0x00000015 + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000016 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017 + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x00000018 + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008 diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc b/Platform/ARM/Morello/MorelloPlatform.dsc.inc new file mode 100644 index 000000000000..0715d5e24a6b --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc @@ -0,0 +1,235 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf + BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # Ramdisk Support + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + +[LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + +[LibraryClasses.common.PEI_CORE] + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.common.DXE_DRIVER] + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 + + # System Memory (2GB - 16MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0x8080000000 + + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 + + # PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|50000000 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase [SAMI] The Serial Debug UART (DBG2) and the Console port (SPCR) cannot be shared. [/SAMI] + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C100000 + + # ARM Architectural Timer Frequency + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # ACPI Table Version + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + + # Runtime Variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # RAM Disk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000 + + # PCIe + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # PEI Phase modules + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # DXE + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + } + + # Architectural Protocols + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + + # ACPI Support + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # Bds + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # RAM Disk + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # Required by PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + + # AHCI Support + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc b/Platform/ARM/Morello/MorelloPlatformFvp.dsc new file mode 100644 index 000000000000..04a966c33f8d --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = morellofvp + PLATFORM_GUID = CB995FFD-EAEF-4d5E-8A4B-3213B39CD14A + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) +!endif + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/Morello/MorelloPlatformFvp.fdf + BUILD_NUMBER = 1 + + # Network definition + DEFINE NETWORK_ISCSI_ENABLE = FALSE + +!include Platform/ARM/Morello/MorelloPlatform.dsc.inc +!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +!include DynamicTablesPkg/DynamicTables.dsc.inc +!include Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc + +[LibraryClasses.common] + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PciHostBridgeLib|Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|TRUE + +[PcdsFixedAtBuild.common] + # Virtio Disk + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1C170000 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x200 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|128 + +[Components.common] + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # Platform driver + Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.fdf b/Platform/ARM/Morello/MorelloPlatformFvp.fdf new file mode 100644 index 000000000000..29e7e099cc7b --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.fdf @@ -0,0 +1,302 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_AP_UEFI] +BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x200 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of +# different images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) +# followed by the pipe "|" character, followed by the size of the region, also +# in hex with the leading "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a +# flash device file. This section also defines order the components and modules +# are positioned within the image. The [FV] section consists of define +# statements, set statements and module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # ACPI Support + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # Configuration Manager + INF Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf + + # Dynamic Table fdf + !include DynamicTablesPkg/DynamicTables.fdf.inc + + # Multiple Console IO support + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # Virtio Block Device support + INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # FAT filesystem + GPT/MBR partitioning + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # UEFI applications + INF ShellPkg/Application/Shell/Shell.inf + + # Platform driver + INF Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf + + # Bds + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + # Required by PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # AHCI Support + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +BlockSize = 0x1000 +NumBlocks = 0x200 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +# +# These SEC rules are used for ArmPlatformPkg/PrePeiCore module. +# ArmPlatformPkg/PrePeiCore is declared as a SEC module to make GenFv patch +# the UEFI Firmware to jump to ArmPlatformPkg/PrePeiCore entrypoint +# + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri ` (4 preceding siblings ...) 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform Chandni Cherukuri @ 2021-03-01 13:13 ` Sami Mujawar 5 siblings, 0 replies; 15+ messages in thread From: Sami Mujawar @ 2021-03-01 13:13 UTC (permalink / raw) To: Chandni Cherukuri, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Leif Lindholm, nd Hi Chandni, Thank you for this patch series. Can you add a Platform\ARM\Morello\Readme.md file describing the following, please? - Where to find the documentation for the platform. - Morello FVP binary download location. - Toolchain to be used and location to download the same. - Firmware build instructions and supported build hosts. - Any other dependencies required to boot to the UEFI shell on Morello FVP. This file could be added as a new patch in the v2 series. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri <chandni.cherukuri@arm.com> Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com> Subject: [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Morello is an ARMv8-A platform that implements the capability architecture extension. This patch series provides ARMv8-A architecture enablement for the Morello FVP platform. The changes can be seen at: https://github.com/chandnich/edk2-platforms/tree/morello_plat_support_v1 Anurag Koul (3): Platform/ARM/Morello: Add Platform library implementation Platform/ARM/Morello: Add PlatformDxe driver for Morello Platform/ARM/Morello: Add initial support for Morello Platform Chandni Cherukuri (2): Platform/ARM/Morello: Add support for PciHostBridgeLib Platform/ARM/Morello: Add Configuration Manager for Morello Platform/ARM/Morello/MorelloPlatform.dec | 59 + .../ConfigurationManagerFvp.dsc.inc | 16 + Platform/ARM/Morello/MorelloPlatform.dsc.inc | 235 ++++ Platform/ARM/Morello/MorelloPlatformFvp.dsc | 60 + Platform/ARM/Morello/MorelloPlatformFvp.fdf | 302 +++++ .../ConfigurationManagerDxeFvp.inf | 94 ++ .../Drivers/PlatformDxe/PlatformDxeFvp.inf | 43 + .../PciHostBridgeLib/PciHostBridgeLibFvp.inf | 48 + .../Library/PlatformLib/PlatformLib.inf | 52 + .../ConfigurationManager.h | 304 +++++ .../ConfigurationManagerFvp.h | 81 ++ .../ConfigurationManagerDxe/Platform.h | 91 ++ .../Guid/MorelloVirtioDevicesFormSet.h | 14 + .../ARM/Morello/Include/MorelloPlatform.h | 67 ++ .../ConfigurationManager.c | 1005 +++++++++++++++++ .../ConfigurationManagerFvp.c | 531 +++++++++ .../Drivers/PlatformDxe/PlatformDxeFvp.c | 58 + .../Drivers/PlatformDxe/VirtioDevices.c | 91 ++ .../PciHostBridgeLib/PciHostBridgeLibFvp.c | 182 +++ .../Morello/Library/PlatformLib/PlatformLib.c | 66 ++ .../Library/PlatformLib/PlatformLibMem.c | 194 ++++ .../AslTables/DsdtFvp.asl | 114 ++ .../AslTables/SsdtPciFvp.asl | 130 +++ .../Library/PlatformLib/AArch64/Helper.S | 83 ++ 24 files changed, 3920 insertions(+) create mode 100644 Platform/ARM/Morello/MorelloPlatform.dec create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc create mode 100644 Platform/ARM/Morello/MorelloPlatform.dsc.inc create mode 100644 Platform/ARM/Morello/MorelloPlatformFvp.dsc create mode 100644 Platform/ARM/Morello/MorelloPlatformFvp.fdf create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf create mode 100644 Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h create mode 100644 Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h create mode 100644 Platform/ARM/Morello/Include/MorelloPlatform.h create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c create mode 100644 Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl create mode 100644 Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S -- 2.17.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-03-05 23:32 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-02-24 13:12 [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Chandni Cherukuri 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Chandni Cherukuri 2021-02-26 18:35 ` [edk2-devel] " Thomas Abraham 2021-03-01 5:21 ` chandni.cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager " Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-03-05 23:32 ` Sami Mujawar 2021-02-24 13:12 ` [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform Chandni Cherukuri 2021-03-01 13:13 ` Sami Mujawar 2021-03-01 13:13 ` [edk2-platforms][PATCH V1 0/5] Add Morello FVP platform support Sami Mujawar
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