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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2021 13:14:08.8307 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dcff8a4f-6082-4c21-73c0-08d8dcb3e601 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB4515 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Chandni, Please find my response inline marked [SAMI]. Regards, Sami Mujawar -----Original Message----- From: Chandni Cherukuri =20 Sent: 24 February 2021 01:12 PM To: devel@edk2.groups.io Cc: Ard Biesheuvel ; Leif Lindholm ; Sami Mujawar Subject: [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform = library implementation From: Anurag Koul This patch adds initial Morello Platform Library support. It includes virtual memory map and helper functions for platform initialization. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 ++++++++++= ++++++++++ Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ 5 files changed, 462 insertions(+) diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Pla= tform/ARM/Morello/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..2066d1f3a3f8 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D ArmMorelloLib + FILE_GUID =3D 36853D86-7200-47B4-9408-E962A00963FD + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c [SAMI] Reorder in alphabetical order. Same for the FixedPcd section below. [/SAMI] + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base + + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress + gArmMorelloTokenSpaceGuid.PcdPciIoSize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/= Morello/Include/MorelloPlatform.h new file mode 100644 index 000000000000..f61cfe7f9ee8 --- /dev/null +++ b/Platform/ARM/Morello/Include/MorelloPlatform.h @@ -0,0 +1,67 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_PLATFORM_H__ +#define MORELLO_PLATFORM_H__ [SAMI] See https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specifica= tion/5_source_files/53_include_files#5-3-5-all-include-file-contents-must-b= e-protected-by-a-include-guard There is a ECC patch that has been recently merged to catch these issues. I= would recommend that you run the ECC tool on the files/folders introduced = in this patch series. e.g To run ecc on a folder you could use: python edk2\BaseTools\Source\Python\Ecc\EccMain.py -c edk2\BaseTools\Sour= ce\Python\Ecc\config.ini -e edk2\BaseTools\Source\Python\Ecc\exception.xml = -r Ecc.csv -t [/SAMI] + +#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB + +// ***********************************************************************= ***** +// Platform Memory Map +// ***********************************************************************= ***** + +// SubSystem Peripherals - UART0 +#define MORELLO_UART0_BASE 0x2A400000 +#define MORELLO_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define MORELLO_UART1_BASE 0x2A410000 +#define MORELLO_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define MORELLO_GENERIC_WDOG_BASE 0x2A440000 +#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define MORELLO_GIC_BASE 0x30000000 +#define MORELLO_GICR_BASE 0x300C0000 +#define MORELLO_GIC_SZ SIZE_256KB +#define MORELLO_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000 +#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define MORELLO_EXP_PERIPH_BASE 0x1C000000 +#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000 + +// Platform information structure base address +#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BAS= E + +/* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structu= re + * format. The elements of MORELLO_PLAT_INFO should be always in sync with + * the lower level firmware. + */ +#pragma pack(1) + +typedef struct { + /*! Local DDR memory size in Bytes */ [SAMI] The doxygen comment stype to be used should be /** instead of /*!.=20 Alternatively, you could also follow https://edk2-docs.gitbook.io/edk-ii-c-= coding-standards-specification/appendix_a_common_examples#type-declarations= =20 [/SAMI] + UINT64 LocalDdrSize; + /*! Remote DDR memory size in Bytes */ + UINT64 RemoteDdrSize; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 Mode; +} MORELLO_PLAT_INFO; + +#pragma pack() + +#endif diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platf= orm/ARM/Morello/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..cd06ca5ce53f --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) [SAMI] Please add doxygen function documentation header. Same at other plac= es in this patch series. [/SAMI] +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable =3D mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { + PrePeiCoreGetMpCoreInfo +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Pl= atform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..140a6ec79bd3 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,194 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +// The total number of descriptors, including the final "end-of-table" des= criptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +#if !defined(MDEPKG_NDEBUG) +STATIC CONST CHAR8 *tblAttrDesc[] =3D { + "UNCACHED_UNBUFFERED ", + "NONSECURE_UNCACHED_UNBUFFERED", + "WRITE_BACK ", + "NONSECURE_WRITE_BACK ", + "WB_NONSHAREABLE ", + "NONSECURE_WB_NONSHAREABLE ", + "WRITE_THROUGH ", + "NONSECURE_WRITE_THROUGH ", + "DEVICE ", + "NONSECURE_DEVICE " +}; +#endif + +#define LOG_MEM(desc) DEBUG (( = \ + EFI_D_ERROR, = \ [SAMI] Replace EFI_D_ERROR with DEBUG_ERROR at all places in this patch ser= ies. [/SAMI] + desc, = \ + VirtualMemoryTable[Index].PhysicalBase, = \ + (VirtualMemoryTable[Index].PhysicalBase + = \ + VirtualMemoryTable[Index].Length - 1), = \ + VirtualMemoryTable[Index].Length, = \ + tblAttrDesc[VirtualMemoryTable[Index].Attributes] = \ + )); + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing + a Physical-to-Virtual Memory mapping. This = array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MORELLO_PLAT_INFO * PlatInfo; + UINT64 DramBlock2Size =3D 0; + + PlatInfo =3D (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) [SAMI] Add { } braces, see https://edk2-docs.gitbook.io/edk-ii-c-coding-sta= ndards-specification/5_source_files/57_c_programming#5-7-3-4-1-the-if-state= ment-shall-be-followed-by-a-space-and-then-the-open-parenthesis + DramBlock2Size =3D PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE; + + if (DramBlock2Size !=3D 0) { + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + } + + ASSERT (VirtualMemoryMap !=3D NULL); + Index =3D 0; [SAMI] Redundant. [/SAMI] + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTO= R) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + DEBUG (( + EFI_D_ERROR, + " Memory Map\n--------------------------------------------------------= --\n" + )); + DEBUG (( + EFI_D_ERROR, + "Description : START - END = " \ + "[ SIZE ] { ATTR }\n" + )); + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase =3D MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GIC_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GIC_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GICR_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GICR_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_NON_SECURE_SRAM_BA= SE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_NON_SECURE_SRAM_BA= SE; + VirtualMemoryTable[Index].Length =3D MORELLO_NON_SECURE_SRAM_SZ= ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; + LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_UART0_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_UART0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // DDR Primary + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_WRITE_BACK; + LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // DDR Secondary + if (DramBlock2Size !=3D 0) { + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].Length =3D DramBlock2Size; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_BACK; + LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%0= 16lx ] { %a }\n"); + } + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_EXP_PERIPH_BASE_SZ= ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPciBusM= ax) - + FixedPcdGet32 (PcdPciBusMin= ) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI MMIO32/IO Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPciMmio32Size= ) + + PcdGet32 (PcdPciIoSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI MMIO64 Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPciMmio64Size= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU= TES)0; + + ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Pl= atform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..f6cc087a132c --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,83 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processo= r. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary cor= e. +// Primary core is the core responsible to initialize hardware and run UEF= I. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret --=20 2.17.1