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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2022 07:03:19.6838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d34b1691-ba27-4283-24a1-08da790c1364 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6717 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable +cc: Ard Biesheuvel, Leif Lindholm, Gerd Hoffmann > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Jianyong > Wu via groups.io > Sent: Friday, July 29, 2022 3:22 PM > To: devel@edk2.groups.io; Sami Mujawar > Cc: ard.biesheuvel@linaro.org; Justin He ; Jianyong > Wu > Subject: [edk2-devel] [PATCH 1/2] CloudHv/arm: add PeiMemInfoLib > > Memory layout in CLoud Hypervisor for arm is changed and is different wit= h > Qemu, thus we should build its own PeiMemInfoLib. > The main change in the memory layout is that normal ram may not > contiguous under 4G. The top 64M under 4G is reserved for 32bit device. > > What this patch does: > 1. get all of the memory node from DT; > 2. Init page table for each memory node; 3. Add all of the memory nodes t= o > Hob; > > Signed-off-by: Jianyong Wu > --- > .../CloudHvVirtMemInfoLib.c | 251 ++++++++++++++++++ > .../CloudHvVirtMemInfoPeiLib.inf | 46 ++++ > 2 files changed, 297 insertions(+) > create mode 100755 > ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c > create mode 100755 > ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf > > diff --git > a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c > b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c > new file mode 100755 > index 0000000000..7ae24641d3 > --- /dev/null > +++ > b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c > @@ -0,0 +1,251 @@ > +/** @file > + > + Copyright (c) 2022, Arm Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include #include > + > +#include > + > +// The first memnory node is the one whose base address is the lowest. > +UINT64 FirMemNodeBase =3D 0, FirMemNodeSize =3D 0; // // Cloud Hyperviso= r > +may have more than one memory nodes. Even there is no limit for that, > +// I think 10 is enough in general. > +// > +#define CLOUDHV_MAX_MEM_NODE_NUM 10 > + > +// Record memory node info (base address and size) struct > +CloudHvMemNodeInfo { > + UINT64 Base; > + UINT64 Size; > +}; > + > +struct CloudHvMemNodeInfo > CloudHvMemNode[CLOUDHV_MAX_MEM_NODE_NUM]; > + > +RETURN_STATUS > +EFIAPI > +CloudHvVirtMemInfoPeiLibConstructor ( > + VOID > + ) > +{ > + VOID *DeviceTreeBase; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + INT32 Node, Prev; > + UINT64 CurBase, MemBase; > + UINT64 CurSize; > + CONST CHAR8 *Type; > + INT32 Len; > + CONST UINT64 *RegProp; > + RETURN_STATUS PcdStatus; > + UINT8 Index; > + > + ZeroMem (CloudHvMemNode, sizeof(CloudHvMemNode[0]) * > + CLOUDHV_MAX_MEM_NODE_NUM); > + > + Index =3D 0; > + MemBase =3D FixedPcdGet64 (PcdSystemMemoryBase); ResourceAttributes > =3D > + ( > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED > + ); > + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 > + (PcdDeviceTreeInitialBaseAddress); > + ASSERT (DeviceTreeBase !=3D NULL); > + > + // > + // Make sure we have a valid device tree blob // ASSERT > + (fdt_check_header (DeviceTreeBase) =3D=3D 0); > + > + // > + // Look for the lowest memory node > + // > + for (Prev =3D 0; ; Prev =3D Node) { > + Node =3D fdt_next_node (DeviceTreeBase, Prev, NULL); > + if (Node < 0) { > + break; > + } > + > + // > + // Check for memory node > + // > + Type =3D fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); > + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { > + // > + // Get the 'reg' property of this node. For now, we will assume > + // two 8 byte quantities for base and size, respectively. > + // > + RegProp =3D fdt_getprop (DeviceTreeBase, Node, "reg", &Len); > + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { > + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); > + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); > + > + DEBUG (( > + DEBUG_INFO, > + "%a: System RAM @ 0x%lx - 0x%lx\n", > + __FUNCTION__, > + CurBase, > + CurBase + CurSize - 1 > + )); > + > + if (CurBase =3D=3D MemBase) { > + FirMemNodeBase =3D CurBase; > + FirMemNodeSize =3D CurSize; > + } > + > + CloudHvMemNode[Index].Base =3D CurBase; > + CloudHvMemNode[Index].Size =3D CurSize; > + Index++; > + // We should build Hob seperately for the memory node except the > first one > + if (CurBase !=3D MemBase) { > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + CurBase, > + CurSize > + ); > + } > + if (Index >=3D CLOUDHV_MAX_MEM_NODE_NUM) { > + DEBUG (( > + DEBUG_WARN, > + "%a: memory node larger than %d will not be included into Me= mory > System\n", > + __FUNCTION__, > + CLOUDHV_MAX_MEM_NODE_NUM > + )); > + break; > + } > + } else { > + DEBUG (( > + DEBUG_ERROR, > + "%a: Failed to parse FDT memory node\n", > + __FUNCTION__ > + )); > + } > + } > + } > + > + // > + // Make sure the start of DRAM matches our expectation // ASSERT > + (FixedPcdGet64 (PcdSystemMemoryBase) =3D=3D FirMemNodeBase); PcdStatus > =3D > + PcdSet64S (PcdSystemMemorySize, FirMemNodeSize); > ASSERT_RETURN_ERROR > + (PcdStatus); ASSERT ( > + (((UINT64)PcdGet64 (PcdFdBaseAddress) + > + (UINT64)PcdGet32 (PcdFdSize)) <=3D FirMemNodeBase) || > + ((UINT64)PcdGet64 (PcdFdBaseAddress) >=3D (FirMemNodeBase + > FirMemNodeSize)) > + ); > + > + return RETURN_SUCCESS; > +} > + > +// Number of Virtual Memory Map Descriptors #define > +MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (4 + > CLOUDHV_MAX_MEM_NODE_NUM) > + > +// > +// Core peripherals such as the UART, the GIC and the RTC are // all > +mapped in the 'miscellaneous device I/O' region, which we just map // > +in its entirety rather than device by device. Note that it does not // > +cover any of the NOR flash banks or PCI resource windows. > +// > +#define MACH_VIRT_PERIPH_BASE 0x00400000 #define > MACH_VIRT_PERIPH_SIZE > +0x0FC00000 > + > +// > +// The top of the 64M memory region under 4GB reserved for device // > +#define TOP_32BIT_DEVICE_BASE 0xFC000000 #define > TOP_32BIT_DEVICE_SIZE > +0x04000000 > + > +/** > + Return the Virtual Memory Map of your platform > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize > + the MMU on your platform. > + > + @param[out] VirtualMemoryMap Array of > ARM_MEMORY_REGION_DESCRIPTOR > + describing a Physical-to-Virtual Mem= ory > + mapping. This array must be ended by= a > + zero-filled entry. The allocated mem= ory > + will not be freed. > + > +**/ > +VOID > +ArmVirtGetMemoryMap ( > + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + ) > +{ > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + UINT8 Index =3D 0, i =3D 0; > + > + ASSERT (VirtualMemoryMap !=3D NULL); > + > + VirtualMemoryTable =3D AllocatePool ( > + sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS > + ); > + > + if (VirtualMemoryTable =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", > __FUNCTION__)); > + return; > + } > + // System DRAM > + while (CloudHvMemNode[i].Size !=3D 0) { > + VirtualMemoryTable[Index].PhysicalBase =3D CloudHvMemNode[i].Base; > + VirtualMemoryTable[Index].VirtualBase =3D CloudHvMemNode[i].Base; > + VirtualMemoryTable[Index].Length =3D CloudHvMemNode[i].Size; > + VirtualMemoryTable[Index].Attributes =3D > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + DEBUG (( > + DEBUG_INFO, > + "%a: Dumping System DRAM Memory Node%d Map:\n" > + "\tPhysicalBase: 0x%lX\n" > + "\tVirtualBase: 0x%lX\n" > + "\tLength: 0x%lX\n", > + __FUNCTION__, > + i, > + VirtualMemoryTable[Index].PhysicalBase, > + VirtualMemoryTable[Index].VirtualBase, > + VirtualMemoryTable[Index].Length > + )); > + Index++; > + i++; > + } > + // Memory mapped peripherals (UART, RTC, GIC, virtio-mmio, etc) > + VirtualMemoryTable[Index].PhysicalBase =3D MACH_VIRT_PERIPH_BASE; > + VirtualMemoryTable[Index].VirtualBase =3D MACH_VIRT_PERIPH_BASE; > + VirtualMemoryTable[Index].Length =3D MACH_VIRT_PERIPH_SIZE; > + VirtualMemoryTable[Index].Attributes =3D > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + Index++; > + > + // Map the FV region as normal executable memory > + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64 (PcdFvBaseAddress); > + VirtualMemoryTable[Index].VirtualBase =3D > VirtualMemoryTable[Index].PhysicalBase; > + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdFvSize); > + VirtualMemoryTable[Index].Attributes =3D > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + Index++; > + > + // Memory mapped for 32bit device (like TPM) > + VirtualMemoryTable[Index].PhysicalBase =3D TOP_32BIT_DEVICE_BASE; > + VirtualMemoryTable[Index].VirtualBase =3D TOP_32BIT_DEVICE_BASE; > + VirtualMemoryTable[Index].Length =3D TOP_32BIT_DEVICE_SIZE; > + VirtualMemoryTable[Index].Attributes =3D > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + Index++; > + > + // End of Table > + ZeroMem (&VirtualMemoryTable[Index], sizeof > + (ARM_MEMORY_REGION_DESCRIPTOR)); > + > + *VirtualMemoryMap =3D VirtualMemoryTable; } > diff --git > a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.in > f > b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.i > nf > new file mode 100755 > index 0000000000..5dd96faadd > --- /dev/null > +++ > b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib. > +++ inf > @@ -0,0 +1,46 @@ > +#/* @file > +# > +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. > +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent # #*/ > + > +[Defines] > + INF_VERSION =3D 0x0001001A > + BASE_NAME =3D QemuVirtMemInfoPeiLib > + FILE_GUID =3D 0c4d10cf-d949-49b4-bd13-47a4ae22efc= e > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D ArmVirtMemInfoLib|PEIM > + CONSTRUCTOR =3D CloudHvVirtMemInfoPeiLibConstructor > + > +[Sources] > + CloudHvVirtMemInfoLib.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmVirtPkg/ArmVirtPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + ArmLib > + BaseMemoryLib > + DebugLib > + FdtLib > + PcdLib > + MemoryAllocationLib > + > +[Pcd] > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFvBaseAddress > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdFdSize > + gArmTokenSpaceGuid.PcdFvSize > + gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress > -- > 2.17.1 > > > >=20 > IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.