From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=17.151.62.25; helo=mail-in2.apple.com; envelope-from=afish@apple.com; receiver=edk2-devel@lists.01.org Received: from mail-in2.apple.com (mail-out2.apple.com [17.151.62.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1404D21CF58A3 for ; Thu, 5 Oct 2017 10:17:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; d=apple.com; s=mailout2048s; c=relaxed/simple; q=dns/txt; i=@apple.com; t=1507224042; h=From:Sender:Reply-To:Subject:Date:Message-id:To:Cc:MIME-version:Content-type: Content-transfer-encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-reply-to:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=3/rymyxuKnoZU1+oLDIEVYo4zus9gKRwMUm4R6ASrKY=; b=lSFLW9nRP5zWz5XwEncZjCXbJ4RuNzClqdCQyDrzpj7jkyNafiImKcY28ijwApFY DsXFB91QptOWYRTWzCu9gGWT0c0Re58IvO02zTiBCkh7xhxbr3msKp51bw+8HgD1 SxEEzackYLRoKspJrqFI43wEB40QBhPU1mfBbKh25rF6hYKcrE6NU1IPL+Sbzb7Y lBkgvu4uW5a7q1D2YVOJUh6qvRtQqXAVDrC4RAO/U3RfEUgmjFccp//ZRM7IPcDl b5ANDxgmiabf21w26+J8kPVNVBadg/cYNlPpnYqB8IgBtQUCVLauObR9tqI6YLGP 6xlmajvY/cNQN+mniyv3Cw==; Received: from relay5.apple.com (relay5.apple.com [17.128.113.88]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mail-in2.apple.com (Apple Secure Mail Relay) with SMTP id 50.7E.28433.AE966D95; Thu, 5 Oct 2017 10:20:42 -0700 (PDT) X-AuditID: 11973e11-c4e0f9c000006f11-7e-59d669ea11c8 Received: from nwk-mmpp-sz09.apple.com (nwk-mmpp-sz09.apple.com [17.128.115.80]) by relay5.apple.com (Apple SCV relay) with SMTP id 7A.BA.10385.AE966D95; Thu, 5 Oct 2017 10:20:42 -0700 (PDT) MIME-version: 1.0 Received: from [17.114.155.82] by nwk-mmpp-sz09.apple.com (Oracle Communications Messaging Server 8.0.1.3.20170825 64bit (built Aug 25 2017)) with ESMTPSA id <0OXD006K01IIDU60@nwk-mmpp-sz09.apple.com>; Thu, 05 Oct 2017 10:20:42 -0700 (PDT) Sender: afish@apple.com From: Andrew Fish In-reply-to: Date: Thu, 05 Oct 2017 10:20:42 -0700 Cc: "edk2-devel@lists.01.org" , Ard Biesheuvel Message-id: References: <352A9DE5-0BFE-47C5-BAE7-72B469DA39C2@apple.com> To: Vabhav Sharma X-Mailer: Apple Mail (2.3273) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMLMWRmVeSWpSXmKPExsUi2FAYofsq81qkQfs5LYv/H3YzWuw5dJTZ on/baxYHZo871/aweXTP/sfisfHdDqYA5igum5TUnMyy1CJ9uwSujJ1njrEV/LOrWPptClMD 42uzLkZODgkBE4nHSx4xg9hCAquZJJr+RMPEZ5ztZOti5AKKH2SUeL/0MStIgldAUOLH5Hss XYwcHMwC8hIHz8uChJkFtCS+P2plgaj/yijxZOcfFpCEsIC4xLszm5gh7ESJ6f1rGUFsNgFl iRXzP7CD2JwCsRJPe3YwgcxkEVCV2PhbAWJ8qsSHt7wQW20kupd3QI1/wiSxZ/plsPEiApoS PVN/s0HcLCtxa/YlZpAiCYEJbBJfnz5mmcAoPAvJ2bMQzp6F5OwFjMyrGIVyEzNzdDPzjPQS CwpyUvWS83M3MYJCfbqd4A7G46usDjEKcDAq8fBGPLoSKcSaWFZcmXuIUZqDRUmc9/1/oJBA emJJanZqakFqUXxRaU5q8SFGJg5OqQbGNTclJywun7dpBn/+lh1Na06tu/FB98EPltwfz06e CLVRNF8254DV1Ub1JU333kxwc26K7zhnKLmqxXp5sdPXE7dPX92woPlT0fatP+aEzzBd5WDz 6J9kApf5n+yAIs5lwZfu+7fFsTic+1X4X+7V6czU5e36Cc93WZ/3y+msPvZhimrBSznFfCWW 4oxEQy3mouJEAPim1MdWAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOLMWRmVeSWpSXmKPExsUi2FAcoPsq81qkwbknahb/P+xmtNhz6Ciz Rf+21ywOzB53ru1h8+ie/Y/FY+O7HUwBzFFcNimpOZllqUX6dglcGTvPHGMr+GdXsfTbFKYG xtdmXYycHBICJhIzznaydTFycQgJHGSUeL/0MStIgldAUOLH5HssXYwcHMwC8hIHz8uChJkF tCS+P2plgaj/yijxZOcfFpCEsIC4xLszm5gh7ESJ6f1rGUFsNgFliRXzP7CD2JwCsRJPe3Yw gcxkEVCV2PhbAWJ8qsSHt7wQW20kupd3QI1/wiSxZ/plsPEiApoSPVN/s0HcLCtxa/Yl5gmM ArOQXDoL4dJZSC5dwMi8ilGgKDUnsdJUL7GgICdVLzk/dxMjODgLI3Yw/l9mdYhRgINRiYc3 4tGVSCHWxLLiytxDjBIczEoivO1p1yKFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8zoKAKUE0hNL UrNTUwtSi2CyTBycUg2MLnz327eVVhe3B3798TjveF4wiyPzpK8pu7+Z8YqueLMnQLXsq9LV HU3La05kzJWboDDx2oVvez4t9/JzDfDz+HFGs8Z527S9T52t5wvVtcm3dZh1uwcJbmnJMtPQ LtQ4vHjPTq25JR1xDpZzv8TsjOHV+3CR45m9Ucp03bNLP9x7Zll2avFlJZbijERDLeai4kQA OBZXH0oCAAA= Subject: Re: Clarification about InitializeCpuExceptionHandlers() and TGE bit in hcr_el2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Oct 2017 17:17:20 -0000 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII > On Oct 5, 2017, at 10:14 AM, Vabhav Sharma wrote: > > Andrew Fish, > Yes catching the exception is very critical for debugging. > Looks like, This is the model where edk2 starts from cold boot > > As per ARM Platform documentation(ArmPlatformPkg\Documentation) edk2 starts from either cold boot(SEC Phase) or 2nd stage bootloader(Prepi Phase where Platform ROM code is 1st stage bootloader) and I don't see handlers are installed before dxemain. > Does same model(edk2 from 2nd stage bootloader) exist for x86 as well? > Vabhav, Generally x86 starts from SEC as it contains the traditional x86 reset vector of 0xFFFFFFF0. Thanks, Andrew Fish > Regards, > Vabhav > > From: afish@apple.com [mailto:afish@apple.com] > Sent: Thursday, October 05, 2017 10:32 PM > To: Vabhav Sharma > Cc: Ard Biesheuvel ; edk2-devel@lists.01.org > Subject: Re: [edk2] Clarification about InitializeCpuExceptionHandlers() and TGE bit in hcr_el2 > > > On Oct 5, 2017, at 9:53 AM, Vabhav Sharma > wrote: > > Thanks Andrew Fish, > I understand. > > In PEI Phase, No handlers are installed and there might be pending exception. ExceptionHandlers() can be installed during PEI phase like after initializing the MMU to catch unhandled exception. Please suggest? > > Vabhav, > > It looks like for x86 InitializeCpuExceptionHandlers() is called in SEC and then in CPU PEIM calls InitializeCpuExceptionHandlers(). > > ~/work/src/edk2(master)>git grep InitializeCpuExceptionHandlers > ArmPkg/Drivers/CpuDxe/Exception.c:37: InitializeCpuExceptionHandlers(VectorInfo); > ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c:94:InitializeCpuExceptionHandlers( > ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c:242:NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c:261: Status = InitializeCpuExceptionHandlers (VectorInfoList); > MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h:40:InitializeCpuExceptionHandlers ( > MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h:73: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c:35:InitializeCpuExceptionHandlers ( > MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c:74: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/IA32/SetIdtEntry.c:44: Status = InitializeCpuExceptionHandlers (NULL); > MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c:155: Status = InitializeCpuExceptionHandlers (NULL); > MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c:249: Status = InitializeCpuExceptionHandlers (NULL); > UefiCpuPkg/CpuMpPei/CpuMpPei.c:447: Status = InitializeCpuExceptionHandlers (VectorInfo); > UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h:158:InitializeCpuExceptionHandlersWorker ( > UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:62:InitializeCpuExceptionHandlers ( > UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:69: return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData); > UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:175: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c:88:InitializeCpuExceptionHandlers ( > UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c:105: Status = InitializeCpuExceptionHandlersWorker (VectorInfo, ExceptionHandlerData); > UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c:156: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c:203:InitializeCpuExceptionHandlersWorker ( > UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c:64:InitializeCpuExceptionHandlers ( > UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c:155: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c:62:InitializeCpuExceptionHandlers ( > UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c:69: return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData); > UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c:104: NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or > UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c:646: Status = InitializeCpuExceptionHandlers (NULL); > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c:157: Status = InitializeCpuExceptionHandlers (NULL); > UefiCpuPkg/SecCore/SecMain.c:184: Status = InitializeCpuExceptionHandlers (NULL); > > > At least on x86 the exceptions don't tend to pend, they just happen. So for example an ASSERT() macro can map to an INT 3 (Breakpoint) on x86, you can get GP faults for accessing a non-cononical address, etc. So catching the exception and printing out the PC, and stack trace if possible is very useful for debugging. > > Thanks, > > Andrew Fish > > > > > Dear Arm Folks, > I request you to comment on hcr_el2 usage mentioned in below email > I understand that Enabling TGE bit will route the EL1 exception to EL2.Is there any EL1 code during UEFI execution? > > Regards, > Vabhav > > -----Original Message----- > From: afish@apple.com [mailto:afish@apple.com] > Sent: Thursday, September 28, 2017 7:31 PM > To: Vabhav Sharma > > Cc: edk2-devel@lists.01.org; edk2-devel > > Subject: Re: [edk2] Clarification about InitializeCpuExceptionHandlers() and TGE bit in hcr_el2 > > > > On Sep 28, 2017, at 4:23 AM, Vabhav Sharma > wrote: > > Hi All, > > I see that InitializeCpuExceptionHandlers() is called from DxeMain to take over exception handlers and later from ArmCpuDxe. > Is there any specific purpose to call it from two places during dxe phase? > > Vabhav, > > DxeMain is the DXE Core and that is like (micro) kernel and it is platform agnostic code. InitializeCpuExceptionHandlers() exists in that location to catch unhandled exceptions, especially in the case when no debugger stub is linked in. The CPU Dxe driver abstracts CPU specifics from the DXE Core and it adds supports for interrupts, cachability, etc. and the DXE Core uses services from this driver to abstract CPU implementation. > > To make things even more complex on some platforms PEI and DXE run in entirely different modes. For example on x86 is is common for PEI to be 32-bit and and DXE to be 64-bit. This is mostly due to how complex it is to turn on memory, and the fact that there is no good place to put the page tables prior to memory init. > > I'll let the ARM folks comment on hcr_el2 usage. > > Thanks, > > Andrew Fish > > > Additionally we are setting TGE bit three times in hcr_el2 during PrePei phase(ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c) > and Twice in Dxe phase: dxemain(),ArmCpuDxe > > Please help to clarify or required to be fixed? > > Regards, > Vabhav > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel