From: "Quan Nguyen" <quan@os.amperecomputing.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: Open Source Review <OpenSourceReview@amperecomputing.com>,
Victor Gallardo OS <Victor@os.amperecomputing.com>,
Leif Lindholm <leif@nuviainc.com>,
Ard Biesheuvel <ard.biesheuvel@arm.com>
Subject: Re: [PATCH v1 1/1] ArmPkg/ArmGicDxe: fix writes to GICD_IPRIORITYR<n> when ARE enable
Date: Thu, 26 Nov 2020 13:09:01 +0000 [thread overview]
Message-ID: <DF3A0303-9235-480F-A893-9292A493C7E3@os.amperecomputing.com> (raw)
In-Reply-To: <20201028012112.12125-1-quan@os.amperecomputing.com>
Dear all,
Any comments about this patch ?
Without this patch there are errors recorded in GICT_ERR<n>STATUS as below:
(https://developer.arm.com/documentation/100336/0002/programmers-model/gict-register-summary/error-record-primary-status-register--gict-err-n-status?lang=en)
+ GICT_ERR<n>STATUS = 0x000000006C20030F
That means:
V = 1: Status register is valid
UE = 1: Un-correctable Error
OF = 1: overflow
MV =1 Misc0 and Misc1 are valid
IERR = 0x3 & SERR=0xF: SYN_GICR_ARE = Attempt to access GICR or GICD registers in mode that cannot work.
+ GICT_ERR<n>MISC0 = 0x0000000000000000
ie: Mis0[8:0] = 0: core ID 0
+ GICT_ERR<n>MISC1 = 0x0000000000000000
Thanks,
Quan
On 10/28/20, 08:22, "Quan Nguyen OS" <quan@os.amperecomputing.com> wrote:
According to ARM doc IHI 0069F, section 11.9.18, "Accessing the
GICD_IPRIORITYR<n>:", "These registers are always used when affinity
routing is not enabled. When affinity routing is enabled for the
Security state of an interrupt:
* GICR_IPRIORITYR<n> is used instead of GICD_IPRIORITYR<n> where n = 0
to 7 (that is, for SGIs and PPIs)."
The current ArmGicV3 code tries to initialize all the IPRIORITYR
registers to a default state via the Distributor (GICD), so skip
writes to the first eight IPRIORITYR registers when Affinity Routing
is Enabled.
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Victor Gallardo <Victor@os.amperecomputing.com>
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
---
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index d7da1f198d9e..bc543502481b 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -378,6 +378,7 @@ GicV3DxeInitialize (
UINTN RegShift;
UINT64 CpuTarget;
UINT64 MpId;
+ BOOLEAN AffinityRoutingEnabled = FALSE;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
@@ -391,11 +392,21 @@ GicV3DxeInitialize (
// Routing enabled. So ensure that the ARE bit is set.
if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
+ // If Affinity Routing is Enabled, the first 32 interrupts (SGI and PPI)
+ // can be programmed only through Redistributor interface (GICR).
+ // Initializing the GICD_IPRIORITYR registers for these interrupts can be
+ // skipped as the Redistributor will be powered up and initialized
+ // at the appropriate time (e.g. in EL3 by trusted firmware).
+ AffinityRoutingEnabled = TRUE;
}
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
+ if (AffinityRoutingEnabled && Index < 32) {
+ continue;
+ }
+
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
--
2.28.0
next prev parent reply other threads:[~2020-11-26 13:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 1:21 [PATCH v1 1/1] ArmPkg/ArmGicDxe: fix writes to GICD_IPRIORITYR<n> when ARE enable quan
2020-11-26 13:09 ` Quan Nguyen [this message]
2020-11-27 7:17 ` Ard Biesheuvel
2020-11-28 1:43 ` Quan Nguyen
2020-11-30 9:09 ` Ard Biesheuvel
2020-12-01 3:46 ` Quan Nguyen
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