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Tue, 15 Jun 2021 02:26:53 +0000 From: "Daniel Schaefer" To: Sunil V L , "devel@edk2.groups.io" CC: "Chang, Abner (HPS SW/FW Technologist)" , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt Subject: Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations Thread-Topic: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations Thread-Index: AQHXXstArKXQaqv/80OV9JFoChTrcqsUXGoQ Date: Tue, 15 Jun 2021 02:26:53 +0000 Message-ID: References: <20210611140503.28409-1-sunilvl@ventanamicro.com>,<20210611140807.GA28471@sunil-ThinkPad-T490> In-Reply-To: <20210611140807.GA28471@sunil-ThinkPad-T490> Accept-Language: en-US, de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: ventanamicro.com; dkim=none (message not signed) header.d=none;ventanamicro.com; dmarc=none action=none header.from=hpe.com; x-originating-ip: [123.193.59.220] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c821b822-550e-43c7-f610-08d92fa50a56 x-ms-traffictypediagnostic: DF4PR8401MB0346: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7219; 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boundary="_000_DF4PR8401MB04447B3FAD40F876349B7E42E0309DF4PR8401MB0444_" --_000_DF4PR8401MB04447B3FAD40F876349B7E42E0309DF4PR8401MB0444_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Great commit message, thanks Sunil! Maintainers, please take a look and let us know if there's any other concer= n. This patch lets us build the RISC-V platforms using modern toolchains that = are provided directly by the distributions, rather than building your own f= rom source. Thanks, Daniel ________________________________ From: Sunil V L Sent: Friday, June 11, 2021 22:08 To: devel@edk2.groups.io Cc: Chang, Abner (HPS SW/FW Technologist) ; Schaefer, = Daniel ; Bob Feng ; Liming G= ao ; Yuwei Chen ; Heinrich = Schuchardt Subject: Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT rel= ocations Hi, I just edited the commit message to indicate the module and CC the maintainers. Could I get the feedback please? Thanks Sunil On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote: > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096 > > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > relocations generated by PIE enabled compiler. This also needed > changes to R_RISCV_32 and R_RISCV_64 relocations as explained in > https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-8466= 82710 > > Changes in v2: > - Addressed Daniel's comment on formatting > > Testing: > 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. > 2) Debian 10.2.0 and booted QEMU virt model. > 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. > > Signed-off-by: Sunil V L > > Acked-by: Abner Chang > Reviewed-by: Daniel Schaefer > Tested-by: > > Cc: Bob Feng > Cc: Liming Gao > Cc: Yuwei Chen > Cc: Heinrich Schuchardt > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++---- > 1 file changed, 38 insertions(+), 6 deletions(-) > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C= /GenFw/Elf64Convert.c > index d097db8632..d684318269 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > STATIC UINT8 *mRiscVPass1Targ =3D NULL; > STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL; > STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0; > +STATIC INT32 mRiscVPass1Offset; > +STATIC INT32 mRiscVPass1GotFixup; > > // > // Initialization Function > @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > break; > > case R_RISCV_32: > - *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh= _addr + mCoffSectionsOffset[Sym->st_shndx]); > + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend; > break; > > case R_RISCV_64: > - *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectio= nsOffset[Sym->st_shndx]; > + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend; > break; > > case R_RISCV_HI20: > @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > mRiscVPass1SymSecIndex =3D 0; > break; > > + case R_RISCV_GOT_HI20: > + Value =3D (Sym->st_value - Rel->r_offset); > + mRiscVPass1Offset =3D RV_X(Value, 0, 12); > + Value =3D RV_X(Value, 12, 20); > + *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); > + > + mRiscVPass1Targ =3D Targ; > + mRiscVPass1Sym =3D SymShdr; > + mRiscVPass1SymSecIndex =3D Sym->st_shndx; > + mRiscVPass1GotFixup =3D 1; > + break; > + > case R_RISCV_PCREL_HI20: > mRiscVPass1Targ =3D Targ; > mRiscVPass1Sym =3D SymShdr; > @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( > if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVP= ass1SymSecIndex !=3D 0) { > int i; > Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > - Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > - if(Value & (RISCV_IMM_REACH/2)) { > - Value |=3D ~(RISCV_IMM_REACH-1); > + > + if(mRiscVPass1GotFixup) { > + Value =3D (UINT32)(mRiscVPass1Offset); > + } else { > + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > + if(Value & (RISCV_IMM_REACH/2)) { > + Value |=3D ~(RISCV_IMM_REACH-1); > + } > } > Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsO= ffset[mRiscVPass1SymSecIndex]; > + > if(-2048 > (INT32)Value) { > i =3D (((INT32)Value * -1) / 4096); > Value2 -=3D i; > @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( > } > } > > - *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T= arg, 0, 20)); > + if(mRiscVPass1GotFixup) { > + *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20) > + | (RV_X(*(UINT32*)Targ, 0, 20)); > + /* Convert LD instruction to ADDI */ > + *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13); > + } else { > + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*= )Targ, 0, 20)); > + } > *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*= (UINT32 *)mRiscVPass1Targ, 0, 12)); > } > mRiscVPass1Sym =3D NULL; > mRiscVPass1Targ =3D NULL; > mRiscVPass1SymSecIndex =3D 0; > + mRiscVPass1Offset =3D 0; > + mRiscVPass1GotFixup =3D 0; > break; > > case R_RISCV_ADD64: > @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( > case R_RISCV_GPREL_I: > case R_RISCV_GPREL_S: > case R_RISCV_CALL: > + case R_RISCV_CALL_PLT: > case R_RISCV_RVC_BRANCH: > case R_RISCV_RVC_JUMP: > case R_RISCV_RELAX: > @@ -1528,6 +1558,7 @@ WriteRelocations64 ( > case R_RISCV_GPREL_I: > case R_RISCV_GPREL_S: > case R_RISCV_CALL: > + case R_RISCV_CALL_PLT: > case R_RISCV_RVC_BRANCH: > case R_RISCV_RVC_JUMP: > case R_RISCV_RELAX: > @@ -1537,6 +1568,7 @@ WriteRelocations64 ( > case R_RISCV_SET16: > case R_RISCV_SET32: > case R_RISCV_PCREL_HI20: > + case R_RISCV_GOT_HI20: > case R_RISCV_PCREL_LO12_I: > break; > > -- > 2.25.1 > --_000_DF4PR8401MB04447B3FAD40F876349B7E42E0309DF4PR8401MB0444_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other concer= n.
This patch lets us build the RISC-V platforms using modern toolchains that = are provided directly by the distributions, rather than building your own f= rom source.

Thanks,
Daniel
From: Sunil V L <sunilvl= @ventanamicro.com>
Sent: Friday, June 11, 2021 22:08
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>= ;; Schaefer, Daniel <daniel.schaefer@hpe.com>; Bob Feng <bob.c.fen= g@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Yuwei Chen &l= t;yuwei.chen@intel.com>; Heinrich Schuchardt <xypron.glpk@gmx.de><= br> Subject: Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/= PLT relocations
 
Hi,
    I just edited the commit message to indicate the module = and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096
>
> This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
> relocations generated by PIE enabled compiler. This also needed
> changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
> https://github.com/riscv/riscv-gnu-toolchain/issues/90= 5#issuecomment-846682710
>
> Changes in v2:
>   - Addressed Daniel's comment on formatting
>
> Testing:
> 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
> 2) Debian 10.2.0 and booted QEMU virt model.
> 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
>
> Acked-by: Abner Chang <abner.chang@hpe.com>
> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
> Tested-by: <daniel.schaefer@hpe.com>
>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Yuwei Chen <yuwei.chen@intel.com>
> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
> ---
>  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++= ++----
>  1 file changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Sourc= e/C/GenFw/Elf64Convert.c
> index d097db8632..d684318269 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
>  STATIC UINT8       *mRiscVPass1Tar= g =3D NULL;
>  STATIC Elf_Shdr    *mRiscVPass1Sym =3D NULL;
>  STATIC Elf64_Half  mRiscVPass1SymSecIndex =3D 0;
> +STATIC INT32       mRiscVPass1Offset; > +STATIC INT32       mRiscVPass1GotFixup;=
> 
>  //
>  // Initialization Function
> @@ -479,11 +481,11 @@ WriteSectionRiscV64 (
>      break;
> 
>    case R_RISCV_32:
> -    *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)T= arg) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
> +    *(UINT64 *)Targ =3D Sym->st_value + Rel->r_a= ddend;
>      break;
> 
>    case R_RISCV_64:
> -    *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->= sh_addr + mCoffSectionsOffset[Sym->st_shndx];
> +    *(UINT64 *)Targ =3D Sym->st_value + Rel->r_a= ddend;
>      break;
> 
>    case R_RISCV_HI20:
> @@ -533,6 +535,18 @@ WriteSectionRiscV64 (
>      mRiscVPass1SymSecIndex =3D 0;
>      break;
> 
> +  case R_RISCV_GOT_HI20:
> +    Value =3D (Sym->st_value - Rel->r_offset); > +    mRiscVPass1Offset =3D RV_X(Value, 0, 12);
> +    Value =3D RV_X(Value, 12, 20);
> +    *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(= UINT32*)Targ, 0, 12));
> +
> +    mRiscVPass1Targ =3D Targ;
> +    mRiscVPass1Sym =3D SymShdr;
> +    mRiscVPass1SymSecIndex =3D Sym->st_shndx;
> +    mRiscVPass1GotFixup =3D 1;
> +    break;
> +
>    case R_RISCV_PCREL_HI20:
>      mRiscVPass1Targ =3D Targ;
>      mRiscVPass1Sym =3D SymShdr;
> @@ -545,11 +559,17 @@ WriteSectionRiscV64 (
>      if (mRiscVPass1Targ !=3D NULL &&= mRiscVPass1Sym !=3D NULL && mRiscVPass1SymSecIndex !=3D 0) {
>        int i;
>        Value2 =3D (UINT32)(RV_X(*(U= INT32 *)mRiscVPass1Targ, 12, 20));
> -      Value =3D (UINT32)(RV_X(*(UINT32 *)Tar= g, 20, 12));
> -      if(Value & (RISCV_IMM_REACH/2)) {<= br> > -        Value |=3D ~(RISCV_IMM_REA= CH-1);
> +
> +      if(mRiscVPass1GotFixup) {
> +        Value =3D (UINT32)(mRiscVP= ass1Offset);
> +      } else {
> +        Value =3D (UINT32)(RV_X(*(= UINT32 *)Targ, 20, 12));
> +        if(Value & (RISCV_IMM_= REACH/2)) {
> +          Value |=3D ~(R= ISCV_IMM_REACH-1);
> +        }
>        }
>        Value =3D Value - (UINT32)mR= iscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
> +
>        if(-2048 > (INT32)Value) = {
>          i =3D (((INT32)V= alue * -1) / 4096);
>          Value2 -=3D i; > @@ -569,12 +589,21 @@ WriteSectionRiscV64 (
>          }
>        }
> 
> -      *(UINT32 *)Targ =3D (RV_X(Value, 0, 12= ) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> +      if(mRiscVPass1GotFixup) {
> +        *(UINT32 *)Targ =3D (RV_X(= (UINT32)Value, 0, 12) << 20)
> +           &nb= sp;            =     | (RV_X(*(UINT32*)Targ, 0, 20));
> +        /* Convert LD instruction = to ADDI */
> +        *(UINT32 *)Targ =3D ((*(UI= NT32 *)Targ & ~0x707f) | 0x13);
> +      } else {
> +        *(UINT32 *)Targ =3D (RV_X(= Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> +      }
>        *(UINT32 *)mRiscVPass1Targ = =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, = 12));
>      }
>      mRiscVPass1Sym =3D NULL;
>      mRiscVPass1Targ =3D NULL;
>      mRiscVPass1SymSecIndex =3D 0;
> +    mRiscVPass1Offset =3D 0;
> +    mRiscVPass1GotFixup =3D 0;
>      break;
> 
>    case R_RISCV_ADD64:
> @@ -586,6 +615,7 @@ WriteSectionRiscV64 (
>    case R_RISCV_GPREL_I:
>    case R_RISCV_GPREL_S:
>    case R_RISCV_CALL:
> +  case R_RISCV_CALL_PLT:
>    case R_RISCV_RVC_BRANCH:
>    case R_RISCV_RVC_JUMP:
>    case R_RISCV_RELAX:
> @@ -1528,6 +1558,7 @@ WriteRelocations64 (
>            = ;  case R_RISCV_GPREL_I:
>            = ;  case R_RISCV_GPREL_S:
>            = ;  case R_RISCV_CALL:
> +            ca= se R_RISCV_CALL_PLT:
>            = ;  case R_RISCV_RVC_BRANCH:
>            = ;  case R_RISCV_RVC_JUMP:
>            = ;  case R_RISCV_RELAX:
> @@ -1537,6 +1568,7 @@ WriteRelocations64 (
>            = ;  case R_RISCV_SET16:
>            = ;  case R_RISCV_SET32:
>            = ;  case R_RISCV_PCREL_HI20:
> +            ca= se R_RISCV_GOT_HI20:
>            = ;  case R_RISCV_PCREL_LO12_I:
>            = ;    break;
> 
> --
> 2.25.1
>
--_000_DF4PR8401MB04447B3FAD40F876349B7E42E0309DF4PR8401MB0444_--