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Sat, 15 Aug 2020 04:53:05 +0000 From: "Daniel Schaefer" To: Leif Lindholm , "devel@edk2.groups.io" CC: "Chang, Abner (HPS SW/FW Technologist)" , "Chen, Gilbert" , Michael D Kinney , Ard Biesheuvel Subject: Re: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS Thread-Topic: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS Thread-Index: AQHWbNoUzl6SFtv4DEyMB6F+Xe8keqk3p1qAgAD9mfc= Date: Sat, 15 Aug 2020 04:53:05 +0000 Message-ID: References: <20200807164444.1304-1-daniel.schaefer@hpe.com> <20200807164444.1304-2-daniel.schaefer@hpe.com>,<20200814134053.GW23500@vanye> In-Reply-To: <20200814134053.GW23500@vanye> Accept-Language: en-US, de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nuviainc.com; dkim=none (message not signed) header.d=none;nuviainc.com; dmarc=none action=none header.from=hpe.com; x-originating-ip: [2a01:598:90a4:3e5d:36c7:d0b6:d1fb:595c] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 4f556192-5335-4e78-794b-08d840d718d6 x-ms-traffictypediagnostic: DF4PR8401MB0666: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3513; 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boundary="_000_DF4PR8401MB0444E981A485B02DAF4C2BA7E0410DF4PR8401MB0444_" --_000_DF4PR8401MB0444E981A485B02DAF4C2BA7E0410DF4PR8401MB0444_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Leif, Great, thanks! Yes, we'll fold it into the commits that introduced the mess in the first = place. I just didn't want to make this effort before you sign off on the re= factoring. And hope it was easier to review this way. Yes, we dropped some tables because we rethought how to apply smbios to th= is flexible RISC-V SoC, which doesn't really fit into the rigid view smbios= has of hardware. Cheers, Daniel ________________________________ From: devel@edk2.groups.io on behalf of Leif Lindho= lm Sent: Friday, August 14, 2020 15:40 To: devel@edk2.groups.io ; Schaefer, Daniel Cc: Chang, Abner (HPS SW/FW Technologist) ; Chen, Gil= bert ; Michael D Kinney ;= Ard Biesheuvel Subject: Re: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate RISC-V S= MBIOS Hi Daniel, Thanks for this rework. It looks a massive improvement. On Fri, Aug 07, 2020 at 18:44:44 +0200, Daniel Schaefer wrote: > There was too much code, which wasn't called but it could have generated= those SMBIOS table entries: > > - Type 4 for each core (4xU51, 1xE51) > - Type 7 L1 instruction/data for each core > - Type 7 L2 for U54 > - Type 44 for each core > - Type 4 for the coreplex > - Type 7 L2 for the coreplex > > Now it only has code for those entries: > > - Type 4 for SOC [1x] > - Type 7 L1 for SOC [1x] (even though every hart has own L1, but my Lapt= op's Intel i5 does that also) > - Type 7 L2 for SOC [1x] > - Type 44 for each hart, associated with CPU [5x] > > In addition to simplifying the SMBIOS tables, the code for U54 and E51 i= s > combined, like Leif suggested in his review. > > Here's what happened to the files: > > Expanded: > > - Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLi= b/FirmwareContextProcessorSpecificLib.c > > Deleted file: > > - Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c > - Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > Merged with E51 code into single file: > > - Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > Added SMBIOS Type 7 for L1 Cache, removed duplicated SMBIOS (Type 4 and = 7 code): > > - Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c > > Cc: Abner Chang > Cc: Gilbert Chen > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Ard Biesheuvel > --- > Silicon/SiFive/SiFive.dec | 2 - > .../FreedomU500VC707Board/U500.dsc | 1 - > .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 - > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 1 - > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ---- > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 4 + > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ---- > .../FirmwareContextProcessorSpecificLib.h | 11 + > .../Include/ProcessorSpecificHobData.h | 3 +- > Silicon/SiFive/Include/Library/SiFiveE51.h | 60 ----- > Silicon/SiFive/Include/Library/SiFiveU54.h | 50 ++-- > .../Include/Library/SiFiveU54MCCoreplex.h | 55 ---- > .../FirmwareContextProcessorSpecificLib.c | 26 ++ > .../Universal/Pei/PlatformPei/Platform.c | 2 +- > .../Universal/Pei/PlatformPei/Platform.c | 2 +- > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 58 +---- > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 235 ----------------- > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 244 +++++++----------- > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 ------------- > 19 files changed, 178 insertions(+), 854 deletions(-) I know you dropped some tables, but that's a *nice* diffstat. I guess this is effectively meant to be folded into existing commits? If so: Reviewed-by: Leif Lindholm If not, I might start grumbling about some unrelated cleanup in this patch... / Leif --_000_DF4PR8401MB0444E981A485B02DAF4C2BA7E0410DF4PR8401MB0444_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Leif,

Great, thanks!
Yes, we'll fold it into the commits that introduced the mess in the f= irst place. I just didn't want to make this effort before you sign off on t= he refactoring. And hope it was easier to review this way.

Yes, we dropped some tables because we rethought how to apply smbios = to this flexible RISC-V SoC, which doesn't really fit into the rigid view s= mbios has of hardware.

Cheers,
Daniel
From: devel@edk2.groups.io= <devel@edk2.groups.io> on behalf of Leif Lindholm <leif@nuviainc.= com>
Sent: Friday, August 14, 2020 15:40
To: devel@edk2.groups.io <devel@edk2.groups.io>; Schaefer, Da= niel <daniel.schaefer@hpe.com>
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com&g= t;; Chen, Gilbert <gilbert.chen@hpe.com>; Michael D Kinney <michae= l.d.kinney@intel.com>; Ard Biesheuvel <ard.biesheuvel@linaro.org><= br> Subject: Re: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate R= ISC-V SMBIOS
 
Hi Daniel,

Thanks for this rework. It looks a massive improvement.

On Fri, Aug 07, 2020 at 18:44:44 +0200, Daniel Schaefer wrote:
> There was too much code, which wasn't called but it could have genera= ted those SMBIOS table entries:
>
> - Type 4 for each core (4xU51, 1xE51)
> - Type 7 L1 instruction/data for each core
> - Type 7 L2 for U54
> - Type 44 for each core
> - Type 4 for the coreplex
> - Type 7 L2 for the coreplex
>
> Now it only has code for those entries:
>
> - Type 4 for SOC [1x]
> - Type 7 L1 for SOC [1x] (even though every hart has own L1, but my L= aptop's Intel i5 does that also)
> - Type 7 L2 for SOC [1x]
> - Type 44 for each hart, associated with CPU [5x]
>
> In addition to simplifying the SMBIOS tables, the code for U54 and E5= 1 is
> combined, like Leif suggested in his review.
>
> Here's what happened to the files:
>
> Expanded:
>
> - Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecifi= cLib/FirmwareContextProcessorSpecificLib.c
>
> Deleted file:
>
> - Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> - Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.= c
>
> Merged with E51 code into single file:
>
> - Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
>
> Added SMBIOS Type 7 for L1 Cache, removed duplicated SMBIOS (Type 4 a= nd 7 code):
>
> - Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c=
>
> Cc: Abner Chang <abner.chang@hpe.com>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/SiFive/SiFive.dec      &n= bsp;            = ;  |   2 -
>  .../FreedomU500VC707Board/U500.dsc     = ;       |   1 -
>  .../FreedomU540HiFiveUnleashedBoard/U540.dsc  |  = ; 1 -
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf   | =   1 -
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf   | = 47 ----
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf   | =   4 +
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf   | = 46 ----
>  .../FirmwareContextProcessorSpecificLib.h   &nbs= p; |  11 +
>  .../Include/ProcessorSpecificHobData.h    &= nbsp;   |   3 +-
>  Silicon/SiFive/Include/Library/SiFiveE51.h    |&= nbsp; 60 -----
>  Silicon/SiFive/Include/Library/SiFiveU54.h    |&= nbsp; 50 ++--
>  .../Include/Library/SiFiveU54MCCoreplex.h   &nbs= p; |  55 ----
>  .../FirmwareContextProcessorSpecificLib.c   &nbs= p; |  26 ++
>  .../Universal/Pei/PlatformPei/Platform.c    = ;  |   2 +-
>  .../Universal/Pei/PlatformPei/Platform.c    = ;  |   2 +-
>  .../Library/PeiCoreInfoHobLib/CoreInfoHob.c   | = 58 +----
>  .../Library/PeiCoreInfoHobLib/CoreInfoHob.c   | 235 -= ----------------
>  .../Library/PeiCoreInfoHobLib/CoreInfoHob.c   | 244 += ++++++-----------
>  .../Library/PeiCoreInfoHobLib/CoreInfoHob.c   | 184 -= ------------
>  19 files changed, 178 insertions(+), 854 deletions(-)

I know you dropped some tables, but that's a *nice* diffstat.

I guess this is effectively meant to be folded into existing commits?
If so:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
If not, I might start grumbling about some unrelated cleanup in this
patch...

/
    Leif



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