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devel@edk2.groups.io,ashraf.ali.s@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: F8FRb3GlGRpUP5QUmzVxLEdpx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_DM4PR11MB5280BA2B91E2ECEE6CE23F8AD7A0ADM4PR11MB5280namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=bIHibrgR; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_DM4PR11MB5280BA2B91E2ECEE6CE23F8AD7A0ADM4PR11MB5280namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: >; Thanks., S, Ashraf Ali From: Kuo, Ted Sent: Tuesday, October 31, 2023 2:06 PM To: Ni, Ray ; devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Duggapu, Chinni B ; Ng, = Ray Han Lim ; Zeng, Star ; S= , Ashraf Ali ; Mohapatra, Susovan Subject: RE: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B whe= n calling C function in 64bit Reviewed-by: Ted Kuo > From: Ni, Ray > Sent: Tuesday, October 31, 2023 4:26 PM To: devel@edk2.groups.io; Ni, Ray > Cc: Chiu, Chasel >; Des= imone, Nathaniel L >; Duggapu, Chinni B >; Ng, Ray Han Lim >; Zeng, Star >; Kuo, Ted >; S, As= hraf Ali >; Mohapatra= , Susovan > Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B whe= n calling C function in 64bit Sorry, I copied the maintainers from Maintainers.txt but forgot to change a= ll M/R to "Cc". That caused not all the maintainers/reviewers are CCed. I will fix the commit message before merging. Thanks, Ray ________________________________ From: devel@edk2.groups.io > on behalf of Ni, Ray > Sent: Tuesday, October 31, 2023 4:22 PM To: devel@edk2.groups.io > Cc: Chiu, Chasel > Subject: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when ca= lling C function in 64bit When FSP runs in API mode, it saves the IDTR in its own stack then switches to bootloader's stack before it returns from FspMemoryInit. Next time when the bootloader calls TempRamExit, FSP switches to its own stack and restores IDTR from its stack saved earlier. However, due to a bug in BaseFspSwitchStackLib, the IDTR saved on FSP's stack might be corrupted that results the following TempRamExit call fails inside FSP due to PeiServices pointer cannot be retrieved from IDT.base - 8. The bug is the assembly code doesn't reserve 32 bytes before calling the C routine in 64bit. According to the x86-64 calling convention, caller is responsible for allocating 32 bytes of "shadow space" on the stack right before calling the function (regardless of the actual number of parameters used). When FSP is built in optimization-off mode, the C routine makes use of the 32-byte "shadow space" which is not reserved by the assembly caller. That causes the IDTR saved on the stack is corrupted by the C routine. The patch fixes so by reserving the 32 bytes before calling C routine. Signed-off-by: Ray Ni > Cc: Chasel Chiu > M: Nate DeSimone > M: Duggapu Chinni B > M: Ray Han Lim Ng > R: Star Zeng > R: Ted Kuo > R: Ashraf Ali S > R: Susovan Mohapatra > --- IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm b/In= telFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm index 1ea1220608..e3a7cf002f 100644 --- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -60,7 +60,9 @@ ASM_PFX(FspSwitchStack): ; Load new stack mov rcx, rsp + sub rsp, 0x20 call ASM_PFX(SwapStack) + add rsp, 0x20 mov rsp, rax ; Restore previous contexts -- 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110384): https://edk2.groups.io/g/devel/message/110384 Mute This Topic: https://groups.io/mt/102293342/1712937 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3759105/1712937/893644498= /xyzzy [ray.ni@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110389): https://edk2.groups.io/g/devel/message/110389 Mute This Topic: https://groups.io/mt/102293342/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_DM4PR11MB5280BA2B91E2ECEE6CE23F8AD7A0ADM4PR11MB5280namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Reviewed-by: <ashraf.ali.s@intel.com>;

 

Thanks.,=

S, Ashraf Ali<= /o:p>

 

From: Kuo, Ted <ted.kuo@intel.com>
Sent: Tuesday, October 31, 2023 2:06 PM
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel = L <nathaniel.l.desimone@intel.com>; Duggapu, Chinni B <chinni.b.du= ggapu@intel.com>; Ng, Ray Han Lim <ray.han.lim.ng@intel.com>; Zeng= , Star <star.zeng@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.co= m>; Mohapatra, Susovan <susovan.mohapatra@intel.com>
Subject: RE: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve = 32B when calling C function in 64bit

 

Reviewed-by: Ted Kuo <ted.kuo@intel.com>

 

From: Ni, Ray <ray.ni@intel.com>
Sent: Tuesday, October 31, 2023 4:26 PM
To: devel@edk2.groups.io= ; Ni, Ray <ray.ni@intel.com><= br> Cc: Chiu, Chasel <chasel= .chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Duggapu, = Chinni B <chinni.b.duggapu= @intel.com>; Ng, Ray Han Lim <ray.han.li= m.ng@intel.com>; Zeng, Star <star.zeng@intel.com>; Kuo, Ted <ted.kuo@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Mohapatra, Susovan <suso= van.mohapatra@intel.com>
Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve = 32B when calling C function in 64bit

 

Sorry, I copied the maintainers from Maintainers.txt but f= orgot to change all M/R to "Cc". That caused not all the maintain= ers/reviewers are CCed.

I will fix the commit message before merging.

 

Thanks,

Ray

From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of= Ni, Ray <ray.ni@intel.com> Sent: Tuesday, October 31, 2023 4:22 PM
To: devel@edk2.groups.io= <devel@edk2.groups.io> Cc: Chiu, Chasel <chasel= .chiu@intel.com>
Subject: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B = when calling C function in 64bit

 

When FSP runs in API = mode, it saves the IDTR in its own stack then
switches to bootloader's stack before it returns from FspMemoryInit.
Next time when the bootloader calls TempRamExit, FSP switches to
its own stack and restores IDTR from its stack saved earlier.

However, due to a bug in BaseFspSwitchStackLib, the IDTR saved on
FSP's stack might be corrupted that results the following TempRamExit
call fails inside FSP due to PeiServices pointer cannot be retrieved
from IDT.base - 8.

The bug is the assembly code doesn't reserve 32 bytes before calling
the C routine in 64bit. According to the x86-64 calling convention,
caller is responsible for allocating 32 bytes of "shadow space" o= n the
stack right before calling the function (regardless of the actual
number of parameters used).

When FSP is built in optimization-off mode, the C routine makes use
of the 32-byte "shadow space" which is not reserved by the assemb= ly
caller. That causes the IDTR saved on the stack is corrupted by the
C routine.
The patch fixes so by reserving the 32 bytes before calling C routine.

Signed-off-by: Ray Ni <ray.ni@intel.= com>
Cc: Chasel Chiu <chasel.chiu@in= tel.com>
M: Nate DeSimone <nath= aniel.l.desimone@intel.com>
M: Duggapu Chinni B <chinn= i.b.duggapu@intel.com>
M: Ray Han Lim Ng <ray.han.l= im.ng@intel.com>
R: Star Zeng <star.zeng@intel.com= >
R: Ted Kuo <ted.kuo@intel.com&g= t;
R: Ashraf Ali S <ashraf.ali.s@= intel.com>
R: Susovan Mohapatra <sus= ovan.mohapatra@intel.com>
---
 IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm | 4 +++-  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm b/In= telFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
index 1ea1220608..e3a7cf002f 100644
--- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
@@ -1,6 +1,6 @@
 ;--------------------------------------------------------------------= ----------

 ;

-; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.<BR= >

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ; Abstract:

@@ -60,7 +60,9 @@ ASM_PFX(FspSwitchStack):
 

     ; Load new stack

     mov     rcx, rsp

+    sub     rsp, 0x20

     call    ASM_PFX(SwapStack)

+    add     rsp, 0x20

     mov     rsp, rax

 

     ; Restore previous contexts

--
2.39.1.windows.1



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