* [edk2-devel][PATCH V1 1/1] UefiCpuPkg/SecCore: Add debug messages to illuminate data flow
@ 2022-06-27 22:48 Oram, Isaac W
2022-07-08 0:33 ` Dong, Eric
0 siblings, 1 reply; 2+ messages in thread
From: Oram, Isaac W @ 2022-06-27 22:48 UTC (permalink / raw)
To: devel
Cc: Isaac Oram, Eric Dong, Ray Ni, Rahul Kumar, Debkumar De,
Harry Han, Catharine West
Add debug messages to make it easier to verify PlatformSecLib
is passing the data properly.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
UefiCpuPkg/SecCore/SecMain.c | 37 ++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index a7526be9dd..4edf0ce972 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -167,6 +167,15 @@ SecStartup (
EFI_SOFTWARE_SEC | EFI_SW_SEC_PC_ENTRY_POINT
);
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() TempRAM Base: 0x%x, TempRAM Size: 0x%x, BootFirmwareVolume 0x%x\n",
+ __FUNCTION__,
+ TempRamBase,
+ SizeOfRam,
+ BootFirmwareVolume
+ ));
+
PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);
if (PeiStackSize == 0) {
PeiStackSize = (SizeOfRam >> 1);
@@ -229,6 +238,20 @@ SecStartup (
SecCoreData.StackBase = (VOID *)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = PeiStackSize;
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size: 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackSize: 0x%x\n",
+ __FUNCTION__,
+ SecCoreData.BootFirmwareVolumeBase,
+ SecCoreData.BootFirmwareVolumeSize,
+ SecCoreData.TemporaryRamBase,
+ SecCoreData.TemporaryRamSize,
+ SecCoreData.PeiTemporaryRamBase,
+ SecCoreData.PeiTemporaryRamSize,
+ SecCoreData.StackBase,
+ SecCoreData.StackSize
+ ));
+
//
// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
//
@@ -318,6 +341,13 @@ SecStartupPhase2 (
}
}
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() PeiCoreEntryPoint: 0x%x\n",
+ __FUNCTION__,
+ PeiCoreEntryPoint
+ ));
+
if (PpiList != NULL) {
AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *)SecCoreData->PeiTemporaryRamBase;
@@ -360,6 +390,13 @@ SecStartupPhase2 (
//
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() PeiTemporaryRamBase: 0x%x, PeiTemporaryRamSize: 0x%x\n",
+ __FUNCTION__,
+ SecCoreData->PeiTemporaryRamBase,
+ SecCoreData->PeiTemporaryRamSize
+ ));
} else {
//
// No addition PPI, PpiList directly point to the common PPI list.
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [edk2-devel][PATCH V1 1/1] UefiCpuPkg/SecCore: Add debug messages to illuminate data flow
2022-06-27 22:48 [edk2-devel][PATCH V1 1/1] UefiCpuPkg/SecCore: Add debug messages to illuminate data flow Oram, Isaac W
@ 2022-07-08 0:33 ` Dong, Eric
0 siblings, 0 replies; 2+ messages in thread
From: Dong, Eric @ 2022-07-08 0:33 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io
Cc: Ni, Ray, Kumar, Rahul1, De, Debkumar, Han, Harry, West, Catharine
Reviewed-by: Eric Dong <eric.dong@intel.com>
-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@intel.com>
Sent: Tuesday, June 28, 2022 6:49 AM
To: devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@intel.com>; Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>
Subject: [edk2-devel][PATCH V1 1/1] UefiCpuPkg/SecCore: Add debug messages to illuminate data flow
Add debug messages to make it easier to verify PlatformSecLib is passing the data properly.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
UefiCpuPkg/SecCore/SecMain.c | 37 ++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index a7526be9dd..4edf0ce972 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -167,6 +167,15 @@ SecStartup (
EFI_SOFTWARE_SEC | EFI_SW_SEC_PC_ENTRY_POINT
);
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() TempRAM Base: 0x%x, TempRAM Size: 0x%x, BootFirmwareVolume 0x%x\n",
+ __FUNCTION__,
+ TempRamBase,
+ SizeOfRam,
+ BootFirmwareVolume
+ ));
+
PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);
if (PeiStackSize == 0) {
PeiStackSize = (SizeOfRam >> 1);
@@ -229,6 +238,20 @@ SecStartup (
SecCoreData.StackBase = (VOID *)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = PeiStackSize;
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size: 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackSize: 0x%x\n",
+ __FUNCTION__,
+ SecCoreData.BootFirmwareVolumeBase,
+ SecCoreData.BootFirmwareVolumeSize,
+ SecCoreData.TemporaryRamBase,
+ SecCoreData.TemporaryRamSize,
+ SecCoreData.PeiTemporaryRamBase,
+ SecCoreData.PeiTemporaryRamSize,
+ SecCoreData.StackBase,
+ SecCoreData.StackSize
+ ));
+
//
// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
//
@@ -318,6 +341,13 @@ SecStartupPhase2 (
}
}
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() PeiCoreEntryPoint: 0x%x\n",
+ __FUNCTION__,
+ PeiCoreEntryPoint
+ ));
+
if (PpiList != NULL) {
AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *)SecCoreData->PeiTemporaryRamBase;
@@ -360,6 +390,13 @@ SecStartupPhase2 (
//
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() PeiTemporaryRamBase: 0x%x, PeiTemporaryRamSize: 0x%x\n",
+ __FUNCTION__,
+ SecCoreData->PeiTemporaryRamBase,
+ SecCoreData->PeiTemporaryRamSize
+ ));
} else {
//
// No addition PPI, PpiList directly point to the common PPI list.
--
2.36.1.windows.1
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2022-07-08 0:33 ` Dong, Eric
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