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boundary="_000_DM4PR11MB6480A75ABD77486E5B294ED8FEA29DM4PR11MB6480namp_" --_000_DM4PR11MB6480A75ABD77486E5B294ED8FEA29DM4PR11MB6480namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Eric Dong From: Ni, Ray Sent: Tuesday, May 24, 2022 4:02 PM To: Wang, Jian J ; devel@edk2.groups.io Cc: Dong, Eric Subject: Re: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code p= ages for DXE instance Jian, Ia32/ExceptionHandlerAsm.nasm is used by 32bit DxeCpuExceptionHandlerLib in= stance. I agree the commit message is not correct. The commit message says SEC still creates 32 entries but 32bit SEC creates 256 entries. I will update the commit message to align to code behavior. Thanks, Ray ________________________________________ From: Wang, Jian J > Sent: Monday, May 23, 2022 0:40 To: devel@edk2.groups.io; Ni, Ray Cc: Dong, Eric Subject: RE: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code p= ages for DXE instance Ray, You changed "%rep 32" to "%rep 256" in Ia32/ExceptionHandlerAsm.nasm. According to my understanding and your comments, this should be done only to X64 code, right? Regards, Jian > -----Original Message----- > From: devel@edk2.groups.io > On Behalf Of Ni, Ray > Sent: Friday, May 20, 2022 10:16 PM > To: devel@edk2.groups.io > Cc: Dong, Eric > > Subject: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code pag= es > for DXE instance > > Today the DXE instance allocates code page and then copies the IDT > vectors to the allocated code page. Then it fixes up the vector number > in the IDT vector. > > But if we update the NASM file to generate 256 IDT vectors, there is > no need to do the copy and fix-up. > > A side effect is up to 4096 bytes (HOOKAFTER_STUB_SIZE * 256) is > used for 256 IDT vectors. While 32 IDT vectors only require 512 bytes. > > But considering the code logic simplification, 3.5K space is not a big > deal. SEC instance still generates 32 IDT vectors so no impact to SEC. > If 3.5K is too much a waste in PEI phase, we can enhance the code > further to generate 32 vectors for PEI. > > Signed-off-by: Ray Ni > > Cc: Eric Dong > > --- > .../CpuExceptionHandlerLib/DxeException.c | 22 ------------------- > .../Ia32/ExceptionHandlerAsm.nasm | 4 ++-- > .../X64/ExceptionHandlerAsm.nasm | 2 ++ > .../X64/Xcode5ExceptionHandlerAsm.nasm | 9 ++++---- > 4 files changed, 9 insertions(+), 28 deletions(-) > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c > index 61f11e98f8..5083c4b8e8 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c > @@ -95,9 +95,6 @@ InitializeCpuInterruptHandlers ( > IA32_DESCRIPTOR IdtDescriptor; > > UINTN IdtEntryCount; > > EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; > > - UINTN Index; > > - UINTN InterruptEntry; > > - UINT8 *InterruptEntryCode; > > RESERVED_VECTORS_DATA *ReservedVectors; > > EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; > > > > @@ -138,25 +135,6 @@ InitializeCpuInterruptHandlers ( > AsmGetTemplateAddressMap (&TemplateMap); > > ASSERT (TemplateMap.ExceptionStubHeaderSize <=3D HOOKAFTER_STUB_SIZE); > > > > - Status =3D gBS->AllocatePool ( > > - EfiBootServicesCode, > > - TemplateMap.ExceptionStubHeaderSize * CPU_INTERRUPT_NU= M, > > - (VOID **)&InterruptEntryCode > > - ); > > - ASSERT (!EFI_ERROR (Status) && InterruptEntryCode !=3D NULL); > > - > > - InterruptEntry =3D (UINTN)InterruptEntryCode; > > - for (Index =3D 0; Index < CPU_INTERRUPT_NUM; Index++) { > > - CopyMem ( > > - (VOID *)InterruptEntry, > > - (VOID *)TemplateMap.ExceptionStart, > > - TemplateMap.ExceptionStubHeaderSize > > - ); > > - AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID > *)TemplateMap.ExceptionStart); > > - InterruptEntry +=3D TemplateMap.ExceptionStubHeaderSize; > > - } > > - > > - TemplateMap.ExceptionStart =3D (UINTN)InterruptEnt= ryCode; > > mExceptionHandlerData.IdtEntryCount =3D CPU_INTERRUPT_NUM; > > mExceptionHandlerData.ReservedVectors =3D ReservedVectors; > > mExceptionHandlerData.ExternalInterruptHandler =3D ExternalInterruptHa= ndler; > > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas > m > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas > m > index 3fe9aed1e8..8ed2b8f455 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas > m > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas > m > @@ -33,7 +33,7 @@ ALIGN 8 > ; > > AsmIdtVectorBegin: > > %assign Vector 0 > > -%rep 32 > > +%rep 256 > > push byte %[Vector]; > > push eax > > mov eax, ASM_PFX(CommonInterruptEntry) > > @@ -439,7 +439,7 @@ ASM_PFX(AsmGetTemplateAddressMap): > > > mov ebx, dword [ebp + 0x8] > > mov dword [ebx], AsmIdtVectorBegin > > - mov dword [ebx + 0x4], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 > > + mov dword [ebx + 0x4], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 256 > > mov dword [ebx + 0x8], HookAfterStubBegin > > > > popad > > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > index 9a806d1f86..aaf8d622e6 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > @@ -31,6 +31,8 @@ SECTION .text > > > ALIGN 8 > > > > +; Generate 32 IDT vectors. > > +; 32 IDT vectors are enough because interrupts (32+) are not enabled in = SEC and > PEI phase. > > AsmIdtVectorBegin: > > %assign Vector 0 > > %rep 32 > > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAs > m.nasm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAs > m.nasm > index 9c72fa5815..7c0e3d3b0b 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAs > m.nasm > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAs > m.nasm > @@ -53,9 +53,10 @@ SECTION .text > > > ALIGN 8 > > > > +; Generate 256 IDT vectors. > > AsmIdtVectorBegin: > > %assign Vector 0 > > -%rep 32 > > +%rep 256 > > push byte %[Vector] > > push rax > > mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterrup= tEntry) > > @@ -453,16 +454,16 @@ global ASM_PFX(AsmGetTemplateAddressMap) > ASM_PFX(AsmGetTemplateAddressMap): > > lea rax, [AsmIdtVectorBegin] > > mov qword [rcx], rax > > - mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / = 32 > > + mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / = 256 > > lea rax, [HookAfterStubHeaderBegin] > > mov qword [rcx + 0x10], rax > > > > ; Fix up CommonInterruptEntry address > > lea rax, [ASM_PFX(CommonInterruptEntry)] > > lea rcx, [AsmIdtVectorBegin] > > -%rep 32 > > +%rep 256 > > mov qword [rcx + (JmpAbsoluteAddress - 8 - HookAfterStubHeaderBeg= in)], > rax > > - add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 > > + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 256 > > %endrep > > ; Fix up HookAfterStubHeaderEnd > > lea rax, [HookAfterStubHeaderEnd] > > -- > 2.35.1.windows.2 > > > > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#89916): https://edk2.groups.io/g/devel/message/89916 > Mute This Topic: https://groups.io/mt/91231767/1768734 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [jian.j.wang@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D > --_000_DM4PR11MB6480A75ABD77486E5B294ED8FEA29DM4PR11MB6480namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Acked-by: Eric Dong <eric.dong@intel.com>=

 

From: Ni, Ray <ray.ni@intel.com>
Sent: Tuesday, May 24, 2022 4:02 PM
To: Wang, Jian J <jian.j.wang@intel.com>; devel@edk2.groups.io=
Cc: Dong, Eric <eric.dong@intel.com>
Subject: Re: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating= code pages for DXE instance

 

Jian,
Ia32/ExceptionHandlerAsm.nasm is used=  by 32bit DxeCpuExceptionHandlerLib instance.
I agree the commit message&= nbsp;is not correct. The commit message says<= /span>
SEC still creates 32 entrie= s but 32bit SEC creates 256 entries.
I will update the commit&nb= sp;message to align to code behavior.

Thanks,
Ray

________________________________________=
From: Wang, Jian J <jian.j.wang@intel.com> Sent: Monday, May 23, 2022&= nbsp;0:40
To: devel@edk2.groups.io; Ni, Ray
Cc: Dong, Eric
Subject: RE: [edk2-devel] [PATCH=  1/5] CpuException: Avoid allocating code pag= es for DXE instance

Ray,

You changed "%rep 32"&= nbsp;to "%rep 256" in Ia32/ExceptionHandlerAs= m.nasm.
According to my understanding&nb= sp;and your comments, this should be done
only to X64 code, right?

Regards,
Jian

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of = ;Ni, Ray
> Sent: Friday, May 20,=  2022 10:16 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>
> Subject: [edk2-devel] [PAT= CH 1/5] CpuException: Avoid allocating code p= ages
> for DXE instance >
> Today the DXE instanc= e allocates code page and then copies th= e IDT
> vectors to the alloca= ted code page. Then it fixes up the = ;vector number
> in the IDT vector.
>
> But if we update = ;the NASM file to generate 256 IDT vecto= rs, there is
> no need to do th= e copy and fix-up.
>
> A side effect is = ;up to 4096 bytes (HOOKAFTER_STUB_SIZE * 256)=  is
> used for 256 IDT = ;vectors. While 32 IDT vectors only require&n= bsp;512 bytes.
>
> But considering the c= ode logic simplification, 3.5K space is not&n= bsp;a big
> deal. SEC instance st= ill generates 32 IDT vectors so no impac= t to SEC.
> If 3.5K is too m= uch a waste in PEI phase, we can en= hance the code
> further to generate 3= 2 vectors for PEI.
>
> Signed-off-by: Ray Ni = ;<ray.ni@intel.com> > Cc: Eric Dong <eric.dong@intel.com>
> ---
>  .../CpuExceptionHandlerLib/Dxe= Exception.c     | 22 -------------------=
>  .../Ia32/ExceptionHandlerAsm.n= asm            =  |  4 ++--
>  .../X64/ExceptionHandlerAsm.na= sm            &= nbsp; |  2 ++
>  .../X64/Xcode5ExceptionHandler= Asm.nasm        |  9 = ;++++----
>  4 files changed,&nbs= p;9 insertions(+), 28 deletions(-)
>
> diff --git a/UefiCpuPkg/Li= brary/CpuExceptionHandlerLib/DxeException.c
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/DxeException.c
> index 61f11e98f8..5083c4b8e8&nb= sp;100644
> --- a/UefiCpuPkg/Library/CpuExc= eptionHandlerLib/DxeException.c
> +++ b/UefiCpuPkg/Library/CpuExc= eptionHandlerLib/DxeException.c
> @@ -95,9 +95,6 @@&nbs= p;InitializeCpuInterruptHandlers (
>    IA32_DESCRIPTOR&nb= sp;            =     IdtDescriptor;
>
>    UINTN  &= nbsp;           &nbs= p;            I= dtEntryCount;
>
>    EXCEPTION_HANDLER_= TEMPLATE_MAP  TemplateMap;
>
> -  UINTN   =             &nb= sp;           Index;=
>
> -  UINTN   =             &nb= sp;           Interr= uptEntry;
>
> -  UINT8   =             &nb= sp;           *Inter= ruptEntryCode;
>
>    RESERVED_VECTORS_D= ATA           *Reser= vedVectors;
>
>    EFI_CPU_INTERRUPT_= HANDLER       *ExternalInterruptHandler;=
>
>
>
> @@ -138,25 +135,6 @@&= nbsp;InitializeCpuInterruptHandlers (
>    AsmGetTemplateAddr= essMap (&TemplateMap);
>
>    ASSERT (Templ= ateMap.ExceptionStubHeaderSize <=3D HOOKAFTER_STUB_SIZE);
>
>
>
> -  Status =3D gB= S->AllocatePool (
>
> -      = ;            Ef= iBootServicesCode,
>
> -      = ;            Te= mplateMap.ExceptionStubHeaderSize * CPU_INTERRUPT_NUM,
>
> -      = ;            (V= OID **)&InterruptEntryCode
>
> -      = ;            );=
>
> -  ASSERT (!EFI_ERROR=  (Status) && InterruptEntryCode !=3D NULL)= ;
>
> -
>
> -  InterruptEntry =3D=  (UINTN)InterruptEntryCode;
>
> -  for (Index = =3D 0; Index < CPU_INTERRUPT_NUM; Index++) = ;{
>
> -    CopyMem&nbs= p;(
>
> -      = ;(VOID *)InterruptEntry,
>
> -      = ;(VOID *)TemplateMap.ExceptionStart,
>
> -      = ;TemplateMap.ExceptionStubHeaderSize
>
> -      = ;);
>
> -    AsmVectorNu= mFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID
> *)TemplateMap.ExceptionStart);
>
> -    InterruptEn= try +=3D TemplateMap.ExceptionStubHeaderSize;
>
> -  }
>
> -
>
> -  TemplateMap.ExceptionSt= art            =          =3D (UINTN)Inter= ruptEntryCode;
>
>    mExceptionHandlerD= ata.IdtEntryCount         &nbs= p;  =3D CPU_INTERRUPT_NUM;
>
>    mExceptionHandlerD= ata.ReservedVectors         &n= bsp;=3D ReservedVectors;
>
>    mExceptionHandlerD= ata.ExternalInterruptHandler =3D ExternalInterruptHandler;=
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> index 3fe9aed1e8..8ed2b8f455&nb= sp;100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> +++
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> @@ -33,7 +33,7 @@&nbs= p;ALIGN   8
>  ;
>
>  AsmIdtVectorBegin:
>
>  %assign Vector 0
>
> -%rep  32
>
> +%rep  256
>
>      push&n= bsp;   byte %[Vector];
>
>      push&n= bsp;   eax
>
>      mov&nb= sp;    eax, ASM_PFX(CommonInterruptEntry) >
> @@ -439,7 +439,7 @@&n= bsp;ASM_PFX(AsmGetTemplateAddressMap):
>
>
>      mov&nb= sp;ebx, dword [ebp + 0x8]
>
>      mov&nb= sp;dword [ebx],      AsmIdtVectorBegin
>
> -    mov dw= ord [ebx + 0x4], (AsmIdtVectorEnd - AsmIdtVec= torBegin) / 32
>
> +    mov dw= ord [ebx + 0x4], (AsmIdtVectorEnd - AsmIdtVec= torBegin) / 256
>
>      mov&nb= sp;dword [ebx + 0x8], HookAfterStubBegin
>
>
>
>      popad<= /span>
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/ExceptionHandlerAsm.nasm
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/ExceptionHandlerAsm.nasm
> index 9a806d1f86..aaf8d622e6&nb= sp;100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/ExceptionHandlerAsm.nasm
> +++
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/ExceptionHandlerAsm.nasm
> @@ -31,6 +31,8 @@&nbs= p;SECTION .text
>
>
>  ALIGN   8
>
>
>
> +; Generate 32 IDT&nb= sp;vectors.
>
> +; 32 IDT vectors&nbs= p;are enough because interrupts (32+) are not=  enabled in SEC and
> PEI phase.
>
>  AsmIdtVectorBegin:
>
>  %assign Vector 0
>
>  %rep  32
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/Xcode5ExceptionHandlerAs
> m.nasm
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/Xcode5ExceptionHandlerAs
> m.nasm
> index 9c72fa5815..7c0e3d3b0b&nb= sp;100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/Xcode5ExceptionHandlerAs
> m.nasm
> +++
> b/UefiCpuPkg/Library/CpuExceptionHan= dlerLib/X64/Xcode5ExceptionHandlerAs
> m.nasm
> @@ -53,9 +53,10 @@&nb= sp;SECTION .text
>
>
>  ALIGN   8
>
>
>
> +; Generate 256 IDT&n= bsp;vectors.
>
>  AsmIdtVectorBegin:
>
>  %assign Vector 0
>
> -%rep  32
>
> +%rep  256
>
>      push&n= bsp;   byte %[Vector]
>
>      push&n= bsp;   rax
>
>      mov&nb= sp;    rax, strict qword 0 ; &= nbsp;  mov     rax, ASM_PFX(CommonI= nterruptEntry)
>
> @@ -453,16 +454,16 @@=  global ASM_PFX(AsmGetTemplateAddressMap)
>  ASM_PFX(AsmGetTemplateAddressM= ap):
>
>      lea&nb= sp;    rax, [AsmIdtVectorBegin]
>
>      mov&nb= sp;    qword [rcx], rax
>
> -    mov &n= bsp;   qword [rcx + 0x8],  (AsmIdtV= ectorEnd - AsmIdtVectorBegin) / 32
>
> +    mov &n= bsp;   qword [rcx + 0x8],  (AsmIdtV= ectorEnd - AsmIdtVectorBegin) / 256
>
>      lea&nb= sp;    rax, [HookAfterStubHeaderBegin]
>
>      mov&nb= sp;    qword [rcx + 0x10], rax
>
>
>
>  ; Fix up Common= InterruptEntry address
>
>      lea&nb= sp;   rax, [ASM_PFX(CommonInterruptEntry)]
>
>      lea&nb= sp;   rcx, [AsmIdtVectorBegin]
>
> -%rep  32
>
> +%rep  256
>
>      mov&nb= sp;   qword [rcx + (JmpAbsoluteAddress -=  8 - HookAfterStubHeaderBegin)],
> rax
>
> -    add &n= bsp;  rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin)&n= bsp;/ 32
>
> +    add &n= bsp;  rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin)&n= bsp;/ 256
>
>  %endrep
>
>  ; Fix up HookAf= terStubHeaderEnd
>
>      lea&nb= sp;   rax, [HookAfterStubHeaderEnd]
>
> --
> 2.35.1.windows.2
>
>
>
> -=3D-=3D-=3D-=3D-=3D-=3D
> Groups.io Links: You = receive all messages sent to this group.
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>

--_000_DM4PR11MB6480A75ABD77486E5B294ED8FEA29DM4PR11MB6480namp_--