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[AMD Official Use Only - AMD Internal Distribution Only]


Hi Liming,

Sorry for the late response. I already created a pull request for it.

Regards,
Neo

From: gaoliming <gaolimi= ng@byosoft.com.cn>
Sent: Wednesday, May 15, 2024 8:08 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; Chang, Abner = <Abner.Chang@amd.com>; Hsueh, Hong-Chih (Neo) <Hong-Chih.Hsueh@amd= .com>
Cc: michael.d.kinney@intel.com <michael.d.kinney@intel.com>; z= higuang.liu@intel.com <zhiguang.liu@intel.com>; He, Jiangang <Jian= gang.He@amd.com>
Subject: =BB=D8=B8=B4: [edk2-devel] [PATCH] MdePkg: Remove non-ASCII= characters from header file (BZ# 4775)
 
Caution: This message originated from an External = Source. Use proper caution when opening attachments, clicking links, or res= ponding.


Abner:
  This change is good to me. Reviewed-by: Liming Gao <gaoliming@byo= soft.com.cn>

  But, this is not critical issue. So, I suggest to merge it after the= stable tag.

Thanks
Liming
> -----=D3=CA=BC=FE=D4=AD=BC=FE-----
> =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io <devel@edk2.groups.io> = =B4=FA=B1=ED Chang, Abner via
> groups.io
> =B7=A2=CB=CD=CA=B1=BC=E4: 2024=C4=EA5=D4=C216=C8=D5 8:50
> =CA=D5=BC=FE=C8=CB: Hsueh, Hong-Chih (Neo) <Hong-Chih.Hsueh@amd.com= >;
> devel@edk2.groups.io
> =B3=AD=CB=CD: michael.d.kinney@intel.com; gaoliming@byosoft.com.cn; > zhiguang.liu@intel.com; He, Jiangang <Jiangang.He@amd.com>
> =D6=F7=CC=E2: Re: [edk2-devel] [PATCH] MdePkg: Remove non-ASCII charac= ters from
> header file (BZ# 4775)
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Mike, Liming and Zhiguang,
> Could you please check this patch sent two weeks ago? The correspondin= g BZ
> ticket is 4775. We overlooked tracking this issue and missed the 20240= 5 stable
> release. As this impacts the build, do you think we can have a quick r= eview and
> approve it; having this change pulled in 202405 stable release? Otherw= ise we will
> have to wait until next stable release.
>
> Thanks
> Abner
>
> > -----Original Message-----
> > From: Hsueh, Hong-Chih (Neo) <Hong-Chih.Hsueh@amd.com>
> > Sent: Thursday, May 2, 2024 3:31 AM
> > To: devel@edk2.groups.io
> > Cc: michael.d.kinney@intel.com; gaoliming@byosoft.com.cn;
> > zhiguang.liu@intel.com; He, Jiangang <Jiangang.He@amd.com>;= Chang,
> > Abner <Abner.Chang@amd.com>; Hsueh, Hong-Chih (Neo) <Hon= g-
> > Chih.Hsueh@amd.com>
> > Subject: [PATCH] MdePkg: Remove non-ASCII characters from header = file
> >
> > Cc: Jiangang He <jiangang.he@amd.com>
> > Signed-off-by: Neo Hsueh <Hong-Chih.Hsueh@amd.com>
> > ---
> >  MdePkg/Include/Register/Amd/Cpuid.h    =           | 4 ++--
> >  MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 8 ++++--= --
> >  2 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/MdePkg/Include/Register/Amd/Cpuid.h
> > b/MdePkg/Include/Register/Amd/Cpuid.h
> > index add43c40aa..51fa9f235c 100644
> > --- a/MdePkg/Include/Register/Amd/Cpuid.h
> > +++ b/MdePkg/Include/Register/Amd/Cpuid.h
> > @@ -46,9 +46,9 @@ CPUID Signature Information
> >    CPUID Extended Topology Enumeration
> >
> >    @note
> > -  Reference: AMD64 Architecture Programmer=A1=AFs Manual Vo= lume 3: General-
> > Purpose and System Instructions,
> > +  Reference: AMD64 Architecture Programmer's Manual Volume = 3: General-
> > Purpose and System Instructions,
> >           =     Revision 3.35 Appendix E,
> > -  E.4.24 Function 8000_0026=A1=AAExtended CPU Topology:
> > +  E.4.24 Function 8000_0026-Extended CPU Topology:
> >      CPUID Fn8000_0026 reports extended = topology information for logical
> > processors, including
> >      asymmetric and heterogenous topolog= y descriptions. Individual logical
> > processors may report
> >      different values in systems with as= ynchronous and heterogeneous
> > topologies.
> > diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> > b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> > index 756e7c86ec..4715c59dc4 100644
> > --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> > +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> > @@ -5733,9 +5733,9 @@ typedef union {
> >      /// [Bit 7:4] TME Policy/Encryption= Algorithm: Only algorithms
> enumerated
> > in
> >      /// IA32_TME_CAPABILITY are allowed= .
> >      /// For example:
> > -    ///   0000 =A8C AES-XTS-128.
> > -    ///   0001 =A8C AES-XTS-128 with in= tegrity.
> > -    ///   0010 =A8C AES-XTS-256.
> > +    ///   0000 - AES-XTS-128.
> > +    ///   0001 - AES-XTS-128 with integ= rity.
> > +    ///   0010 - AES-XTS-256.
> >      ///   Other values are in= valid.
> >      ///
> >      UINT32    TmePolicy = : 4;
> > @@ -5756,7 +5756,7 @@ typedef union {
> >      /// Similar to enumeration, this is= an encoded value.
> >      /// Writing a value greater than MK= _TME_MAX_KEYID_BITS will result in
> > #GP.
> >      /// Writing a non-zero value to thi= s field will #GP if bit 1 of EAX (Hardware
> > -    /// Encryption Enable) is not also set to =A1= =AE1, as encryption hardware must
> be
> > +    /// Encryption Enable) is not also set to 1, = as encryption hardware must
> be
> >      /// enabled to use MKTME.
> >      /// Example: To support 255 keys, t= his field would be set to a value of 8.
> >      ///
> > --
> > 2.40.0.windows.1
>
>
>
>
>



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