From: "Heng Luo" <heng.luo@intel.com>
To: Takuto Naito <naitaku@gmail.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>
Subject: Re: [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5
Date: Mon, 22 Feb 2021 01:06:36 +0000 [thread overview]
Message-ID: <DM5PR1101MB2362B1F274DDA7FDF6A689A493819@DM5PR1101MB2362.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210221151020.40242-3-naitaku@gmail.com>
Reviewed-by: Heng Luo <heng.luo@intel.com>
> -----Original Message-----
> From: Takuto Naito <naitaku@gmail.com>
> Sent: Sunday, February 21, 2021 11:10 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com>
> Subject: [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224
>
> - Fix the Teton Glacier Endpoint entry in mPciDeviceTable
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Heng Luo <heng.luo@intel.com>
> Signed-off-by: Takuto Naito <naitaku@gmail.com>
> ---
>
> Notes:
> v2:
> - Split the v1 patch into 2 patches,
> One is for Platform/Intel/TigerlakeOpenBoardPkg,
> another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg.
>
> .../DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> index 577e436e32..1553d2e2aa 100644
> ---
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> @@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED
> PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
> //
> // Teton Glacier Endpoint
> //
> - { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5,
> 0, 0, 0, 0 },
> + { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5,
> 0, 0 },
>
> //
> // End of Table
> --
> 2.30.1
next prev parent reply other threads:[~2021-02-22 1:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito
2021-02-21 15:10 ` [PATCH v2 1/2] TigerlakeOpenBoardPkg: " Takuto Naito
2021-02-22 1:06 ` Heng Luo
2021-02-21 15:10 ` [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: " Takuto Naito
2021-02-22 1:06 ` Heng Luo [this message]
2021-02-22 1:09 ` [PATCH v2 0/2] TigerlakeOpenBoard: " Heng Luo
2021-02-22 22:21 ` Nate DeSimone
2021-02-22 22:27 ` Nate DeSimone
2021-02-23 17:01 ` Takuto Naito
2021-02-24 1:13 ` [edk2-devel] " Heng Luo
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