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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Heng Luo > -----Original Message----- > From: Takuto Naito > Sent: Sunday, February 21, 2021 11:10 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L ; Luo, Heng > Subject: [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors wit= h GCC5 >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3224 >=20 > - Fix the Teton Glacier Endpoint entry in mPciDeviceTable >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Cc: Heng Luo > Signed-off-by: Takuto Naito > --- >=20 > Notes: > v2: > - Split the v1 patch into 2 patches, > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg= . >=20 > .../DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchP= cieRp > PolicyLib/DxePchPcieRpPolicyLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchP= cieRp > PolicyLib/DxePchPcieRpPolicyLib.c > index 577e436e32..1553d2e2aa 100644 > --- > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchP= cieRp > PolicyLib/DxePchPcieRpPolicyLib.c > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchP= cieRp > PolicyLib/DxePchPcieRpPolicyLib.c > @@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED > PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] =3D { > // > // Teton Glacier Endpoint > // > - { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, = 0x3C, 0, 5, > 0, 0, 0, 0 }, > + { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, = 0x3C, 0, 5, > 0, 0 }, >=20 > // > // End of Table > -- > 2.30.1